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Commit 777894d8 authored by Andrea Boccardi's avatar Andrea Boccardi
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trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
View file @ 777894d8
Release 12.3 ngdbuild M.70d (nt) Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3
SFpga.ngd SFpga.ngc SFpga.ngd
Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ... Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ...
Gathering constraint information from source properties... Gathering constraint information from source properties...
...@@ -49,10 +49,10 @@ NGDBUILD Design Results Summary: ...@@ -49,10 +49,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 16 Number of warnings: 16
Total memory usage is 87012 kilobytes Total memory usage is 155028 kilobytes
Writing NGD file "SFpga.ngd" ... Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 5 sec Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"... Writing NGDBUILD log file "SFpga.bld"...
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ 777894d8
...@@ -210,3 +210,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 - ...@@ -210,3 +210,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
View file @ 777894d8
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:01 2011 Fri Jan 28 15:08:32 2011
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.par
View file @ 777894d8
Release 12.3 par M.70d (nt) Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Fri Jan 28 11:49:02 2011 PCBE13225:: Fri Jan 28 15:05:49 2011
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
...@@ -26,7 +26,7 @@ Slice Logic Utilization: ...@@ -26,7 +26,7 @@ Slice Logic Utilization:
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1% Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1% Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616 Number using O6 output only: 616
Number using O5 output only: 83 Number using O5 output only: 83
...@@ -42,17 +42,17 @@ Slice Logic Utilization: ...@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 2 Number using O5 and O6: 2
Number used exclusively as route-thrus: 14 Number used exclusively as route-thrus: 12
Number with same-slice register load: 9 Number with same-slice register load: 7
Number with same-slice carry load: 5 Number with same-slice carry load: 5
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1% Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060 Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 372 out of 1,060 35% Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 209 out of 1,060 19% Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 479 out of 1,060 45% Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0% to control set restrictions: 0 out of 184,304 0%
...@@ -99,8 +99,8 @@ Specific Feature Utilization: ...@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High Overall effort level (-ol): High
Router effort level (-rl): High Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 20 secs Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 20 secs Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal DdsRamSwpOvr_i_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal DdsRamSwpOvr_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PcbRev_ib8<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal PcbRev_ib8<0>_IBUF has no load. PAR will not attempt to route this signal.
...@@ -154,29 +154,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O ...@@ -154,29 +154,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router Starting Router
Phase 1 : 4748 unrouted; REAL time: 23 secs Phase 1 : 4750 unrouted; REAL time: 11 secs
Phase 2 : 4243 unrouted; REAL time: 30 secs Phase 2 : 4245 unrouted; REAL time: 14 secs
Phase 3 : 1611 unrouted; REAL time: 5 mins 41 secs Phase 3 : 1604 unrouted; REAL time: 2 mins 34 secs
Phase 4 : 1611 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 52 secs Phase 4 : 1604 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 39 secs
Updating file: SFpga.ncd with current fully routed design. Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 55 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 41 secs
Total REAL time to Router completion: 5 mins 56 secs Total REAL time to Router completion: 2 mins 41 secs
Total CPU time to Router completion: 5 mins 54 secs Total CPU time to Router completion: 2 mins 40 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -194,14 +194,14 @@ Generating Clock Report ...@@ -194,14 +194,14 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 203 | 0.325 | 1.693 | | VcTcXo_ik_IBUF_BUFG | BUFGMUX_X3Y16| No | 204 | 0.325 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 6 | 0.009 | 1.690 | | Si57x_BUFG | BUFGMUX_X2Y4| No | 6 | 0.009 | 1.690 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.189 | 1.692 | | SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.190 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | | |i_Core/i_VmeInterfac | | | | | |
| e/Stb_oq | Local| | 17 | 0.000 | 2.404 | | e/Stb_oq | Local| | 17 | 0.000 | 2.145 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
...@@ -220,7 +220,7 @@ Asterisk (*) preceding a constraint indicates it was not met. ...@@ -220,7 +220,7 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.649ns| 4.684ns| 0| 0 TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 3.404ns| 4.929ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.439ns| | 0| 0 lk_ik" 120 MHz HIGH 50% | HOLD | 0.439ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 5.833ns| 2.500ns| 0| 0 TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | MINPERIOD | 5.833ns| 2.500ns| 0| 0
...@@ -241,10 +241,10 @@ All signals are completely routed. ...@@ -241,10 +241,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 49 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 49 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 5 mins 59 secs Total REAL time to PAR completion: 2 mins 43 secs
Total CPU time to PAR completion: 5 mins 58 secs Total CPU time to PAR completion: 2 mins 42 secs
Peak Memory Usage: 366 MB Peak Memory Usage: 559 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ 777894d8
//! ************************************************************************** //! **************************************************************************
// Written by: Map M.70d on Fri Jan 28 11:48:58 2011 // Written by: Map M.70d on Fri Jan 28 15:05:46 2011
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ 777894d8
...@@ -329,4 +329,4 @@ ...@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.649" best="4.684" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.439" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="6.152" best="2.181" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.464" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.404" best="4.929" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.439" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="6.152" best="2.181" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.464" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.syr
View file @ 777894d8
Release 12.3 - xst M.70d (nt) Release 12.3 - xst M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp --> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst --> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.16 secs Total CPU time to Xst completion: 0.08 secs
--> Reading design: SFpga.prj --> Reading design: SFpga.prj
...@@ -1032,7 +1032,7 @@ Delay: 2.365ns (Levels of Logic = 25) ...@@ -1032,7 +1032,7 @@ Delay: 2.365ns (Levels of Logic = 25)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'VcTcXo_ik' Timing constraint: Default period analysis for Clock 'VcTcXo_ik'
Clock period: 6.551ns (frequency: 152.654MHz) Clock period: 6.551ns (frequency: 152.654MHz)
Total number of paths / destination ports: 26774 / 1542 Total number of paths / destination ports: 26773 / 1542
------------------------------------------------------------------------- -------------------------------------------------------------------------
Delay: 6.551ns (Levels of Logic = 10) Delay: 6.551ns (Levels of Logic = 10)
Source: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF) Source: i_Core/i_SpiMasterWB/Config2_qb32_2 (FF)
...@@ -1121,7 +1121,7 @@ Offset: 12.206ns (Levels of Logic = 10) ...@@ -1121,7 +1121,7 @@ Offset: 12.206ns (Levels of Logic = 10)
LUT6:I1->O 6 0.254 0.973 i_Core/i_VmeInterface/GapError1 (i_Core/i_VmeInterface/GapError) LUT6:I1->O 6 0.254 0.973 i_Core/i_VmeInterface/GapError1 (i_Core/i_VmeInterface/GapError)
LUT4:I1->O 1 0.235 1.035 i_Core/i_VmeInterface/Mmux_BoardBaseAddr_b521 (i_Core/i_VmeInterface/BoardBaseAddr_b5<1>) LUT4:I1->O 1 0.235 1.035 i_Core/i_VmeInterface/Mmux_BoardBaseAddr_b521 (i_Core/i_VmeInterface/BoardBaseAddr_b5<1>)
LUT6:I0->O 1 0.254 0.808 i_Core/i_VmeInterface/ValidRWBA_a81 (i_Core/i_VmeInterface/ValidRWBA_a8) LUT6:I0->O 1 0.254 0.808 i_Core/i_VmeInterface/ValidRWBA_a81 (i_Core/i_VmeInterface/ValidRWBA_a8)
LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N294) LUT6:I3->O 1 0.235 1.035 i_Core/i_VmeInterface/ValidRWBA_a83_SW0 (N296)
LUT6:I0->O 3 0.254 0.879 i_Core/i_VmeInterface/ValidRWBA_a83 (i_Core/i_VmeInterface/ValidRWBA_a) LUT6:I0->O 3 0.254 0.879 i_Core/i_VmeInterface/ValidRWBA_a83 (i_Core/i_VmeInterface/ValidRWBA_a)
LUT4:I1->O 1 0.235 0.580 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1_SW0 (N42) LUT4:I1->O 1 0.235 0.580 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1_SW0 (N42)
LUT6:I5->O 8 0.254 1.031 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1 (N3) LUT6:I5->O 8 0.254 1.031 i_Core/i_VmeInterface/State_q_FSM_FFd2-In1 (N3)
...@@ -1254,12 +1254,12 @@ i_Core/i_VmeInterface/Stb_oq| 2.049| | | | ...@@ -1254,12 +1254,12 @@ i_Core/i_VmeInterface/Stb_oq| 2.049| | | |
========================================================================= =========================================================================
Total REAL time to Xst completion: 28.00 secs Total REAL time to Xst completion: 18.00 secs
Total CPU time to Xst completion: 27.13 secs Total CPU time to Xst completion: 17.41 secs
--> -->
Total memory usage is 155300 kilobytes Total memory usage is 280792 kilobytes
Number of errors : 0 ( 0 filtered) Number of errors : 0 ( 0 filtered)
Number of warnings : 129 ( 0 filtered) Number of warnings : 129 ( 0 filtered)
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
View file @ 777894d8
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:02 2011 Fri Jan 28 15:08:33 2011
All signals are completely routed. All signals are completely routed.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_envsettings.html
View file @ 777894d8
...@@ -15,17 +15,17 @@ ...@@ -15,17 +15,17 @@
</tr> </tr>
<tr> <tr>
<td>PATHEXT</td> <td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td> <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr> </tr>
<tr> <tr>
<td>Path</td> <td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
</tr> </tr>
<tr> <tr>
<td>XILINX</td> <td>XILINX</td>
...@@ -35,13 +35,6 @@ ...@@ -35,13 +35,6 @@
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td> <td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr> </tr>
<tr> <tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td> <td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td> <td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td> <td>C:\Xilinx\12.3\ISE_DS\ISE</td>
...@@ -515,31 +508,31 @@ ...@@ -515,31 +508,31 @@
</tr> </tr>
<tr> <tr>
<td>CPU Architecture/Speed</td> <td>CPU Architecture/Speed</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td> <td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
</tr> </tr>
<tr> <tr>
<td>Host</td> <td>Host</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
<td>bqplv2</td> <td>PCBE13225</td>
</tr> </tr>
<tr> <tr>
<td>OS Name</td> <td>OS Name</td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
<td>Microsoft Windows XP Professional</td> <td>Microsoft </td>
</tr> </tr>
<tr> <tr>
<td>OS Release</td> <td>OS Release</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
<td>Service Pack 3 (build 2600)</td> <td>major release (build 7600)</td>
</tr> </tr>
</TABLE> </TABLE>
</BODY> </HTML> </BODY> </HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map
View file @ 777894d8
Release 12.3 Map M.70d (nt) Release 12.3 Map M.70d (nt64)
Xilinx Map Application Log File for Design 'SFpga' Xilinx Map Application Log File for Design 'SFpga'
Design Information Design Information
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Jan 28 11:48:01 2011 Mapped Date : Fri Jan 28 15:05:14 2011
Mapping design into LUTs... Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
...@@ -87,58 +87,58 @@ Updating timing models... ...@@ -87,58 +87,58 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp). (.mrp).
Running timing-driven placement... Running timing-driven placement...
Total REAL time at the beginning of Placer: 25 secs Total REAL time at the beginning of Placer: 12 secs
Total CPU time at the beginning of Placer: 24 secs Total CPU time at the beginning of Placer: 11 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:cc31257e) REAL time: 32 secs Phase 1.1 Initial Placement Analysis (Checksum:cc31257e) REAL time: 16 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
and 2 are not locked. If you would like to print the names of these IOs, and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:cc31257e) REAL time: 33 secs Phase 2.7 Design Feasibility Check (Checksum:cc31257e) REAL time: 17 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:cc31257e) REAL time: 33 secs Phase 3.31 Local Placement Optimization (Checksum:cc31257e) REAL time: 17 secs
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
... ...
Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:aaca966e) REAL time: 40 secs (Checksum:aaca966e) REAL time: 21 secs
Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:aaca966e) REAL time: 40 secs Phase 5.36 Local Placement Optimization (Checksum:aaca966e) REAL time: 21 secs
Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:aaca966e) REAL time: 40 secs Phase 6.30 Global Clock Region Assignment (Checksum:aaca966e) REAL time: 21 secs
Phase 7.3 Local Placement Optimization Phase 7.3 Local Placement Optimization
... ...
Phase 7.3 Local Placement Optimization (Checksum:98519d88) REAL time: 41 secs Phase 7.3 Local Placement Optimization (Checksum:98519d88) REAL time: 22 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:aaea37e3) REAL time: 41 secs Phase 8.5 Local Placement Optimization (Checksum:aaea37e3) REAL time: 22 secs
Phase 9.8 Global Placement Phase 9.8 Global Placement
.... .........
.................... ..........................................
Phase 9.8 Global Placement (Checksum:f9eafb45) REAL time: 44 secs Phase 9.8 Global Placement (Checksum:de2814d1) REAL time: 24 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:f9eafb45) REAL time: 44 secs Phase 10.5 Local Placement Optimization (Checksum:de2814d1) REAL time: 24 secs
Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:af7d4423) REAL time: 45 secs Phase 11.18 Placement Optimization (Checksum:b777ab7) REAL time: 25 secs
Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:af7d4423) REAL time: 45 secs Phase 12.5 Local Placement Optimization (Checksum:b777ab7) REAL time: 25 secs
Phase 13.34 Placement Validation Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:1a6c36bd) REAL time: 46 secs Phase 13.34 Placement Validation (Checksum:f00dac81) REAL time: 25 secs
Total REAL time to Placer completion: 55 secs Total REAL time to Placer completion: 30 secs
Total CPU time to Placer completion: 55 secs Total CPU time to Placer completion: 29 secs
Running post-placement packing... Running post-placement packing...
Writing output files... Writing output files...
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete. WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
...@@ -253,7 +253,7 @@ Slice Logic Utilization: ...@@ -253,7 +253,7 @@ Slice Logic Utilization:
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1% Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1% Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616 Number using O6 output only: 616
Number using O5 output only: 83 Number using O5 output only: 83
...@@ -269,17 +269,17 @@ Slice Logic Utilization: ...@@ -269,17 +269,17 @@ Slice Logic Utilization:
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 2 Number using O5 and O6: 2
Number used exclusively as route-thrus: 14 Number used exclusively as route-thrus: 12
Number with same-slice register load: 9 Number with same-slice register load: 7
Number with same-slice carry load: 5 Number with same-slice carry load: 5
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1% Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060 Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 372 out of 1,060 35% Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 209 out of 1,060 19% Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 479 out of 1,060 45% Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of unique control sets: 27 Number of unique control sets: 27
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 71 out of 184,304 1% to control set restrictions: 71 out of 184,304 1%
...@@ -325,9 +325,9 @@ Specific Feature Utilization: ...@@ -325,9 +325,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.41 Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 396 MB Peak Memory Usage: 618 MB
Total REAL time to MAP completion: 58 secs Total REAL time to MAP completion: 32 secs
Total CPU time to MAP completion: 58 secs Total CPU time to MAP completion: 31 secs
Mapping completed. Mapping completed.
See MAP report file "SFpga_map.mrp" for details. See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp
View file @ 777894d8
Release 12.3 Map M.70d (nt) Release 12.3 Map M.70d (nt64)
Xilinx Mapping Report File for Design 'SFpga' Xilinx Mapping Report File for Design 'SFpga'
Design Information Design Information
...@@ -10,7 +10,7 @@ Target Device : xc6slx150t ...@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676 Target Package : fgg676
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $ Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Jan 28 11:48:01 2011 Mapped Date : Fri Jan 28 15:05:14 2011
Design Summary Design Summary
-------------- --------------
...@@ -22,7 +22,7 @@ Slice Logic Utilization: ...@@ -22,7 +22,7 @@ Slice Logic Utilization:
Number used as Latches: 0 Number used as Latches: 0
Number used as Latch-thrus: 0 Number used as Latch-thrus: 0
Number used as AND/OR logics: 0 Number used as AND/OR logics: 0
Number of Slice LUTs: 851 out of 92,152 1% Number of Slice LUTs: 849 out of 92,152 1%
Number used as logic: 823 out of 92,152 1% Number used as logic: 823 out of 92,152 1%
Number using O6 output only: 616 Number using O6 output only: 616
Number using O5 output only: 83 Number using O5 output only: 83
...@@ -38,17 +38,17 @@ Slice Logic Utilization: ...@@ -38,17 +38,17 @@ Slice Logic Utilization:
Number using O6 output only: 4 Number using O6 output only: 4
Number using O5 output only: 0 Number using O5 output only: 0
Number using O5 and O6: 2 Number using O5 and O6: 2
Number used exclusively as route-thrus: 14 Number used exclusively as route-thrus: 12
Number with same-slice register load: 9 Number with same-slice register load: 7
Number with same-slice carry load: 5 Number with same-slice carry load: 5
Number with other load: 0 Number with other load: 0
Slice Logic Distribution: Slice Logic Distribution:
Number of occupied Slices: 392 out of 23,038 1% Number of occupied Slices: 386 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,060 Number of LUT Flip Flop pairs used: 1,046
Number with an unused Flip Flop: 372 out of 1,060 35% Number with an unused Flip Flop: 356 out of 1,046 34%
Number with an unused LUT: 209 out of 1,060 19% Number with an unused LUT: 197 out of 1,046 18%
Number of fully used LUT-FF pairs: 479 out of 1,060 45% Number of fully used LUT-FF pairs: 493 out of 1,046 47%
Number of unique control sets: 27 Number of unique control sets: 27
Number of slice register sites lost Number of slice register sites lost
to control set restrictions: 71 out of 184,304 1% to control set restrictions: 71 out of 184,304 1%
...@@ -94,9 +94,9 @@ Specific Feature Utilization: ...@@ -94,9 +94,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 3.41 Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 396 MB Peak Memory Usage: 618 MB
Total REAL time to MAP completion: 58 secs Total REAL time to MAP completion: 32 secs
Total CPU time to MAP completion: 58 secs Total CPU time to MAP completion: 31 secs
Table of Contents Table of Contents
----------------- -----------------
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.xrpt
View file @ 777894d8
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3"> <document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Fri Jan 28 11:49:00 2011"> <application stringID="Map" timeStamp="Fri Jan 28 15:05:47 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/> <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="2">
<item stringID="variable" value="XILINX"/> <item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row> </row>
<row stringID="row" value="3"> <row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/> <item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row> </row>
<row stringID="row" value="5"> <row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/> <item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row> </row>
<row stringID="row" value="6"> <row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/> <item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row> </row>
</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/> <item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/> <item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item> </item>
<item stringID="User_EnvHost" value="bqplv2"/> <item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/> <item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3389 MHz"/> <item stringID="speed" value="3158 MHz"/>
</row> </row>
</table> </table>
</section> </section>
...@@ -120,9 +116,9 @@ ...@@ -120,9 +116,9 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/> <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/> <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/> <item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="405884"/> <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="632572"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="58 secs "/> <item stringID="MAP_TOTAL_REAL_TIME" value="32 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="58 secs "/> <item stringID="MAP_TOTAL_CPU_TIME" value="31 secs "/>
</section> </section>
<section stringID="MAP_SLICE_REPORTING"> <section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="765"> <item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="765">
...@@ -131,7 +127,7 @@ ...@@ -131,7 +127,7 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item> </item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="851"> <item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="849">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="83"/> <item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="83"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="616"/> <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="616"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="124"/> <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="124"/>
...@@ -148,21 +144,21 @@ ...@@ -148,21 +144,21 @@
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="4"/> <item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="4"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="2"/> <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="2"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="5"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="9"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="9"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="7"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="5"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="5"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/> <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item> </item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="392"> <item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="386">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="51"/> <item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="51"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/> <item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="337"/> <item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="331"/>
</item> </item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1060"> <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1046">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="372"/> <item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="356"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="209"/> <item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="197"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="479"/> <item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="493"/>
</item> </item>
</section> </section>
<section stringID="MAP_IOB_REPORTING"> <section stringID="MAP_IOB_REPORTING">
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt
View file @ 777894d8
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3"> <document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Fri Jan 28 11:47:59 2011"> <application stringID="NgdBuild" timeStamp="Fri Jan 28 15:05:13 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
</row> </row>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/> <item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/> <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="2">
<item stringID="variable" value="XILINX"/> <item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row> </row>
<row stringID="row" value="3"> <row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/> <item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row> </row>
<row stringID="row" value="5"> <row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/> <item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row> </row>
<row stringID="row" value="6"> <row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/> <item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row> </row>
</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/> <item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/> <item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item> </item>
<item stringID="User_EnvHost" value="bqplv2"/> <item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/> <item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3389 MHz"/> <item stringID="speed" value="3158 MHz"/>
</row> </row>
</table> </table>
</section> </section>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ 777894d8
#Release 12.3 - par M.70d (nt) #Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Fri Jan 28 11:55:00 2011 #Fri Jan 28 15:08:32 2011
# #
## NOTE: This file is designed to be imported into a spreadsheet program ## NOTE: This file is designed to be imported into a spreadsheet program
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ 777894d8
Release 12.3 - par M.70d (nt) Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:01 2011 Fri Jan 28 15:08:32 2011
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ 777894d8
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="59"> <DesignSummary rev="61">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt
View file @ 777894d8
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3"> <document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Fri Jan 28 11:47:26 2011"> <application stringID="Xst" timeStamp="Fri Jan 28 15:04:51 2011">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
<column stringID="value"/> <column stringID="value"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="variable" value="Path"/> <item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files\PuTTY"/>
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</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="2">
<item stringID="variable" value="XILINX"/> <item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row> </row>
<row stringID="row" value="3"> <row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/> <item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row> </row>
<row stringID="row" value="5"> <row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/> <item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row> </row>
<row stringID="row" value="6"> <row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/> <item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/> <item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row> </row>
</table> </table>
<item stringID="User_EnvOs" value="OS Information"> <item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/> <item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/> <item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item> </item>
<item stringID="User_EnvHost" value="bqplv2"/> <item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu"> <table stringID="User_EnvCpu">
<column stringID="arch"/> <column stringID="arch"/>
<column stringID="speed"/> <column stringID="speed"/>
<row stringID="row" value="0"> <row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/> <item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3389 MHz"/> <item stringID="speed" value="3158 MHz"/>
</row> </row>
</table> </table>
</section> </section>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise
View file @ 777894d8
...@@ -111,7 +111,7 @@ ...@@ -111,7 +111,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1296211673" xil_pn:in_ck="-394197636941444327" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1296211644"> <transform xil_pn:end_ts="1296223509" xil_pn:in_ck="-394197636941444327" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1296223489">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -133,7 +133,7 @@ ...@@ -133,7 +133,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1296211680" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1296211673"> <transform xil_pn:end_ts="1296223514" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1296223509">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -143,10 +143,12 @@ ...@@ -143,10 +143,12 @@
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1296211741" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1296211680"> <transform xil_pn:end_ts="1296223548" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1296223514">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SFpga.pcf"/> <outfile xil_pn:name="SFpga.pcf"/>
<outfile xil_pn:name="SFpga_map.map"/> <outfile xil_pn:name="SFpga_map.map"/>
<outfile xil_pn:name="SFpga_map.mrp"/> <outfile xil_pn:name="SFpga_map.mrp"/>
...@@ -157,7 +159,7 @@ ...@@ -157,7 +159,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/> <outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1296212125" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1296211741"> <transform xil_pn:end_ts="1296223725" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1296223548">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -172,7 +174,7 @@ ...@@ -172,7 +174,7 @@
<outfile xil_pn:name="SFpga_par.xrpt"/> <outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform> </transform>
<transform xil_pn:end_ts="1296212185" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-774614059244361160" xil_pn:start_ts="1296212125"> <transform xil_pn:end_ts="1296223769" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-774614059244361160" xil_pn:start_ts="1296223725">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -188,13 +190,9 @@ ...@@ -188,13 +190,9 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1294318860" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1294318858"> <transform xil_pn:end_ts="1296223783" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1296223781">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="sfpga.isc"/> <outfile xil_pn:name="sfpga.isc"/>
</transform> </transform>
<transform xil_pn:end_ts="1294819273" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1294819271"> <transform xil_pn:end_ts="1294819273" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1294819271">
...@@ -219,7 +217,7 @@ ...@@ -219,7 +217,7 @@
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
</transform> </transform>
<transform xil_pn:end_ts="1296212125" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1296212103"> <transform xil_pn:end_ts="1296223725" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1296223714">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/> <outfile xil_pn:name="SFpga.twr"/>
......
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ 777894d8
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1296211672 C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1296223508
OK OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs
View file @ 777894d8
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/VmeToWishBone.v\&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/InterruptManagerWB.v\&quot; into library work</arg>
</msg> </msg>
</messages> </messages>
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport
View file @ 777894d8
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2011-01-28T11:09:00</DateModified> <DateModified>2011-01-28T15:02:31</DateModified>
<ModuleName>SFpga</ModuleName> <ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-20T13:49:08</SummaryTimeStamp> <SummaryTimeStamp>2010-12-20T13:49:08</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath> <SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SystemFpga.projectmgr
View file @ 777894d8
...@@ -36,12 +36,14 @@ ...@@ -36,12 +36,14 @@
<ClosedNodes> <ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion> <ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes> </ClosedNodes>
<SelectedItems/> <SelectedItems>
<SelectedItem>VmeToWishBone.v</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000040101000100000000000000000000000064ffffffff000000810000000000000004000000ac00000001000000000000002400000001000000000000006600000001000000000000006c0000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000019a000000040101000100000000000000000000000064ffffffff000000810000000000000004000000ac0000000100000000000000240000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>AddrDecoderWBSys.v</CurrentItem> <CurrentItem>VmeToWishBone.v</CurrentItem>
</ItemView> </ItemView>
<ItemView guiview="Library" > <ItemView guiview="Library" >
<ClosedNodes> <ClosedNodes>
...@@ -50,7 +52,7 @@ ...@@ -50,7 +52,7 @@
<SelectedItems/> <SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000001a2000000010001000100000000000000000000000064ffffffff000000810000000000000001000001a20000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem> <CurrentItem>work</CurrentItem>
</ItemView> </ItemView>
...@@ -64,13 +66,13 @@ ...@@ -64,13 +66,13 @@
<ClosedNode>Implement Design/Translate</ClosedNode> <ClosedNode>Implement Design/Translate</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>Design Summary/Reports</SelectedItem> <SelectedItem>Configure Target Device</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >20</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >22</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000191000000010000000100000000000000000000000064ffffffff000000810000000000000001000001910000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000189000000010000000100000000000000000000000064ffffffff000000810000000000000001000001890000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Design Summary/Reports</CurrentItem> <CurrentItem>Configure Target Device</CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes> <ClosedNodes>
......
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html
View file @ 777894d8
...@@ -2,30 +2,30 @@ ...@@ -2,30 +2,30 @@
<xtag-section name="ParStatistics"> <xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1355</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1355</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4356</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4360</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4356</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4360</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>127</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>127</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>23.6 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>29.9 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>14.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>339.9 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>153.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>351.1 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>158.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
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<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>354.5 sec</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>160.6 sec</xtag-par-property-value></TD></TR>
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<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>14.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>14.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>22.4</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>22.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>14.3</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>14.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>10.9</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>11.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>6.7</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>7.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0615</xtag-par-property-value></TD></TR> <TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0635</xtag-par-property-value></TD></TR>
</xtag-section> </xtag-section>
</TABLE> </TABLE>
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn
View file @ 777894d8
Release 12.3 - Bitgen M.70d (nt) Release 12.3 - Bitgen M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx150t.nph' in environment Loading device for application Rf_Device from file '6slx150t.nph' in environment
C:\Xilinx\12.3\ISE_DS\ISE\. C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3 "SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf. Opened constraints file SFpga.pcf.
Fri Jan 28 11:55:36 2011 Fri Jan 28 15:08:51 2011
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:26 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:yes -b -g IEEE1532:Yes -g CRC:Enable -g Reset_on_err:No -g ConfigRate:26 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
WARNING:Bitgen:244 - A StartupClk setting other than JtagClk is being used to WARNING:Bitgen:244 - A StartupClk setting other than JtagClk is being used to
generate a bitstream in IEEE1532 format. The IEEE1532 option implies that generate a bitstream in IEEE1532 format. The IEEE1532 option implies that
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc
View file @ 777894d8
Release 12.3 Drc M.70d (nt) Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Jan 28 11:55:36 2011 Fri Jan 28 15:08:51 2011
drc -z SFpga.ncd SFpga.pcf drc -z SFpga.ncd SFpga.pcf
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.isc
View file @ 777894d8
This diff is collapsed.
trunk/firmware/XilinxISE/SystemFpga/sfpga.rbt
View file @ 777894d8
This diff is collapsed.
trunk/firmware/XilinxISE/SystemFpga/webtalk.log
View file @ 777894d8
...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ...@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information Project Information
-------------------- --------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=28 ProjectIteration=29
WebTalk Summary WebTalk Summary
---------------- ----------------
...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled. ...@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON. INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON. INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2011-01-28T11:56:25. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2011-01-28T15:09:29. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml
View file @ 777894d8
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Jan 28 11:55:26 2011"> <application name="pn" timeStamp="Fri Jan 28 15:08:46 2011">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/> <property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="28" type="project"/> <property name="ProjectIteration" value="29" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/> <property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/> <property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section> </section>
...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/> <property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/> <property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="28" type="process"/> <property name="PROP_intWbtProjectIteration" value="29" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> <property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
trunk/hdl/design/InterruptManagerWB.v
View file @ 777894d8
...@@ -157,8 +157,8 @@ wire [7:0] fpga_revision; ...@@ -157,8 +157,8 @@ wire [7:0] fpga_revision;
wire [15:0] date; wire [15:0] date;
assign fpga_version = 8'h00; assign fpga_version = 8'h00;
assign fpga_revision = 8'h01; assign fpga_revision = 8'h02;
assign date = {8'd6, 4'd10,4'd10}; assign date = {8'd27, 4'd1,4'd11};
assign Ack_oa = Stb_i&&Cyc_i; assign Ack_oa = Stb_i&&Cyc_i;
......
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