Commit 7b8bf263 authored by Andrea Boccardi's avatar Andrea Boccardi


parent cbef8cc2
......@@ -670,7 +670,7 @@ assign VAdjCs_on = SpiSS_nb32[1];
assign VAdjDin_o = SpiMoSi;
assign VAdjSClk_ok = SpiSClk_k;
assign VAdjSpi_o = 1'b1; //we keep it in SPI mode
assign VAdjInhibit_ozn = 1'bz; //we keep the generator on
assign VAdjInhibit_ozn = 1'b1; //we keep the generator on
assign SpiMiSo_b32[0] = PllDacDin_o; //in feedback as the module doesn't have a Dout: this way at least we read the last sent.
assign PllDacSynch_on = SpiSS_nb32[0];
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