Commit 8cac29ef authored by Andrea Boccardi's avatar Andrea Boccardi

minor changes in the structure of the project

parent b46b223e
module Generic4InputRegs (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output Ack_oa,
input [31:0] Reg0Value_ib32,
input [31:0] Reg1Value_ib32,
input [31:0] Reg2Value_ib32,
input [31:0] Reg3Value_ib32);
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ib32;
2'b01: Dat_oab32 = Reg1Value_ib32;
2'b10: Dat_oab32 = Reg2Value_ib32;
2'b11: Dat_oab32 = Reg3Value_ib32;
default: Dat_oab32 = Reg0Value_ib32;
endcase
endmodule
module Generic4InputRegs (
input Rst_irq,
input Cyc_i,
input Stb_i,
input [1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output Ack_oa,
input [31:0] Reg0Value_ib32,
input [31:0] Reg1Value_ib32,
input [31:0] Reg2Value_ib32,
input [31:0] Reg3Value_ib32);
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ib32;
2'b01: Dat_oab32 = Reg1Value_ib32;
2'b10: Dat_oab32 = Reg2Value_ib32;
2'b11: Dat_oab32 = Reg3Value_ib32;
default: Dat_oab32 = Reg0Value_ib32;
endcase
endmodule
\ No newline at end of file
......@@ -62,7 +62,7 @@ always @(posedge Clk_ik) begin
end
end
assign asynch_clk_change = clrn && ~interrupt_in[6];
assign asynch_clk_change = ~Rst_irq && ~interrupt_in[6];
initial osc_clk = 1;
......@@ -169,4 +169,4 @@ always @* case(Adr_ib2)
default: Dat_oab32 <= # dly 32'hdead_beef;
endcase
endmodule
endmodule
\ No newline at end of file
module Monostable (
input AsynchIn_ia,
input Clk_ik,
output reg SynchOutput_oq);
parameter g_CounterBits = 20;
reg AsynchIn_ax = 1'b0;
reg [2:0] AsynchInAX_db3 = 2'b0;
always @(posedge AsynchIn_ia) AsynchIn_ax <= #1 ~AsynchIn_ax;
always @(posedge Clk_ik) AsynchInAX_db3 <= #1 {AsynchInAX_db3[1:0], AsynchIn_ax};
wire SynchIn_p = ^AsynchInAX_qdb3[2:1];
reg [g_CounterBits-1:0] Counter_c = 'b0;
always @(posedge Clk_ik) begin
if (SynchIn_p) Counter_c <= #1 'b0;
else if (~&Counter_c) Counter_c <= #1 Counter_c + 1'b1;
end
always @(posedge Clk_ik) SynchOutput_oq <= #1 ~&Counter_c;
endmodule
module Monostable (
input AsynchIn_ia,
input Clk_ik,
output reg SynchOutput_oq);
parameter g_CounterBits = 20;
reg AsynchIn_ax = 1'b0;
reg [2:0] AsynchInAX_db3 = 2'b0;
always @(posedge AsynchIn_ia) AsynchIn_ax <= #1 ~AsynchIn_ax;
always @(posedge Clk_ik) AsynchInAX_db3 <= #1 {AsynchInAX_db3[1:0], AsynchIn_ax};
wire SynchIn_p = ^AsynchInAX_db3[2:0];
reg [g_CounterBits-1:0] Counter_c = 'b0;
always @(posedge Clk_ik) begin
if (SynchIn_p) Counter_c <= #1 'b0;
else if (~&Counter_c) Counter_c <= #1 Counter_c + 1'b1;
end
always @(posedge Clk_ik) SynchOutput_oq <= #1 ~&Counter_c;
endmodule
\ No newline at end of file
module Slv2SerWB (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input We_i,
input [20:0] Adr_ib21,
input [31:0] Dat_ib32,
input Stb_i,
output reg [31:0] Dat_ob32,
output reg Ack_o,
output SerClk_ok,
output SerDat_o,
output SerCntrl_o, //We, Cyc and Adr Rst are serialized on this line
output Stb_o,
input SerClk_ik,
input SerDat_i,
input Ack_i);
`define dly #1
reg [31:0] DatOutShReg_b32 = 32'h0,
DatInShReg_b32 = 32'h0,
CntrlShReg_b32 = 32'h2;
reg [31:0] StbShReg_b32 = 32'h2;
reg StbI_d, AckI_d;
always @(posedge Clk_ik)
if (Rst_irq) begin
AckI_d <= `dly 1'b0;
StbI_d <= `dly 1'b0;
end else begin
AckI_d <= `dly Ack_i;
StbI_d <= `dly Stb_i;
end
wire NewStbI_a = Stb_i && ~StbI_d;
always @(posedge Clk_ik) begin
DatOutShReg_b32 <= `dly {1'b0, DatOutShReg_b32[31:1]};
CntrlShReg_b32 <= `dly {1'b0, CntrlShReg_b32[31:1]};
StbShReg_b32 <= `dly {1'b0, Stb_i, StbShReg_b32[30:1]};
if (Rst_irq) begin
DatOutShReg_b32 <= `dly 32'h0;
CntrlShReg_b32 <= `dly 32'h4;
StbShReg_b32 <= `dly 'h2;
end else if (NewStbI_a) begin
DatOutShReg_b32 <= `dly Dat_ib32;
CntrlShReg_b32 <= `dly {Rst_irq, Cyc_i, We_i, 8'b0, Adr_ib21}; //Rst is useless here, but is just for documentation that i keep it
end
end
assign SerDat_o = DatOutShReg_b32[0];
assign SerCntrl_o = CntrlShReg_b32[0];
assign Stb_o = StbShReg_b32[0];
assign SerClk_ok = ~Clk_ik;
reg [2:0] AckI_d3;
always @(posedge SerClk_ik)
if (Rst_irq) begin
AckI_d3 <= `dly 'b0;
end else begin
AckI_d3 <= `dly {AckI_d3[1:0], Ack_i};
end
wire NewAckI_a = AckI_d3[2:1]==2'b01;
reg [31:0] Dat_xb32;
always @(posedge SerClk_ik) DatInShReg_b32 <= `dly {SerDat_i, DatInShReg_b32[31:1]};
always @(posedge SerClk_ik) if (NewAckI_a) Dat_xb32 <= `dly DatInShReg_b32;
reg [2:0] AckI_xb3;
always @(posedge SerClk_ik) AckI_xb3[2] <= `dly Ack_i;
always @(posedge Clk_ik) AckI_xb3[1:0]<= `dly AckI_xb3[2:1];
always @(posedge Clk_ik) if (AckI_xb3[0]) Dat_ob32 <= `dly Dat_xb32;
always @(posedge Clk_ik) Ack_o <= `dly AckI_xb3[0];
endmodule
module Slv2SerWB (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input We_i,
input [20:0] Adr_ib21,
input [31:0] Dat_ib32,
input Stb_i,
output reg [31:0] Dat_ob32,
output reg Ack_o,
output SerClk_ok,
output SerDat_o,
output SerCntrl_o, //We, Cyc and Adr Rst are serialized on this line
output Stb_o,
input SerClk_ik,
input SerDat_i,
input Ack_i);
`define dly #1
reg [31:0] DatOutShReg_b32 = 32'h0,
DatInShReg_b32 = 32'h0,
CntrlShReg_b32 = 32'h2;
reg [31:0] StbShReg_b32 = 32'h2;
reg StbI_d;
always @(posedge Clk_ik)
if (Rst_irq) begin
StbI_d <= `dly 1'b0;
end else begin
StbI_d <= `dly Stb_i;
end
wire NewStbI_a = Stb_i && ~StbI_d;
always @(posedge Clk_ik) begin
DatOutShReg_b32 <= `dly {1'b0, DatOutShReg_b32[31:1]};
CntrlShReg_b32 <= `dly {1'b0, CntrlShReg_b32[31:1]};
StbShReg_b32 <= `dly {1'b0, Stb_i, StbShReg_b32[30:1]};
if (Rst_irq) begin
DatOutShReg_b32 <= `dly 32'h0;
CntrlShReg_b32 <= `dly 32'h4;
StbShReg_b32 <= `dly 'h2;
end else if (NewStbI_a) begin
DatOutShReg_b32 <= `dly Dat_ib32;
CntrlShReg_b32 <= `dly {Rst_irq, Cyc_i, We_i, 8'b0, Adr_ib21}; //Rst is useless here, but is just for documentation that i keep it
end
end
assign SerDat_o = DatOutShReg_b32[0];
assign SerCntrl_o = CntrlShReg_b32[0];
assign Stb_o = StbShReg_b32[0];
assign SerClk_ok = ~Clk_ik;
reg [2:0] AckI_d3;
always @(posedge SerClk_ik)
if (Rst_irq) begin
AckI_d3 <= `dly 'b0;
end else begin
AckI_d3 <= `dly {AckI_d3[1:0], Ack_i};
end
wire NewAckI_a = AckI_d3[2:1]==2'b01;
reg [31:0] Dat_xb32;
always @(posedge SerClk_ik) DatInShReg_b32 <= `dly {SerDat_i, DatInShReg_b32[31:1]};
always @(posedge SerClk_ik) if (NewAckI_a) Dat_xb32 <= `dly DatInShReg_b32;
reg [2:0] AckI_xb3;
always @(posedge SerClk_ik) AckI_xb3[2] <= `dly Ack_i;
always @(posedge Clk_ik) AckI_xb3[1:0]<= `dly AckI_xb3[2:1];
always @(posedge Clk_ik) if (AckI_xb3[0]) Dat_ob32 <= `dly Dat_xb32;
always @(posedge Clk_ik) Ack_o <= `dly AckI_xb3[0];
endmodule
\ No newline at end of file
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......@@ -57,9 +57,6 @@ wire [4:0] base_addr;
wire gap_error;
wire selected;
reg dav_reg;
reg [31:0] data_in_reg;
wire valid_am;
reg [2:0] state;
......@@ -246,4 +243,4 @@ end
endmodule
\ No newline at end of file
from VmeFunctions import *
class VfcRegisters:
###############################################################################
###############################################################################
# REGISTER SPACE
###############################################################################
###############################################################################
def __init__(self, Slot):
self.Slot = Slot
BoardBaseAddress = Slot*2**24
......
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