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VME FMC Carrier VFC
Commit 8cac29ef authored by Andrea Boccardi's avatar Andrea Boccardi
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minor changes in the structure of the project

parent b46b223e
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trunk/hdl/design/Generic4InputRegs.v
View file @ 8cac29ef
module Generic4InputRegs (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output Ack_oa,
input [31:0] Reg0Value_ib32,
input [31:0] Reg1Value_ib32,
input [31:0] Reg2Value_ib32,
input [31:0] Reg3Value_ib32);
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ib32;
2'b01: Dat_oab32 = Reg1Value_ib32;
2'b10: Dat_oab32 = Reg2Value_ib32;
2'b11: Dat_oab32 = Reg3Value_ib32;
default: Dat_oab32 = Reg0Value_ib32;
endcase
endmodule
module Generic4InputRegs (
input Rst_irq,
input Cyc_i,
input Stb_i,
input [1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output Ack_oa,
input [31:0] Reg0Value_ib32,
input [31:0] Reg1Value_ib32,
input [31:0] Reg2Value_ib32,
input [31:0] Reg3Value_ib32);
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ib32;
2'b01: Dat_oab32 = Reg1Value_ib32;
2'b10: Dat_oab32 = Reg2Value_ib32;
2'b11: Dat_oab32 = Reg3Value_ib32;
default: Dat_oab32 = Reg0Value_ib32;
endcase
endmodule
\ No newline at end of file
trunk/hdl/design/InterruptManagerWB.v
View file @ 8cac29ef
......@@ -62,7 +62,7 @@ always @(posedge Clk_ik) begin
end
end
assign asynch_clk_change = clrn && ~interrupt_in[6];
assign asynch_clk_change = ~Rst_irq && ~interrupt_in[6];
initial osc_clk = 1;
......@@ -169,4 +169,4 @@ always @* case(Adr_ib2)
default: Dat_oab32 <= # dly 32'hdead_beef;
endcase
endmodule
endmodule
\ No newline at end of file
trunk/hdl/design/Monostable.v
View file @ 8cac29ef
module Monostable (
input AsynchIn_ia,
input Clk_ik,
output reg SynchOutput_oq);
parameter g_CounterBits = 20;
reg AsynchIn_ax = 1'b0;
reg [2:0] AsynchInAX_db3 = 2'b0;
always @(posedge AsynchIn_ia) AsynchIn_ax <= #1 ~AsynchIn_ax;
always @(posedge Clk_ik) AsynchInAX_db3 <= #1 {AsynchInAX_db3[1:0], AsynchIn_ax};
wire SynchIn_p = ^AsynchInAX_qdb3[2:1];
reg [g_CounterBits-1:0] Counter_c = 'b0;
always @(posedge Clk_ik) begin
if (SynchIn_p) Counter_c <= #1 'b0;
else if (~&Counter_c) Counter_c <= #1 Counter_c + 1'b1;
end
always @(posedge Clk_ik) SynchOutput_oq <= #1 ~&Counter_c;
endmodule
module Monostable (
input AsynchIn_ia,
input Clk_ik,
output reg SynchOutput_oq);
parameter g_CounterBits = 20;
reg AsynchIn_ax = 1'b0;
reg [2:0] AsynchInAX_db3 = 2'b0;
always @(posedge AsynchIn_ia) AsynchIn_ax <= #1 ~AsynchIn_ax;
always @(posedge Clk_ik) AsynchInAX_db3 <= #1 {AsynchInAX_db3[1:0], AsynchIn_ax};
wire SynchIn_p = ^AsynchInAX_db3[2:0];
reg [g_CounterBits-1:0] Counter_c = 'b0;
always @(posedge Clk_ik) begin
if (SynchIn_p) Counter_c <= #1 'b0;
else if (~&Counter_c) Counter_c <= #1 Counter_c + 1'b1;
end
always @(posedge Clk_ik) SynchOutput_oq <= #1 ~&Counter_c;
endmodule
\ No newline at end of file
trunk/hdl/design/Slv2SerWB.v
View file @ 8cac29ef
module Slv2SerWB (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input We_i,
input [20:0] Adr_ib21,
input [31:0] Dat_ib32,
input Stb_i,
output reg [31:0] Dat_ob32,
output reg Ack_o,
output SerClk_ok,
output SerDat_o,
output SerCntrl_o, //We, Cyc and Adr Rst are serialized on this line
output Stb_o,
input SerClk_ik,
input SerDat_i,
input Ack_i);
`define dly #1
reg [31:0] DatOutShReg_b32 = 32'h0,
DatInShReg_b32 = 32'h0,
CntrlShReg_b32 = 32'h2;
reg [31:0] StbShReg_b32 = 32'h2;
reg StbI_d, AckI_d;
always @(posedge Clk_ik)
if (Rst_irq) begin
AckI_d <= `dly 1'b0;
StbI_d <= `dly 1'b0;
end else begin
AckI_d <= `dly Ack_i;
StbI_d <= `dly Stb_i;
end
wire NewStbI_a = Stb_i && ~StbI_d;
always @(posedge Clk_ik) begin
DatOutShReg_b32 <= `dly {1'b0, DatOutShReg_b32[31:1]};
CntrlShReg_b32 <= `dly {1'b0, CntrlShReg_b32[31:1]};
StbShReg_b32 <= `dly {1'b0, Stb_i, StbShReg_b32[30:1]};
if (Rst_irq) begin
DatOutShReg_b32 <= `dly 32'h0;
CntrlShReg_b32 <= `dly 32'h4;
StbShReg_b32 <= `dly 'h2;
end else if (NewStbI_a) begin
DatOutShReg_b32 <= `dly Dat_ib32;
CntrlShReg_b32 <= `dly {Rst_irq, Cyc_i, We_i, 8'b0, Adr_ib21}; //Rst is useless here, but is just for documentation that i keep it
end
end
assign SerDat_o = DatOutShReg_b32[0];
assign SerCntrl_o = CntrlShReg_b32[0];
assign Stb_o = StbShReg_b32[0];
assign SerClk_ok = ~Clk_ik;
reg [2:0] AckI_d3;
always @(posedge SerClk_ik)
if (Rst_irq) begin
AckI_d3 <= `dly 'b0;
end else begin
AckI_d3 <= `dly {AckI_d3[1:0], Ack_i};
end
wire NewAckI_a = AckI_d3[2:1]==2'b01;
reg [31:0] Dat_xb32;
always @(posedge SerClk_ik) DatInShReg_b32 <= `dly {SerDat_i, DatInShReg_b32[31:1]};
always @(posedge SerClk_ik) if (NewAckI_a) Dat_xb32 <= `dly DatInShReg_b32;
reg [2:0] AckI_xb3;
always @(posedge SerClk_ik) AckI_xb3[2] <= `dly Ack_i;
always @(posedge Clk_ik) AckI_xb3[1:0]<= `dly AckI_xb3[2:1];
always @(posedge Clk_ik) if (AckI_xb3[0]) Dat_ob32 <= `dly Dat_xb32;
always @(posedge Clk_ik) Ack_o <= `dly AckI_xb3[0];
endmodule
module Slv2SerWB (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input We_i,
input [20:0] Adr_ib21,
input [31:0] Dat_ib32,
input Stb_i,
output reg [31:0] Dat_ob32,
output reg Ack_o,
output SerClk_ok,
output SerDat_o,
output SerCntrl_o, //We, Cyc and Adr Rst are serialized on this line
output Stb_o,
input SerClk_ik,
input SerDat_i,
input Ack_i);
`define dly #1
reg [31:0] DatOutShReg_b32 = 32'h0,
DatInShReg_b32 = 32'h0,
CntrlShReg_b32 = 32'h2;
reg [31:0] StbShReg_b32 = 32'h2;
reg StbI_d;
always @(posedge Clk_ik)
if (Rst_irq) begin
StbI_d <= `dly 1'b0;
end else begin
StbI_d <= `dly Stb_i;
end
wire NewStbI_a = Stb_i && ~StbI_d;
always @(posedge Clk_ik) begin
DatOutShReg_b32 <= `dly {1'b0, DatOutShReg_b32[31:1]};
CntrlShReg_b32 <= `dly {1'b0, CntrlShReg_b32[31:1]};
StbShReg_b32 <= `dly {1'b0, Stb_i, StbShReg_b32[30:1]};
if (Rst_irq) begin
DatOutShReg_b32 <= `dly 32'h0;
CntrlShReg_b32 <= `dly 32'h4;
StbShReg_b32 <= `dly 'h2;
end else if (NewStbI_a) begin
DatOutShReg_b32 <= `dly Dat_ib32;
CntrlShReg_b32 <= `dly {Rst_irq, Cyc_i, We_i, 8'b0, Adr_ib21}; //Rst is useless here, but is just for documentation that i keep it
end
end
assign SerDat_o = DatOutShReg_b32[0];
assign SerCntrl_o = CntrlShReg_b32[0];
assign Stb_o = StbShReg_b32[0];
assign SerClk_ok = ~Clk_ik;
reg [2:0] AckI_d3;
always @(posedge SerClk_ik)
if (Rst_irq) begin
AckI_d3 <= `dly 'b0;
end else begin
AckI_d3 <= `dly {AckI_d3[1:0], Ack_i};
end
wire NewAckI_a = AckI_d3[2:1]==2'b01;
reg [31:0] Dat_xb32;
always @(posedge SerClk_ik) DatInShReg_b32 <= `dly {SerDat_i, DatInShReg_b32[31:1]};
always @(posedge SerClk_ik) if (NewAckI_a) Dat_xb32 <= `dly DatInShReg_b32;
reg [2:0] AckI_xb3;
always @(posedge SerClk_ik) AckI_xb3[2] <= `dly Ack_i;
always @(posedge Clk_ik) AckI_xb3[1:0]<= `dly AckI_xb3[2:1];
always @(posedge Clk_ik) if (AckI_xb3[0]) Dat_ob32 <= `dly Dat_xb32;
always @(posedge Clk_ik) Ack_o <= `dly AckI_xb3[0];
endmodule
\ No newline at end of file
trunk/hdl/design/SpiMasterWB.v
View file @ 8cac29ef
/*
* This is a SPI master for up to 32 independent slaves
* The module support the following configurations:
* - Any CPol CPha combination
* - The lenght of the reg is programmable up to 256 allowing
* the concatenation of several slaves, if the access is longer
* than 32 bits between 2 registers the communication is paused
* - MSB or LSB first
* - The speed of the clock is settable
* - It is possible to put a wait state between the falling edge
* of SS (Slave Select) and the 1st edge of SClk as requested from some
* ADC
*/
module SpiMasterWB (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [2:0] Adr_ib3,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output reg Ack_oa,
output reg WaitingNewData_o,
output reg ModuleIdle_o,
output reg SClk_o,
output MoSi_o,
input [31:0] MiSo_ib32,
output reg [31:0] SS_onb32);
`define c_AddrStatus 3'd0
`define c_AddrConfig1 3'd1
`define c_AddrConfig2 3'd2
`define c_AddrShiftOut 3'd3
`define c_AddrShiftIn 3'd4
reg [31:0] Config2_qb32,
ShiftOut_qb32,
ShiftIn_qb32,
a_Status_b32,
Config1_qb32;
wire a_CPol = Config1_qb32[31];
wire a_CPha = Config1_qb32[30];
wire a_Lsb1St = Config1_qb32[29];
wire [4:0] a_SpiChannel_b5 = Config1_qb32[20:16];
wire [11:0] a_RegisterLenght_b12 = Config1_qb32[11:0];
wire [15:0] a_ClkSemiPeriod_b16 = Config2_qb32[31:16];
wire [15:0] a_WaitTime_b16 = Config2_qb32[15:0];
reg [2:0] State_a,
State_q;
`define s_Idle 3'd0
`define s_WaitBefore1StEdge 3'd1
`define s_EdgeTypeOne 3'd2
`define s_EdgeTypeTwo 3'd3
`define s_TxPause 3'd4
`define s_EndOfTx 3'd5
reg [15:0] TimeCounter_cb16;
reg [11:0] TxCounter_cb12;
always @(posedge Clk_ik)
if (Rst_irq) State_q <= `s_Idle;
else State_q <= State_a;
always @* begin
State_a = State_q;
case (State_q)
`s_Idle: if (StartTx_q) State_a = `s_WaitBefore1StEdge;
`s_WaitBefore1StEdge: if (TimeCounter_cb16==a_WaitTime_b16) State_a = `s_EdgeTypeOne;
`s_EdgeTypeOne: if (TimeCounter_cb16==a_ClkSemiPeriod_b16) State_a = `s_EdgeTypeTwo;
`s_EdgeTypeTwo: if (TimeCounter_cb16==a_ClkSemiPeriod_b16)
if (TxCounter_cb12==a_RegisterLenght_b12) State_a = `s_EndOfTx;
else if (|TxCounter_cb12[4:0]) State_a = `s_EdgeTypeOne;
else State_a = `s_TxPause;
`s_TxPause: if (StartTx_q) State_a = `s_EdgeTypeOne;
`s_EndOfTx: if (TimeCounter_cb16==a_ClkSemiPeriod_b16) State_a = `s_Idle;
default: State_a = `s_Idle;
endcase
end
reg WriteAck_q, StartTx_q;
assign MoSi_o = a_Lsb1St ? ShiftOut_qb32[0] : ShiftOut_qb32[31];
always @(posedge Clk_ik) begin
WriteAck_q <= WriteAck_q && Stb_i; // Default clear condition valid for all the states
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
if (Rst_irq) begin
StartTx_q <= 'b0;
WriteAck_q <= 'b0;
SClk_o <= 'b0;
SS_onb32 <= 32'hFFFF_FFFF;
TimeCounter_cb16 <= 'h0;
TxCounter_cb12 <= 'h0;
Config1_qb32 <= 'h0;
Config2_qb32 <= 'h0;
ShiftOut_qb32 <= 'h0;
ShiftIn_qb32 <= 'h0;
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
end else case (State_q)
`s_Idle: begin
SClk_o <= a_CPol;
SS_onb32 <= 32'h_FFFF_FFFF;
TimeCounter_cb16 <= 'h0;
TxCounter_cb12 <= 'h0;
ModuleIdle_o <= State_a==`s_Idle;
if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrShiftOut) begin
ShiftOut_qb32 <= Dat_ib32;
ShiftIn_qb32 <= 'h0;
WriteAck_q <= 1'b1;
StartTx_q <= 1'b1;
end else if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrConfig1) begin
Config1_qb32 <= Dat_ib32;
WriteAck_q <= 1'b1;
end else if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrConfig2) begin
Config2_qb32 <= Dat_ib32;
WriteAck_q <= 1'b1;
end
end
`s_WaitBefore1StEdge: begin
TimeCounter_cb16 <= TimeCounter_cb16 + 1'b1;
SS_onb32[a_SpiChannel_b5] <= 1'b0;
if (State_a==`s_EdgeTypeOne) TimeCounter_cb16 <= 'h0;
end
`s_EdgeTypeOne: begin
TimeCounter_cb16 <= TimeCounter_cb16 + 1'b1;
if (State_a==`s_EdgeTypeTwo) begin
TimeCounter_cb16 <= 'h0;
SClk_o <= ~SClk_o;
TxCounter_cb12 <= TxCounter_cb12 + 1'b1;
StartTx_q <= 'h0;
if (a_CPha && ~StartTx_q) ShiftOut_qb32 <= a_Lsb1St ? {ShiftOut_qb32[0], ShiftOut_qb32[31:1]} : {ShiftOut_qb32[30:0], ShiftOut_qb32[31]};
else if (~a_CPha) ShiftIn_qb32 <= a_Lsb1St ? {MiSo_ib32[a_SpiChannel_b5], ShiftIn_qb32[31:1]} : {ShiftIn_qb32[30:0], MiSo_ib32[a_SpiChannel_b5]};
end
end
`s_EdgeTypeTwo: begin
TimeCounter_cb16 <= TimeCounter_cb16 + 1'b1;
if (State_a!=`s_EdgeTypeTwo) begin
SClk_o <= ~SClk_o;
TimeCounter_cb16 <= 'h0;
if (~a_CPha)ShiftOut_qb32 <= a_Lsb1St ? {ShiftOut_qb32[0], ShiftOut_qb32[31:1]} : {ShiftOut_qb32[30:0], ShiftOut_qb32[31]};
else ShiftIn_qb32 <= a_Lsb1St ? {MiSo_ib32[a_SpiChannel_b5], ShiftIn_qb32[31:1]} : {ShiftIn_qb32[30:0], MiSo_ib32[a_SpiChannel_b5]};
end
end
`s_TxPause: begin
WaitingNewData_o <= State_a==`s_TxPause;
if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrShiftOut) begin
ShiftOut_qb32 <= Dat_ib32;
ShiftIn_qb32 <= 'h0;
WriteAck_q <= 1'b1;
StartTx_q <= 1'b1;
end
end
`s_EndOfTx: begin
TimeCounter_cb16 <= TimeCounter_cb16 + 1'b1;
if (State_a==`s_Idle) SS_onb32 <= 32'hFFFF_FFFF;
end
default: begin
StartTx_q <= 'b0;
WriteAck_q <= 'b0;
SClk_o <= 'b0;
SS_onb32 <= 32'hFFFF_FFFF;
TimeCounter_cb16 <= 'h0;
TxCounter_cb12 <= 'h0;
Config1_qb32 <= 'h0;
Config2_qb32 <= 'h0;
ShiftOut_qb32 <= 'h0;
ShiftIn_qb32 <= 'h0;
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
end
endcase
end
always @* begin
Ack_oa <= (Stb_i&&Cyc_i&&~We_i) || WriteAck_q;
case (Adr_ib3)
`c_AddrStatus: Dat_oab32 <= {12'h0, 1'b0, State_q, 4'b0, TxCounter_cb12};
`c_AddrConfig1: Dat_oab32 <= Config1_qb32;
`c_AddrConfig2: Dat_oab32 <= Config2_qb32;
`c_AddrShiftOut: Dat_oab32 <= ShiftOut_qb32;
`c_AddrShiftIn: Dat_oab32 <= ShiftIn_qb32;
default: Dat_oab32 <= 32'hDEAD_BEEF;
endcase
end
endmodule
/*
* This is a SPI master for up to 32 independent slaves
* The module support the following configurations:
* - Any CPol CPha combination
* - The lenght of the reg is programmable up to 256 allowing
* the concatenation of several slaves, if the access is longer
* than 32 bits between 2 registers the communication is paused
* - MSB or LSB first
* - The speed of the clock is settable
* - It is possible to put a wait state between the falling edge
* of SS (Slave Select) and the 1st edge of SClk as requested from some
* ADC
*/
module SpiMasterWB (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [2:0] Adr_ib3,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output reg Ack_oa,
output reg WaitingNewData_o,
output reg ModuleIdle_o,
output reg SClk_o,
output MoSi_o,
input [31:0] MiSo_ib32,
output reg [31:0] SS_onb32);
`define c_AddrStatus 3'd0
`define c_AddrConfig1 3'd1
`define c_AddrConfig2 3'd2
`define c_AddrShiftOut 3'd3
`define c_AddrShiftIn 3'd4
reg [31:0] Config2_qb32,
ShiftOut_qb32,
ShiftIn_qb32,
Config1_qb32;
wire a_CPol = Config1_qb32[31];
wire a_CPha = Config1_qb32[30];
wire a_Lsb1St = Config1_qb32[29];
wire [4:0] a_SpiChannel_b5 = Config1_qb32[20:16];
wire [11:0] a_RegisterLenght_b12 = Config1_qb32[11:0];
wire [15:0] a_ClkSemiPeriod_b16 = Config2_qb32[31:16];
wire [15:0] a_WaitTime_b16 = Config2_qb32[15:0];
reg [2:0] State_a,
State_q;
`define s_Idle 3'd0
`define s_WaitBefore1StEdge 3'd1
`define s_EdgeTypeOne 3'd2
`define s_EdgeTypeTwo 3'd3
`define s_TxPause 3'd4
`define s_EndOfTx 3'd5
reg [15:0] TimeCounter_cb16;
reg [11:0] TxCounter_cb12;
reg WriteAck_q, StartTx_q;
always @(posedge Clk_ik)
if (Rst_irq) State_q <= `s_Idle;
else State_q <= State_a;
always @* begin
State_a = State_q;
case (State_q)
`s_Idle: if (StartTx_q) State_a = `s_WaitBefore1StEdge;
`s_WaitBefore1StEdge: if (TimeCounter_cb16==a_WaitTime_b16) State_a = `s_EdgeTypeOne;
`s_EdgeTypeOne: if (TimeCounter_cb16==a_ClkSemiPeriod_b16) State_a = `s_EdgeTypeTwo;
`s_EdgeTypeTwo: if (TimeCounter_cb16==a_ClkSemiPeriod_b16)
if (TxCounter_cb12==a_RegisterLenght_b12) State_a = `s_EndOfTx;
else if (|TxCounter_cb12[4:0]) State_a = `s_EdgeTypeOne;
else State_a = `s_TxPause;
`s_TxPause: if (StartTx_q) State_a = `s_EdgeTypeOne;
`s_EndOfTx: if (TimeCounter_cb16==a_ClkSemiPeriod_b16) State_a = `s_Idle;
default: State_a = `s_Idle;
endcase
end
assign MoSi_o = a_Lsb1St ? ShiftOut_qb32[0] : ShiftOut_qb32[31];
always @(posedge Clk_ik) begin
WriteAck_q <= WriteAck_q && Stb_i; // Default clear condition valid for all the states
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
if (Rst_irq) begin
StartTx_q <= 'b0;
WriteAck_q <= 'b0;
SClk_o <= 'b0;
SS_onb32 <= 32'hFFFF_FFFF;
TimeCounter_cb16 <= 'h0;
TxCounter_cb12 <= 'h0;
Config1_qb32 <= 'h0;
Config2_qb32 <= 'h0;
ShiftOut_qb32 <= 'h0;
ShiftIn_qb32 <= 'h0;
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
end else case (State_q)
`s_Idle: begin
SClk_o <= a_CPol;
SS_onb32 <= 32'hFFFF_FFFF;
TimeCounter_cb16 <= 'h0;
TxCounter_cb12 <= 'h0;
ModuleIdle_o <= State_a==`s_Idle;
if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrShiftOut) begin
ShiftOut_qb32 <= Dat_ib32;
ShiftIn_qb32 <= 'h0;
WriteAck_q <= 1'b1;
StartTx_q <= 1'b1;
end else if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrConfig1) begin
Config1_qb32 <= Dat_ib32;
WriteAck_q <= 1'b1;
end else if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrConfig2) begin
Config2_qb32 <= Dat_ib32;
WriteAck_q <= 1'b1;
end
end
`s_WaitBefore1StEdge: begin
TimeCounter_cb16 <= TimeCounter_cb16 + 1'b1;
SS_onb32[a_SpiChannel_b5] <= 1'b0;
if (State_a==`s_EdgeTypeOne) TimeCounter_cb16 <= 'h0;
end
`s_EdgeTypeOne: begin
TimeCounter_cb16 <= TimeCounter_cb16 + 1'b1;
if (State_a==`s_EdgeTypeTwo) begin
TimeCounter_cb16 <= 'h0;
SClk_o <= ~SClk_o;
TxCounter_cb12 <= TxCounter_cb12 + 1'b1;
StartTx_q <= 'h0;
if (a_CPha && ~StartTx_q) ShiftOut_qb32 <= a_Lsb1St ? {ShiftOut_qb32[0], ShiftOut_qb32[31:1]} : {ShiftOut_qb32[30:0], ShiftOut_qb32[31]};
else if (~a_CPha) ShiftIn_qb32 <= a_Lsb1St ? {MiSo_ib32[a_SpiChannel_b5], ShiftIn_qb32[31:1]} : {ShiftIn_qb32[30:0], MiSo_ib32[a_SpiChannel_b5]};
end
end
`s_EdgeTypeTwo: begin
TimeCounter_cb16 <= TimeCounter_cb16 + 1'b1;
if (State_a!=`s_EdgeTypeTwo) begin
SClk_o <= ~SClk_o;
TimeCounter_cb16 <= 'h0;
if (~a_CPha)ShiftOut_qb32 <= a_Lsb1St ? {ShiftOut_qb32[0], ShiftOut_qb32[31:1]} : {ShiftOut_qb32[30:0], ShiftOut_qb32[31]};
else ShiftIn_qb32 <= a_Lsb1St ? {MiSo_ib32[a_SpiChannel_b5], ShiftIn_qb32[31:1]} : {ShiftIn_qb32[30:0], MiSo_ib32[a_SpiChannel_b5]};
end
end
`s_TxPause: begin
WaitingNewData_o <= State_a==`s_TxPause;
if (Cyc_i && We_i && Stb_i && Adr_ib3==`c_AddrShiftOut) begin
ShiftOut_qb32 <= Dat_ib32;
ShiftIn_qb32 <= 'h0;
WriteAck_q <= 1'b1;
StartTx_q <= 1'b1;
end
end
`s_EndOfTx: begin
TimeCounter_cb16 <= TimeCounter_cb16 + 1'b1;
if (State_a==`s_Idle) SS_onb32 <= 32'hFFFF_FFFF;
end
default: begin
StartTx_q <= 'b0;
WriteAck_q <= 'b0;
SClk_o <= 'b0;
SS_onb32 <= 32'hFFFF_FFFF;
TimeCounter_cb16 <= 'h0;
TxCounter_cb12 <= 'h0;
Config1_qb32 <= 'h0;
Config2_qb32 <= 'h0;
ShiftOut_qb32 <= 'h0;
ShiftIn_qb32 <= 'h0;
ModuleIdle_o <= 'h0;
WaitingNewData_o <= 'h0;
end
endcase
end
always @* begin
Ack_oa <= (Stb_i&&Cyc_i&&~We_i) || WriteAck_q;
case (Adr_ib3)
`c_AddrStatus: Dat_oab32 <= {12'h0, 1'b0, State_q, 4'b0, TxCounter_cb12};
`c_AddrConfig1: Dat_oab32 <= Config1_qb32;
`c_AddrConfig2: Dat_oab32 <= Config2_qb32;
`c_AddrShiftOut: Dat_oab32 <= ShiftOut_qb32;
`c_AddrShiftIn: Dat_oab32 <= ShiftIn_qb32;
default: Dat_oab32 <= 32'hDEAD_BEEF;
endcase
end
endmodule
\ No newline at end of file
trunk/hdl/design/SystemFpga.v
View file @ 8cac29ef
`timescale 1ns/1ns
module SystemFpga (
// VME BUS SIGNALS
input UseGa_i,
input [4:0] ManualAddress_ib5,
input [4:0] VmeGa_ib5n,
input VmeGaP_in,
output [7:1] VmeIrq_ob7, // Active high because of the connection on the board
inout [31:0] VmeD_iob32,
output VmeDtAckOe_oe,
output VmeDtAck_on,
inout [31:1] VmeA_iob31,
inout VmeLword_io,
input [5:0] VmeAm_ib6,
input VmeAs_in,
input VmeSysClk_ik,
input VmeWrite_in,
output VmeDOeN_oen,
output VmeDDirVfcToVme_o,
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
input [2:1] VmeDs_inb2,
output VmeAOeN_oen,
output VmeADirVfcToVme_o,
output VmeRetryOe_oe,
output VmeRetry_on,
output VmeBerr_o, // Active high because of the connection on the board
input VmeSysReset_in,
input VmeTck_i,
input VmeTrst_i,
output VmeTdoOe_oe,
output VmeTdo_o,
input VmeTdi_i,
input VmeTms_i,
// CLOCKS
input VcTcXo_ik,
input Si57x_ik,
// PUSH BUTTON
inout PushButton_ion,
// SWITCHES
input [1:0] Switch_ib2,
// Front Panel GPIO
output [7:0] FpLed_onb8,
// Front Panel GPIO
output FpGpIo1OutputMode_o,
output FpGpIo2OutputMode_o,
output FpGpIo34OutputMode_o,
// Application FPGA Programming Pins
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgClk_io,
inout [1:0] AFpgaProgM_iob2,
inout AFpgaProgCsi_io,
inout AFpgaProgRdWr_io,
inout AFpgaProgInit_io,
// Application FPGA Clk
output SysAppClk_o,
// Application FPGA Slow Communication
inout [2:1] SysAppSlow_iob2,
// Flash PROMs Interfaces
output FlashSFpgaD_o,
output FlashSFpgaClk_ok,
output FlashSFpgaCs_on,
input FlashSFpgaQ_i,
output FlashAFpgaD_o,
output FlashAFpgaClk_ok,
output FlashAFpgaCs_on,
input FlashAFpgaQ_i,
// Voltage Monitoring ADC interface
output VAdcSClk_ok,
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_on,
// VAdj Control
output VAdjCs_on,
output VAdjSClk_ok,
output VAdjDin_o,
output VAdjInhibit_ozn,
output VAdjSpi_o,
// PLLs control
input PllFmc1Ld_i,
input PllFmc1Status_i,
input PllFmc1RefMon_i,
output PllFmc1RefSel_o,
output PllFmc1Ref1_ok,
output PllFmc1Pd_on,
output PllFmc1Synch_on,
output PllFmc1Reset_orn,
output PllFmc1SClk_ok,
inout PllFmc1SDio_io,
input PllFmc1Sdo_i,
output PllFmc1Cs_on,
input PllFmc12SFpgaP_ik,
input PllFmc2Ld_i,
input PllFmc2Status_i,
input PllFmc2RefMon_i,
output PllFmc2RefSel_o,
output PllFmc2Ref1_ok,
output PllFmc2Pd_on,
output PllFmc2Synch_on,
output PllFmc2Reset_orn,
output PllFmc2SClk_ok,
inout PllFmc2SDio_io,
input PllFmc2Sdo_i,
output PllFmc2Cs_on,
input PllFmc22SFpgaP_ik,
input PllSysLd_i,
input PllSysStatus_i,
input PllSysRefMon_i,
output PllSysRefSel_o,
output PllSysRef12_ok,
output PllSysPd_on,
output PllSysSynch_on,
output PllSysReset_orn,
output PllSysSClk_ok,
inout PllSysSDio_io,
input PllSysSdo_i,
output PllSysCs_on,
input PllSys2SFpgaP_ik,
input PllDdsLd_i,
input PllDdsStatus_i,
input PllDdsRefMon_i,
output PllDdsRefSel_o,
output PllDdsPd_on,
output PllDdsSynch_on,
output PllDdsReset_orn,
output PllDdsClk_ok,
output PllDdsSClk_ok,
inout PllDdsSDio_io,
input PllDdsSdo_i,
output PllDdsCs_on,
input PllDds2SFpgaP_ik,
// PLL DAC
output PllDacSClk_ok,
output PllDacSynch_on,
output PllDacDin_o,
input PllDacDout_i,
output PllDacClrn_orn,
output PllDacLDac_on
);
`define dly 1
//####################################
// FP Leds
//####################################
wire VmeAccessForLed;
wire RstForLed;
Monostable i_VmeAccessMonostable(
.AsynchIn_ia(StbMaster),
.Clk_ik(Clk_k),
.SynchOutput_oq(VmeAccessForLed));
Monostable i_ClearMonostable(
.AsynchIn_ia(Rst_rq),
.Clk_ik(Clk_k),
.SynchOutput_oq(RstForLed));
assign FpLed_onb8[0] = VmeAccessForLed ? 1'b0 : 1'bz;
assign FpLed_onb8[1] = (~&VmeIrq_ob7) ? 1'b0 : 1'bz;
assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz;
assign FpLed_onb8[3] = RstForLed ? 1'b0 : 1'bz;
wire Si57xDivided = Si57xDivider_c[21];
reg [21:0] Si57xDivider_c = 'd0;
always @(posedge Si57x_ik) Si57xDivider_c <= #`dly Si57xDivider_c + 1'b1;
wire VcTcXoDivided = VcTcXoDivider_c[21];
reg [21:0] VcTcXoDivider_c = 'd0;
always @(posedge VcTcXo_ik) VcTcXoDivider_c <= #`dly VcTcXoDivider_c + 1'b1;
wire VmeSysClkDivided = VmeSysClkDivider_c[21];
reg [21:0] VmeSysClkDivider_c = 'd0;
always @(posedge VmeSysClk_ik) VmeSysClkDivider_c <= #`dly VmeSysClkDivider_c + 1'b1;
reg a_FpLed7;
always @* case(Switch_ib2)
2'b00: a_FpLed7 = Si57xDivided;
2'b01: a_FpLed7 = VcTcXoDivided;
2'b10: a_FpLed7 = VmeSysClkDivided;
default: a_FpLed7 = VcTcXoDivided;
endcase
assign FpLed_onb8[4] = Si57xDivided ? 1'bz : 1'b0;
assign FpLed_onb8[5] = VcTcXoDivided ? 1'bz : 1'b0;
assign FpLed_onb8[6] = VmeSysClkDivided ? 1'bz : 1'b0;
assign FpLed_onb8[7] = a_FpLed7 ? 1'bz : 1'b0;
//####################################
// FP GP IO
//####################################
assign FpGpIo1OutputMode_o = 1'b0;
assign FpGpIo2OutputMode_o = 1'b1;
assign FpGpIo34OutputMode_o = 1'b1;
//####################################
// Clock
//####################################
reg Clk_k;
always @* case(Switch_ib2)
2'b00: Clk_k = Si57x_ik;
2'b01: Clk_k = VcTcXo_ik;
2'b10: Clk_k = VmeSysClk_ik;
default: Clk_k = VcTcXo_ik;
endcase
//#####################################
// Reset Signal Generation
//#####################################
reg Rst_rq;
reg [1:0] VmeSysReset_dx;
always @(posedge Clk_k) VmeSysReset_dx <= #`dly {VmeSysReset_dx[0], VmeSysReset_in};
wire a_VmeSysReset_nq = VmeSysReset_dx[1];
wire DeboucedPushButton_q;
Debouncer #(.g_CounterWidth(16), .g_SynchDepth(3)) i_Debouncer (
.Clk_ik(Clk_k),
.BouncingSignal_ia(PushButton_ion),
.DebouncedSignal_oq(DeboucedPushButton_q));
always @(posedge Clk_k) Rst_rq <= #`dly ~DeboucedPushButton_q || ~a_VmeSysReset_nq;
//#####################################
// VME Interface
//#####################################
wire IntAcknowledged;
wire AssertInterrupt;
wire VmeDtAck_n, VmeDOe;
wire RdReg, WrReg;
wire [7:1] VmeIrq_b7n;
assign VmeDtAck_on = 1'b0;
assign VmeDtAckOe_oe = ~VmeDtAck_n;
assign VmeDOeN_oen = ~VmeDOe;
assign VmeAOeN_oen = 1'b0;
assign VmeADirVfcToVme_o = 1'b0;
assign VmeRetryOe_oe = 1'b0;
assign VmeRetry_on = 1'b1;
assign VmeBerr_o = 1'b0;
assign VmeIrq_ob7 = ~VmeIrq_b7n;
assign VmeTdoOe_oe = 1'b0;
wire [2:0] InterrupLevel = InterruptConfigReg_b32[30:28];
wire [7:0] IntVector_b8 = InterruptConfigReg_b32[7:0];
wire [7:0] IntSource_b8;
assign IntSource_b8[7:2] = GenericOutputReg1[7:2];
assign IntSource_b8[1] = SpiIdle;
assign IntSource_b8[0] = SpiWaitingData;
wire StbMaster, AckMaster, Cyc, We;
wire [21:0] Adr_b22;
wire [31:0] DatMasterI_b32, DatMasterO_b32;
VmeInterfaceWB i_VmeInterface(
.rst_i(Rst_rq),
.clk_i(Clk_k),
.adr_o(Adr_b22),
.dat_o(DatMasterO_b32),
.dat_i(DatMasterI_b32),
.we_o(We),
.stb_o(StbMaster),
.ack_i(AckMaster),
.cyc_o(Cyc),
.UseGa_i(UseGa_i),
.ManualAddress_i(ManualAddress_ib5),
.vme_ga(VmeGa_ib5n),
.vme_gap(VmeGaP_in),
.vme_as(VmeAs_in),
.vme_ds1(VmeDs_inb2[1]),
.vme_ds2(VmeDs_inb2[2]),
.vme_am(VmeAm_ib6),
.vme_wr(VmeWrite_in),
.vme_dtack(VmeDtAck_n),
.vme_lword(VmeLword_io),
.vme_addr(VmeA_iob31),
.vme_data(VmeD_iob32),
.VmeDOe_o(VmeDOe),
.VmeDDirFpgaToVme_o(VmeDDirVfcToVme_o),
.vme_iackinn(VmeIackIn_in),
.vme_iackn(VmeIack_in),
.vme_iack_outn(VmeIackOut_on),
.vme_irqn(VmeIrq_b7n),
.intlev_reg(InterrupLevel),
.IrqVector_i(IntVector_b8),
.assert_interrupt(AssertInterrupt),
.clear_int(IntAcknowledged));
wire [31:0] DatIntManagerO_b32;
wire StbIntManager, AckIntMAnager;
InterruptManagerWB i_InterruptManager(
.Clk_ik(Clk_k),
.Rst_irq(Rst_rq),
.int_enable({1'b1}),
.Cyc_i(Cyc),
.Stb_i(StbIntManager),
.We_i(We),
.Adr_ib2(Adr_b22[1:0]),
.Dat_ib32(DatMasterO_b32),
.Dat_oab32(DatIntManagerO_b32),
.Ack_oa(AckIntMAnager),
.interrupt_in(IntSource_b8),
.int_acknowledged(IntAcknowledged),
.clear_all({1'b0}),
.assert_interrupt(AssertInterrupt));
AddressDecoderWBSys i_AddressDecoderWB(
.Adr_ib22(Adr_b22),
.Stb_i(StbMaster),
.Dat_ob32(DatMasterI_b32),
.Ack_o(AckMaster),
.DatIntManager_ib32(DatIntManagerO_b32),
.AckIntMAnager_i(AckIntMAnager),
.StbIntManager_o(StbIntManager),
.DatGenericOutputRegs_ib32(DatGenericOutputRegsrO_b32),
.AckGenericOutputRegs_i(AckGenericOutputRegs),
.StbGenericOutputRegs_o(StbGenericOutputRegs),
.DatGenericInputRegs_ib32(DatGenericInputRegsrO_b32),
.AckGenericInputRegs_i(AckGenericInputRegs),
.StbGenericInputRegs_o(StbGenericInputRegs),
.DatSlv2SerWB_ib32(DatSlv2SerWBO_b32),
.AckSlv2SerWB_i(AckSlv2SerWB),
.StbSlv2SerWB_o(StbSlv2SerWB),
.DatSpiMaster_ib32(DatSpiMaster_b32),
.AckSpiMaster_i(AckSpiMaster),
.StbSpiMaster_o(StbSpiMaster));
//#####################################
// GenericOutput Registers
//#####################################
wire [31:0] InterruptConfigReg_b32, GenericOutputReg1, PllConfigBits_b32, GenericOutputReg3;
wire [31:0] DatGenericOutputRegsrO_b32;
wire StbGenericOutputRegs, AckGenericOutputRegs;
Generic4OutputRegs #(.Reg2Default(32'h8888)) i_Generic4OutputRegs(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.Stb_i(StbGenericOutputRegs),
.We_i(We),
.Adr_ib2(Adr_b22[1:0]),
.Dat_ib32(DatMasterO_b32),
.Dat_oab32(DatGenericOutputRegsrO_b32),
.Ack_oa(AckGenericOutputRegs),
.Reg0Value_ob32(InterruptConfigReg_b32),
.Reg1Value_ob32(GenericOutputReg1),
.Reg2Value_ob32(PllConfigBits_b32),
.Reg3Value_ob32(GenericOutputReg3));
//#####################################
// GenericInput Registers
//#####################################
wire [31:0] PllStatusBits_b32, GenericInputReg1, GenericInputReg2, GenericInputReg3;
wire [31:0] DatGenericInputRegsrO_b32;
wire StbGenericInputRegs, AckGenericInputRegs;
Generic4InputRegs i_Generic4InputRegs(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.Stb_i(StbGenericInputRegs),
.We_i(We),
.Adr_ib2(Adr_b22[1:0]),
.Dat_oab32(DatGenericInputRegsrO_b32),
.Ack_oa(AckGenericInputRegs),
.Reg0Value_ib32(PllStatusBits_b32),
.Reg1Value_ib32(GenericInputReg1),
.Reg2Value_ib32(GenericInputReg2),
.Reg3Value_ib32(GenericInputReg3));
//#####################################
// WB Serial Interface To The A-FPGA
//#####################################
wire [31:0] DatSlv2SerWBO_b32;
wire StbSlv2SerWB, AckSlv2SerWB;
Slv2SerWB i_Slv2SerWB(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.We_i(We),
.Adr_ib21(Adr_b22[20:0]),
.Dat_ib32(DatMasterO_b32),
.Stb_i(StbSlv2SerWB),
.Dat_ob32(DatSlv2SerWBO_b32),
.Ack_o(AckSlv2SerWB),
.SerClk_ok(SysAppClk_o),
.SerDat_o(SysAppSlow_iob2[1]),
.SerCntrl_o(SysAppSlow_iob2[2]),
.Stb_o(AFpgaProgD_iob8[7]),
.SerClk_ik(AFpgaProgD_iob8[6]),
.SerDat_i(AFpgaProgD_iob8[5]),
.Ack_i(AFpgaProgD_iob8[4]));
//#####################################
// SPI master
//#####################################
wire [31:0] SpiSS_nb32, SpiMiSo_b32;
wire SpiMoSi, SpiSClk_k;
wire StbSpiMaster, AckSpiMaster;
wire [31:0] DatSpiMaster_b32;
assign SpiMiSo_b32[31] = SpiMoSi;
assign SpiMiSo_b32[8] = FlashSFpgaQ_i; //Think about removing it and placing it in a special place (CSR space)
assign FlashSFpgaCs_on = SpiSS_nb32[8]; //Think about removing it and placing it in a special place (CSR space)
assign FlashSFpgaD_o = SpiMoSi; //Think about removing it and placing it in a special place (CSR space)
assign FlashSFpgaClk_ok = SpiSClk_k; //Think about removing it and placing it in a special place (CSR space)
assign SpiMiSo_b32[7] = FlashAFpgaQ_i;
assign FlashAFpgaCs_on = SpiSS_nb32[7];
assign FlashAFpgaD_o = SpiMoSi;
assign FlashAFpgaClk_ok = SpiSClk_k;
assign SpiMiSo_b32[6] = VAdcDout_i;
assign VAdcCs_on = SpiSS_nb32[6];
assign VAdcDin_o = SpiMoSi;
assign VAdcSClk_ok = SpiSClk_k;
assign SpiMiSo_b32[5] = PllFmc1Sdo_i;
assign PllFmc1Cs_on = SpiSS_nb32[5];
assign PllFmc1SDio_io = SpiMoSi;
assign PllFmc1SClk_ok = SpiSClk_k;
assign SpiMiSo_b32[4] = PllFmc2Sdo_i;
assign PllFmc2Cs_on = SpiSS_nb32[4];
assign PllFmc2SDio_io = SpiMoSi;
assign PllFmc2SClk_ok = SpiSClk_k;
assign SpiMiSo_b32[3] = PllSysSdo_i;
assign PllSysCs_on = SpiSS_nb32[3];
assign PllSysSDio_io = SpiMoSi;
assign PllSysSClk_ok = SpiSClk_k;
assign SpiMiSo_b32[2] = PllDdsSdo_i;
assign PllDdsCs_on = SpiSS_nb32[2];
assign PllDdsSDio_io = SpiMoSi;
assign PllDdsSClk_ok = SpiSClk_k;
assign SpiMiSo_b32[1] = SpiMoSi; //in feedback as the module doesn't have a Dout: this way at least we read the last sent.
assign VAdjCs_on = SpiSS_nb32[1];
assign VAdjDin_o = SpiMoSi;
assign VAdjSClk_ok = SpiSClk_k;
assign VAdjSpi_o = 1'b1; //we keep it in SPI mode
assign VAdjInhibit_ozn = 1'bz; //we keep the generator on
assign SpiMiSo_b32[0] = PllDacDin_o; //in feedback as the module doesn't have a Dout: this way at least we read the last sent.
assign PllDacSynch_on = SpiSS_nb32[0];
assign PllDacDin_o = SpiMoSi;
assign PllDacSClk_ok = SpiSClk_k;
wire SpiIdle, SpiWaitingData;
SpiMasterWB i_SpiMasterWB(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.We_i(We),
.Adr_ib3(Adr_b22[2:0]),
.Dat_ib32(DatMasterO_b32),
.Stb_i(StbSpiMaster),
.Dat_oab32(DatSpiMaster_b32),
.Ack_oa(AckSpiMaster),
.WaitingNewData_o(SpiWaitingData),
.ModuleIdle_o(SpiIdle),
.SClk_o(SpiSClk_k),
.MoSi_o(SpiMoSi),
.MiSo_ib32(SpiMiSo_b32),
.SS_onb32(SpiSS_nb32));
//#####################################
// Non SPI PLLs Control bits
//#####################################
assign PllFmc1RefSel_o = PllConfigBits_b32[15];
assign PllFmc1Pd_on = PllConfigBits_b32[14];
assign PllFmc1Synch_on = PllConfigBits_b32[13];
assign PllFmc1Reset_orn = PllConfigBits_b32[12];
assign PllFmc2RefSel_o = PllConfigBits_b32[11];
assign PllFmc2Pd_on = PllConfigBits_b32[10];
assign PllFmc2Synch_on = PllConfigBits_b32[9];
assign PllFmc2Reset_orn = PllConfigBits_b32[8];
assign PllSysRefSel_o = PllConfigBits_b32[7];
assign PllSysPd_on = PllConfigBits_b32[6];
assign PllSysSynch_on = PllConfigBits_b32[5];
assign PllSysReset_orn = PllConfigBits_b32[4];
assign PllDdsRefSel_o = PllConfigBits_b32[3];
assign PllDdsPd_on = PllConfigBits_b32[2];
assign PllDdsSynch_on = PllConfigBits_b32[1];
assign PllDdsReset_orn = PllConfigBits_b32[0];
assign PllStatusBits_b32[15] = PllFmc1Ld_i;
assign PllStatusBits_b32[14] = PllFmc1Status_i;
assign PllStatusBits_b32[13] = PllFmc1RefMon_i;
assign PllStatusBits_b32[12] = PllFmc12SFpgaP_ik;
assign PllStatusBits_b32[11] = PllFmc2Ld_i;
assign PllStatusBits_b32[10] = PllFmc2Status_i;
assign PllStatusBits_b32[9] = PllFmc2RefMon_i;
assign PllStatusBits_b32[8] = PllFmc22SFpgaP_ik;
assign PllStatusBits_b32[7] = PllSysLd_i;
assign PllStatusBits_b32[6] = PllSysStatus_i;
assign PllStatusBits_b32[5] = PllSysRefMon_i;
assign PllStatusBits_b32[4] = PllSys2SFpgaP_ik;
assign PllStatusBits_b32[3] = PllDdsLd_i;
assign PllStatusBits_b32[2] = PllDdsStatus_i;
assign PllStatusBits_b32[1] = PllDdsRefMon_i;
assign PllStatusBits_b32[0] = PllDds2SFpgaP_ik;
assign PllFmc1Ref1_ok = Clk_k;
assign PllFmc2Ref1_ok = Clk_k;
assign PllSysRef12_ok = Clk_k;
assign PllDdsClk_ok = Clk_k;
//#####################################
// Non SPI DAC Control bits
//#####################################
assign PllDacClrn_orn = 1'b1;
assign PllDacLDac_on = 1'b0; //always updating the dac after a new value is loaded
endmodule
`timescale 1ns/1ns
module SystemFpga (
// VME BUS SIGNALS
input UseGa_i,
input [4:0] ManualAddress_ib5,
input [4:0] VmeGa_ib5n,
input VmeGaP_in,
output [7:1] VmeIrq_ob7, // Active high because of the connection on the board
inout [31:0] VmeD_iob32,
output VmeDtAckOe_oe,
output VmeDtAck_on,
inout [31:1] VmeA_iob31,
inout VmeLword_io,
input [5:0] VmeAm_ib6,
input VmeAs_in,
input VmeSysClk_ik,
input VmeWrite_in,
output VmeDOeN_oen,
output VmeDDirVfcToVme_o,
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
input [2:1] VmeDs_inb2,
output VmeAOeN_oen,
output VmeADirVfcToVme_o,
output VmeRetryOe_oe,
output VmeRetry_on,
output VmeBerr_o, // Active high because of the connection on the board
input VmeSysReset_in,
input VmeTck_i,
input VmeTrst_i,
output VmeTdoOe_oe,
output VmeTdo_o,
input VmeTdi_i,
input VmeTms_i,
// CLOCKS
input VcTcXo_ik,
input Si57x_ik,
// PUSH BUTTON
inout PushButton_ion,
// SWITCHES
input [1:0] Switch_ib2,
// Front Panel GPIO
output [7:0] FpLed_onb8,
// Front Panel GPIO
output FpGpIo1OutputMode_o,
output FpGpIo2OutputMode_o,
output FpGpIo34OutputMode_o,
// Application FPGA Programming Pins
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgClk_io,
inout [1:0] AFpgaProgM_iob2,
inout AFpgaProgCsi_io,
inout AFpgaProgRdWr_io,
inout AFpgaProgInit_io,
// Application FPGA Clk
output SysAppClk_o,
// Application FPGA Slow Communication
inout [2:1] SysAppSlow_iob2,
// Flash PROMs Interfaces
output FlashSFpgaD_o,
output FlashSFpgaClk_ok,
output FlashSFpgaCs_on,
input FlashSFpgaQ_i,
output FlashAFpgaD_o,
output FlashAFpgaClk_ok,
output FlashAFpgaCs_on,
input FlashAFpgaQ_i,
// Voltage Monitoring ADC interface
output VAdcSClk_ok,
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_on,
// VAdj Control
output VAdjCs_on,
output VAdjSClk_ok,
output VAdjDin_o,
output VAdjInhibit_ozn,
output VAdjSpi_o,
// PLLs control
input PllFmc1Ld_i,
input PllFmc1Status_i,
input PllFmc1RefMon_i,
output PllFmc1RefSel_o,
output PllFmc1Ref1_ok,
output PllFmc1Pd_on,
output PllFmc1Synch_on,
output PllFmc1Reset_orn,
output PllFmc1SClk_ok,
inout PllFmc1SDio_io,
input PllFmc1Sdo_i,
output PllFmc1Cs_on,
input PllFmc12SFpgaP_ik,
input PllFmc2Ld_i,
input PllFmc2Status_i,
input PllFmc2RefMon_i,
output PllFmc2RefSel_o,
output PllFmc2Ref1_ok,
output PllFmc2Pd_on,
output PllFmc2Synch_on,
output PllFmc2Reset_orn,
output PllFmc2SClk_ok,
inout PllFmc2SDio_io,
input PllFmc2Sdo_i,
output PllFmc2Cs_on,
input PllFmc22SFpgaP_ik,
input PllSysLd_i,
input PllSysStatus_i,
input PllSysRefMon_i,
output PllSysRefSel_o,
output PllSysRef12_ok,
output PllSysPd_on,
output PllSysSynch_on,
output PllSysReset_orn,
output PllSysSClk_ok,
inout PllSysSDio_io,
input PllSysSdo_i,
output PllSysCs_on,
input PllSys2SFpgaP_ik,
input PllDdsLd_i,
input PllDdsStatus_i,
input PllDdsRefMon_i,
output PllDdsRefSel_o,
output PllDdsPd_on,
output PllDdsSynch_on,
output PllDdsReset_orn,
output PllDdsClk_ok,
output PllDdsSClk_ok,
inout PllDdsSDio_io,
input PllDdsSdo_i,
output PllDdsCs_on,
input PllDds2SFpgaP_ik,
// PLL DAC
output PllDacSClk_ok,
output PllDacSynch_on,
output PllDacDin_o,
input PllDacDout_i,
output PllDacClrn_orn,
output PllDacLDac_on
);
`define dly 1
wire [31:0] InterruptConfigReg_b32, GenericOutputReg1, PllConfigBits_b32, GenericOutputReg3;
wire [31:0] DatGenericOutputRegsrO_b32;
wire StbGenericOutputRegs, AckGenericOutputRegs;
wire VmeAccessForLed;
wire RstForLed;
//####################################
// FP Leds
//####################################
Monostable i_VmeAccessMonostable(
.AsynchIn_ia(StbMaster),
.Clk_ik(Clk_k),
.SynchOutput_oq(VmeAccessForLed));
Monostable i_ClearMonostable(
.AsynchIn_ia(Rst_rq),
.Clk_ik(Clk_k),
.SynchOutput_oq(RstForLed));
assign FpLed_onb8[0] = VmeAccessForLed ? 1'b0 : 1'bz;
assign FpLed_onb8[1] = (~&VmeIrq_ob7) ? 1'b0 : 1'bz;
assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz;
assign FpLed_onb8[3] = RstForLed ? 1'b0 : 1'bz;
reg [21:0] Si57xDivider_c = 'd0;
wire Si57xDivided = Si57xDivider_c[21];
always @(posedge Si57x_ik) Si57xDivider_c <= #`dly Si57xDivider_c + 1'b1;
reg [21:0] VcTcXoDivider_c = 'd0;
wire VcTcXoDivided = VcTcXoDivider_c[21];
always @(posedge VcTcXo_ik) VcTcXoDivider_c <= #`dly VcTcXoDivider_c + 1'b1;
reg [21:0] VmeSysClkDivider_c = 'd0;
wire VmeSysClkDivided = VmeSysClkDivider_c[21];
always @(posedge VmeSysClk_ik) VmeSysClkDivider_c <= #`dly VmeSysClkDivider_c + 1'b1;
reg a_FpLed7;
always @* case(Switch_ib2)
2'b00: a_FpLed7 = Si57xDivided;
2'b01: a_FpLed7 = VcTcXoDivided;
2'b10: a_FpLed7 = VmeSysClkDivided;
default: a_FpLed7 = VcTcXoDivided;
endcase
assign FpLed_onb8[4] = Si57xDivided ? 1'bz : 1'b0;
assign FpLed_onb8[5] = VcTcXoDivided ? 1'bz : 1'b0;
assign FpLed_onb8[6] = VmeSysClkDivided ? 1'bz : 1'b0;
assign FpLed_onb8[7] = a_FpLed7 ? 1'bz : 1'b0;
//####################################
// FP GP IO
//####################################
assign FpGpIo1OutputMode_o = 1'b0;
assign FpGpIo2OutputMode_o = 1'b1;
assign FpGpIo34OutputMode_o = 1'b1;
//####################################
// Clock
//####################################
wire Clk_k= Si57x_ik;
//#####################################
// Reset Signal Generation
//#####################################
reg Rst_rq;
reg [1:0] VmeSysReset_dx;
always @(posedge Clk_k) VmeSysReset_dx <= #`dly {VmeSysReset_dx[0], VmeSysReset_in};
wire a_VmeSysReset_nq = VmeSysReset_dx[1];
wire DeboucedPushButton_q;
Debouncer #(.g_CounterWidth(16), .g_SynchDepth(3)) i_Debouncer (
.Clk_ik(Clk_k),
.BouncingSignal_ia(PushButton_ion),
.DebouncedSignal_oq(DeboucedPushButton_q));
always @(posedge Clk_k) Rst_rq <= #`dly ~DeboucedPushButton_q || ~a_VmeSysReset_nq;
//#####################################
// VME Interface
//#####################################
wire SpiIdle, SpiWaitingData;
wire IntAcknowledged;
wire AssertInterrupt;
wire VmeDtAck_n, VmeDOe;
wire [7:1] VmeIrq_b7n;
assign VmeDtAck_on = 1'b0;
assign VmeDtAckOe_oe = ~VmeDtAck_n;
assign VmeDOeN_oen = ~VmeDOe;
assign VmeAOeN_oen = 1'b0;
assign VmeADirVfcToVme_o = 1'b0;
assign VmeRetryOe_oe = 1'b0;
assign VmeRetry_on = 1'b1;
assign VmeBerr_o = 1'b0;
assign VmeIrq_ob7 = ~VmeIrq_b7n;
assign VmeTdoOe_oe = 1'b0;
wire [2:0] InterrupLevel = InterruptConfigReg_b32[30:28];
wire [7:0] IntVector_b8 = InterruptConfigReg_b32[7:0];
wire [7:0] IntSource_b8;
assign IntSource_b8[7:2] = GenericOutputReg1[7:2];
assign IntSource_b8[1] = SpiIdle;
assign IntSource_b8[0] = SpiWaitingData;
wire StbMaster, AckMaster, Cyc, We;
wire [21:0] Adr_b22;
wire [31:0] DatMasterI_b32, DatMasterO_b32;
VmeInterfaceWB i_VmeInterface(
.rst_i(Rst_rq),
.clk_i(Clk_k),
.adr_o(Adr_b22),
.dat_o(DatMasterO_b32),
.dat_i(DatMasterI_b32),
.we_o(We),
.stb_o(StbMaster),
.ack_i(AckMaster),
.cyc_o(Cyc),
.UseGa_i(UseGa_i),
.ManualAddress_i(ManualAddress_ib5),
.vme_ga(VmeGa_ib5n),
.vme_gap(VmeGaP_in),
.vme_as(VmeAs_in),
.vme_ds1(VmeDs_inb2[1]),
.vme_ds2(VmeDs_inb2[2]),
.vme_am(VmeAm_ib6),
.vme_wr(VmeWrite_in),
.vme_dtack(VmeDtAck_n),
.vme_lword(VmeLword_io),
.vme_addr(VmeA_iob31),
.vme_data(VmeD_iob32),
.VmeDOe_o(VmeDOe),
.VmeDDirFpgaToVme_o(VmeDDirVfcToVme_o),
.vme_iackinn(VmeIackIn_in),
.vme_iackn(VmeIack_in),
.vme_iack_outn(VmeIackOut_on),
.vme_irqn(VmeIrq_b7n),
.intlev_reg(InterrupLevel),
.IrqVector_i(IntVector_b8),
.assert_interrupt(AssertInterrupt),
.clear_int(IntAcknowledged));
wire [31:0] DatIntManagerO_b32;
wire StbIntManager, AckIntMAnager;
InterruptManagerWB i_InterruptManager(
.Clk_ik(Clk_k),
.Rst_irq(Rst_rq),
.int_enable({1'b1}),
.Cyc_i(Cyc),
.Stb_i(StbIntManager),
.We_i(We),
.Adr_ib2(Adr_b22[1:0]),
.Dat_ib32(DatMasterO_b32),
.Dat_oab32(DatIntManagerO_b32),
.Ack_oa(AckIntMAnager),
.interrupt_in(IntSource_b8),
.int_acknowledged(IntAcknowledged),
.clear_all({1'b0}),
.assert_interrupt(AssertInterrupt));
AddressDecoderWBSys i_AddressDecoderWB(
.Adr_ib22(Adr_b22),
.Stb_i(StbMaster),
.Dat_ob32(DatMasterI_b32),
.Ack_o(AckMaster),
.DatIntManager_ib32(DatIntManagerO_b32),
.AckIntMAnager_i(AckIntMAnager),
.StbIntManager_o(StbIntManager),
.DatGenericOutputRegs_ib32(DatGenericOutputRegsrO_b32),
.AckGenericOutputRegs_i(AckGenericOutputRegs),
.StbGenericOutputRegs_o(StbGenericOutputRegs),
.DatGenericInputRegs_ib32(DatGenericInputRegsrO_b32),
.AckGenericInputRegs_i(AckGenericInputRegs),
.StbGenericInputRegs_o(StbGenericInputRegs),
.DatSlv2SerWB_ib32(DatSlv2SerWBO_b32),
.AckSlv2SerWB_i(AckSlv2SerWB),
.StbSlv2SerWB_o(StbSlv2SerWB),
.DatSpiMaster_ib32(DatSpiMaster_b32),
.AckSpiMaster_i(AckSpiMaster),
.StbSpiMaster_o(StbSpiMaster));
//#####################################
// GenericOutput Registers
//#####################################
Generic4OutputRegs #(.Reg2Default(32'h8888)) i_Generic4OutputRegs(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.Stb_i(StbGenericOutputRegs),
.We_i(We),
.Adr_ib2(Adr_b22[1:0]),
.Dat_ib32(DatMasterO_b32),
.Dat_oab32(DatGenericOutputRegsrO_b32),
.Ack_oa(AckGenericOutputRegs),
.Reg0Value_ob32(InterruptConfigReg_b32),
.Reg1Value_ob32(GenericOutputReg1),
.Reg2Value_ob32(PllConfigBits_b32),
.Reg3Value_ob32(GenericOutputReg3));
//#####################################
// GenericInput Registers
//#####################################
wire [31:0] PllStatusBits_b32, GenericInputReg1, GenericInputReg2, GenericInputReg3;
wire [31:0] DatGenericInputRegsrO_b32;
wire StbGenericInputRegs, AckGenericInputRegs;
Generic4InputRegs i_Generic4InputRegs(
.Rst_irq(Rst_rq),
.Cyc_i(Cyc),
.Stb_i(StbGenericInputRegs),
.Adr_ib2(Adr_b22[1:0]),
.Dat_oab32(DatGenericInputRegsrO_b32),
.Ack_oa(AckGenericInputRegs),
.Reg0Value_ib32(PllStatusBits_b32),
.Reg1Value_ib32(GenericInputReg1),
.Reg2Value_ib32(GenericInputReg2),
.Reg3Value_ib32(GenericInputReg3));
//#####################################
// WB Serial Interface To The A-FPGA
//#####################################
wire [31:0] DatSlv2SerWBO_b32;
wire StbSlv2SerWB, AckSlv2SerWB;
Slv2SerWB i_Slv2SerWB(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.We_i(We),
.Adr_ib21(Adr_b22[20:0]),
.Dat_ib32(DatMasterO_b32),
.Stb_i(StbSlv2SerWB),
.Dat_ob32(DatSlv2SerWBO_b32),
.Ack_o(AckSlv2SerWB),
.SerClk_ok(SysAppClk_o),
.SerDat_o(SysAppSlow_iob2[1]),
.SerCntrl_o(SysAppSlow_iob2[2]),
.Stb_o(AFpgaProgD_iob8[7]),
.SerClk_ik(AFpgaProgD_iob8[6]),
.SerDat_i(AFpgaProgD_iob8[5]),
.Ack_i(AFpgaProgD_iob8[4]));
//#####################################
// SPI master
//#####################################
wire [31:0] SpiSS_nb32, SpiMiSo_b32;
wire SpiMoSi, SpiSClk_k;
wire StbSpiMaster, AckSpiMaster;
wire [31:0] DatSpiMaster_b32;
assign SpiMiSo_b32[31] = SpiMoSi;
assign SpiMiSo_b32[8] = FlashSFpgaQ_i; //Think about removing it and placing it in a special place (CSR space)
assign FlashSFpgaCs_on = SpiSS_nb32[8]; //Think about removing it and placing it in a special place (CSR space)
assign FlashSFpgaD_o = SpiMoSi; //Think about removing it and placing it in a special place (CSR space)
assign FlashSFpgaClk_ok = SpiSClk_k; //Think about removing it and placing it in a special place (CSR space)
assign SpiMiSo_b32[7] = FlashAFpgaQ_i;
assign FlashAFpgaCs_on = SpiSS_nb32[7];
assign FlashAFpgaD_o = SpiMoSi;
assign FlashAFpgaClk_ok = SpiSClk_k;
assign SpiMiSo_b32[6] = VAdcDout_i;
assign VAdcCs_on = SpiSS_nb32[6];
assign VAdcDin_o = SpiMoSi;
assign VAdcSClk_ok = SpiSClk_k;
assign SpiMiSo_b32[5] = PllFmc1Sdo_i;
assign PllFmc1Cs_on = SpiSS_nb32[5];
assign PllFmc1SDio_io = SpiMoSi;
assign PllFmc1SClk_ok = SpiSClk_k;
assign SpiMiSo_b32[4] = PllFmc2Sdo_i;
assign PllFmc2Cs_on = SpiSS_nb32[4];
assign PllFmc2SDio_io = SpiMoSi;
assign PllFmc2SClk_ok = SpiSClk_k;
assign SpiMiSo_b32[3] = PllSysSdo_i;
assign PllSysCs_on = SpiSS_nb32[3];
assign PllSysSDio_io = SpiMoSi;
assign PllSysSClk_ok = SpiSClk_k;
assign SpiMiSo_b32[2] = PllDdsSdo_i;
assign PllDdsCs_on = SpiSS_nb32[2];
assign PllDdsSDio_io = SpiMoSi;
assign PllDdsSClk_ok = SpiSClk_k;
assign SpiMiSo_b32[1] = SpiMoSi; //in feedback as the module doesn't have a Dout: this way at least we read the last sent.
assign VAdjCs_on = SpiSS_nb32[1];
assign VAdjDin_o = SpiMoSi;
assign VAdjSClk_ok = SpiSClk_k;
assign VAdjSpi_o = 1'b1; //we keep it in SPI mode
assign VAdjInhibit_ozn = 1'bz; //we keep the generator on
assign SpiMiSo_b32[0] = PllDacDin_o; //in feedback as the module doesn't have a Dout: this way at least we read the last sent.
assign PllDacSynch_on = SpiSS_nb32[0];
assign PllDacDin_o = SpiMoSi;
assign PllDacSClk_ok = SpiSClk_k;
SpiMasterWB i_SpiMasterWB(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.We_i(We),
.Adr_ib3(Adr_b22[2:0]),
.Dat_ib32(DatMasterO_b32),
.Stb_i(StbSpiMaster),
.Dat_oab32(DatSpiMaster_b32),
.Ack_oa(AckSpiMaster),
.WaitingNewData_o(SpiWaitingData),
.ModuleIdle_o(SpiIdle),
.SClk_o(SpiSClk_k),
.MoSi_o(SpiMoSi),
.MiSo_ib32(SpiMiSo_b32),
.SS_onb32(SpiSS_nb32));
//#####################################
// Non SPI PLLs Control bits
//#####################################
assign PllFmc1RefSel_o = PllConfigBits_b32[15];
assign PllFmc1Pd_on = PllConfigBits_b32[14];
assign PllFmc1Synch_on = PllConfigBits_b32[13];
assign PllFmc1Reset_orn = PllConfigBits_b32[12];
assign PllFmc2RefSel_o = PllConfigBits_b32[11];
assign PllFmc2Pd_on = PllConfigBits_b32[10];
assign PllFmc2Synch_on = PllConfigBits_b32[9];
assign PllFmc2Reset_orn = PllConfigBits_b32[8];
assign PllSysRefSel_o = PllConfigBits_b32[7];
assign PllSysPd_on = PllConfigBits_b32[6];
assign PllSysSynch_on = PllConfigBits_b32[5];
assign PllSysReset_orn = PllConfigBits_b32[4];
assign PllDdsRefSel_o = PllConfigBits_b32[3];
assign PllDdsPd_on = PllConfigBits_b32[2];
assign PllDdsSynch_on = PllConfigBits_b32[1];
assign PllDdsReset_orn = PllConfigBits_b32[0];
assign PllStatusBits_b32[31:16] = 16'h0;
assign PllStatusBits_b32[15] = PllFmc1Ld_i;
assign PllStatusBits_b32[14] = PllFmc1Status_i;
assign PllStatusBits_b32[13] = PllFmc1RefMon_i;
assign PllStatusBits_b32[12] = PllFmc12SFpgaP_ik;
assign PllStatusBits_b32[11] = PllFmc2Ld_i;
assign PllStatusBits_b32[10] = PllFmc2Status_i;
assign PllStatusBits_b32[9] = PllFmc2RefMon_i;
assign PllStatusBits_b32[8] = PllFmc22SFpgaP_ik;
assign PllStatusBits_b32[7] = PllSysLd_i;
assign PllStatusBits_b32[6] = PllSysStatus_i;
assign PllStatusBits_b32[5] = PllSysRefMon_i;
assign PllStatusBits_b32[4] = PllSys2SFpgaP_ik;
assign PllStatusBits_b32[3] = PllDdsLd_i;
assign PllStatusBits_b32[2] = PllDdsStatus_i;
assign PllStatusBits_b32[1] = PllDdsRefMon_i;
assign PllStatusBits_b32[0] = PllDds2SFpgaP_ik;
assign PllFmc1Ref1_ok = Clk_k;
assign PllFmc2Ref1_ok = Clk_k;
assign PllSysRef12_ok = Clk_k;
assign PllDdsClk_ok = Clk_k;
//#####################################
// Non SPI DAC Control bits
//#####################################
assign PllDacClrn_orn = 1'b1;
assign PllDacLDac_on = 1'b0; //always updating the dac after a new value is loaded
endmodule
\ No newline at end of file
trunk/hdl/design/VmeInterfaceWB.v
View file @ 8cac29ef
......@@ -57,9 +57,6 @@ wire [4:0] base_addr;
wire gap_error;
wire selected;
reg dav_reg;
reg [31:0] data_in_reg;
wire valid_am;
reg [2:0] state;
......@@ -246,4 +243,4 @@ end
endmodule
\ No newline at end of file
trunk/software/VfcRegistersMap.py
View file @ 8cac29ef
from VmeFunctions import *
class VfcRegisters:
###############################################################################
###############################################################################
# REGISTER SPACE
###############################################################################
###############################################################################
def __init__(self, Slot):
self.Slot = Slot
BoardBaseAddress = Slot*2**24
......
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