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VME FMC Carrier VFC
Commits
9bd86086
Commit
9bd86086
authored
Feb 07, 2011
by
Andrea Boccardi
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...
parent
e723ed57
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2 changed files
with
16 additions
and
9 deletions
+16
-9
SystemFpga.v
trunk/hdl/design/SystemFpga.v
+9
-6
VmeToWishBone.v
trunk/hdl/design/VmeToWishBone.v
+7
-3
No files found.
trunk/hdl/design/SystemFpga.v
View file @
9bd86086
...
...
@@ -433,8 +433,8 @@ assign FpGpIo34OutputMode_o = 1'b1;
// Clock
//####################################
//
assign Clk_k= Si57x_ik;
assign
Clk_k
=
VcTcXo_ik
;
assign
Clk_k
=
Si57x_ik
;
//
assign Clk_k= VcTcXo_ik;
//#####################################
...
...
@@ -474,6 +474,8 @@ assign IntSource_b8[7:2] = GenericOutputReg1[7:2];
assign
IntSource_b8
[
1
]
=
SpiIdle
;
assign
IntSource_b8
[
0
]
=
SpiWaitingData
;
wire
[
1
:
0
]
DebugVmeState
;
VmeToWishBone
i_VmeInterface
(
.
Rst_irq
(
Rst_rq
)
,
.
Clk_ik
(
Clk_k
)
,
...
...
@@ -507,7 +509,8 @@ VmeToWishBone i_VmeInterface(
.
ManualAddress_ib5
(
ManualAddress_ib5
)
,
.
AssertInterrupt_i
(
AssertInterrupt
)
,
.
ClearInt_op
(
IntAcknowledged
)
,
.
DebugOut_ob4
(
VmeDebug_b4
))
;
.
DebugOut_ob4
(
VmeDebug_b4
)
,
.
State_oq
(
DebugVmeState
))
;
InterruptManagerWB
i_InterruptManager
(
.
Clk_ik
(
Clk_k
)
,
...
...
@@ -620,9 +623,9 @@ assign AFpgaProgProgram_o = 1'bz;
assign
SpiMiSo_b32
[
31
]
=
SpiMoSi
;
assign
SpiMiSo_b32
[
30
]
=
AFpgaProgD_iob8
[
0
]
;
assign
AFpgaProgD_iob8
[
3
]
=
SpiSS_nb32
[
30
]
;
assign
AFpgaProgD_iob8
[
2
]
=
SpiMoSi
;
assign
AFpgaProgD_iob8
[
1
]
=
SpiSClk_k
;
assign
AFpgaProgD_iob8
[
3
]
=
|
DebugVmeState
;
assign
AFpgaProgD_iob8
[
2
]
=
DebugVmeState
[
1
]
;
assign
AFpgaProgD_iob8
[
1
]
=
DebugVmeState
[
0
]
;
assign
SpiMiSo_b32
[
8
]
=
FlashSFpgaQ_i
;
//Think about removing it and placing it in a special place (CSR space)
assign
FlashSFpgaCs_on
=
SpiSS_nb32
[
8
]
;
//Think about removing it and placing it in a special place (CSR space)
...
...
trunk/hdl/design/VmeToWishBone.v
View file @
9bd86086
...
...
@@ -35,7 +35,9 @@ module VmeToWishBone(
input
AssertInterrupt_i
,
output
reg
ClearInt_op
,
output
[
3
:
0
]
DebugOut_ob4
)
;
output
[
3
:
0
]
DebugOut_ob4
,
output
[
1
:
0
]
State_oq
)
;
// Board Base Address
...
...
@@ -86,6 +88,8 @@ localparam s_Idle = 2'b00,
always
@
(
posedge
Clk_ik
)
State_q
<=
Rst_irq
?
s_Idle
:
NextState_a
;
assign
State_oq
=
State_q
;
always
@*
begin
NextState_a
=
State_q
;
case
(
State_q
)
...
...
@@ -93,9 +97,9 @@ always @* begin
if
(
VmeRWAccess_a
)
NextState_a
=
VmeWr_in
?
s_Read
:
s_Write
;
else
if
(
VmeIntAckAccess_a
)
NextState_a
=
s_IntAck
;
s_Write:
if
((
~
Ack_i
&&
~
Stb_oq
&&
~
VmeRWAccess_a
)
||
&
TimeoutCounter_cb8
)
NextState_a
=
s_Idle
;
if
((
~
Ack_i
&&
~
Stb_oq
&&
a_As_q
&&
a_Ds1_q
&&
a_Ds2_q
)
||
&
TimeoutCounter_cb8
)
NextState_a
=
s_Idle
;
s_Read:
if
((
~
Ack_i
&&
~
Stb_oq
&&
~
VmeRWAccess_a
)
||
&
TimeoutCounter_cb8
)
NextState_a
=
s_Idle
;
if
((
~
Ack_i
&&
~
Stb_oq
&&
a_As_q
&&
a_Ds1_q
&&
a_Ds2_q
)
||
&
TimeoutCounter_cb8
)
NextState_a
=
s_Idle
;
s_IntAck:
if
((
a_Ds1_q
&&
a_IAckIn_q
)
||
&
TimeoutCounter_cb8
)
NextState_a
=
s_Idle
;
default:
...
...
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