Commit af702851 authored by Andrea Boccardi's avatar Andrea Boccardi

debug leds and FP lemo changes

parent 936d57a5
Release 12.3 ngdbuild M.70d (nt)
Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3
ApplicationFpga.ngc ApplicationFpga.ngd
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p
xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
Reading NGO file
"C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ngc" ...
......@@ -18,6 +18,7 @@ Done...
Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'FpGpIo_iob4<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver
......@@ -37,12 +38,12 @@ Partition Implementation Status
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 11
Number of warnings: 12
Total memory usage is 83940 kilobytes
Total memory usage is 146700 kilobytes
Writing NGD file "ApplicationFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 3 sec
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "ApplicationFpga.bld"...
......@@ -6,3 +6,27 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
......@@ -107,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292838673" xil_pn:in_ck="4072638633301905625" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="6138376139572991401" xil_pn:start_ts="1292838659">
<transform xil_pn:end_ts="1292855052" xil_pn:in_ck="4072638633301905625" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="6138376139572991401" xil_pn:start_ts="1292855045">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -129,7 +129,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292839133" xil_pn:in_ck="-2234839937575114378" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1018860157679998437" xil_pn:start_ts="1292839127">
<transform xil_pn:end_ts="1292855056" xil_pn:in_ck="-2234839937575114378" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1018860157679998437" xil_pn:start_ts="1292855052">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -139,9 +139,11 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292839186" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292839133">
<transform xil_pn:end_ts="1292855079" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292855056">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ApplicationFpga.pcf"/>
<outfile xil_pn:name="ApplicationFpga_map.map"/>
<outfile xil_pn:name="ApplicationFpga_map.mrp"/>
......@@ -152,7 +154,7 @@
<outfile xil_pn:name="ApplicationFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292839259" xil_pn:in_ck="4718546783015930448" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292839186">
<transform xil_pn:end_ts="1292855116" xil_pn:in_ck="4718546783015930448" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292855079">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -167,7 +169,7 @@
<outfile xil_pn:name="ApplicationFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292839392" xil_pn:in_ck="-4700563312770461419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292839336">
<transform xil_pn:end_ts="1292855146" xil_pn:in_ck="-4700563312770461419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292855116">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -183,7 +185,12 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1292839259" xil_pn:in_ck="8541715597190098387" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292839237">
<transform xil_pn:end_ts="1292855153" xil_pn:in_ck="4850548760538546975" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1292855146">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="applicationfpga.isc"/>
</transform>
<transform xil_pn:end_ts="1292855116" xil_pn:in_ck="8541715597190098387" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292855105">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ApplicationFpga.twr"/>
......
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Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 11:00:36 2010
Mon Dec 20 15:25:03 2010
# NOTE: This file is designed to be imported into a spreadsheet program
......
Release 12.3 par M.70d (nt)
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Mon Dec 20 10:59:47 2010
PCBE13225:: Mon Dec 20 15:24:39 2010
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd
ApplicationFpga.ncd ApplicationFpga.pcf
......@@ -27,9 +27,9 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 257 out of 92,152 1%
Number used as logic: 233 out of 92,152 1%
Number using O6 output only: 217
Number of Slice LUTs: 264 out of 92,152 1%
Number used as logic: 238 out of 92,152 1%
Number using O6 output only: 222
Number using O5 output only: 14
Number using O5 and O6: 2
Number used as ROM: 0
......@@ -40,17 +40,17 @@ Slice Logic Utilization:
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 19
Number with same-slice register load: 18
Number used exclusively as route-thrus: 21
Number with same-slice register load: 20
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355
Number with an unused Flip Flop: 44 out of 355 12%
Number with an unused LUT: 98 out of 355 27%
Number of fully used LUT-FF pairs: 213 out of 355 60%
Number with an unused Flip Flop: 46 out of 355 12%
Number with an unused LUT: 91 out of 355 25%
Number of fully used LUT-FF pairs: 218 out of 355 61%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -95,8 +95,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 20 secs
Finished initial Timing Analysis. REAL time: 20 secs
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal.
......@@ -106,35 +106,36 @@ WARNING:Par:288 - The signal AFpgaProgD_iob8<2>_IBUF has no load. PAR will not
WARNING:Par:288 - The signal AFpgaProgD_iob8<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgCsi_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal FpGpIo_iob4<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgInit_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 1668 unrouted; REAL time: 23 secs
Phase 1 : 1691 unrouted; REAL time: 10 secs
Phase 2 : 1536 unrouted; REAL time: 29 secs
Phase 2 : 1560 unrouted; REAL time: 13 secs
Phase 3 : 731 unrouted; REAL time: 32 secs
Phase 3 : 730 unrouted; REAL time: 15 secs
Phase 4 : 731 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 43 secs
Phase 4 : 730 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 21 secs
Updating file: ApplicationFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 45 secs
Total REAL time to Router completion: 45 secs
Total CPU time to Router completion: 45 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Total REAL time to Router completion: 22 secs
Total CPU time to Router completion: 22 secs
Partition Implementation Status
-------------------------------
......@@ -152,8 +153,8 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|FpGpIo_iob4_2_OBUF_B | | | | | |
| UFG | BUFGMUX_X2Y1| No | 85 | 0.144 | 1.648 |
|FpGpIo_iob4_4_OBUF_B | | | | | |
| UFG | BUFGMUX_X2Y1| No | 84 | 0.138 | 1.640 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -170,8 +171,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 1.090ns| 7.243ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.264ns| | 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 0.419ns| 7.914ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.383ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -182,19 +183,19 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 11 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 48 secs
Total CPU time to PAR completion: 48 secs
Total REAL time to PAR completion: 24 secs
Total CPU time to PAR completion: 24 secs
Peak Memory Usage: 353 MB
Peak Memory Usage: 521 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 13
Number of warning messages: 14
Number of info messages: 0
Writing design to file ApplicationFpga.ncd
......
//! **************************************************************************
// Written by: Map M.70d on Mon Dec 20 10:59:44 2010
// Written by: Map M.70d on Mon Dec 20 15:24:37 2010
//! **************************************************************************
SCHEMATIC START;
......@@ -214,7 +214,7 @@ TIMEGRP SysAppClk_ik = BEL "Rst_rq" BEL "i_Ser2MstWB/AckI_d31_1" BEL
BEL "i_DebugRegs/Reg3Value_ob32_3" BEL "i_DebugRegs/Reg3Value_ob32_2"
BEL "i_DebugRegs/Reg3Value_ob32_1" BEL "i_DebugRegs/Reg3Value_ob32_0"
BEL "i_Ser2MstWB/Ack_o" BEL "i_Debouncer/DebouncedSignal_oq" BEL
"i_Debouncer/State_q" BEL "FpGpIo_iob4_2_OBUF_BUFG" BEL
"i_Debouncer/State_q" BEL "FpGpIo_iob4_4_OBUF_BUFG" BEL
"i_Ser2MstWB/Mshreg_StbI_d3_1" BEL "i_Ser2MstWB/StbI_d3_1" BEL
"i_Ser2MstWB/Mshreg_Rst_xb3_2" BEL "i_Ser2MstWB/Rst_xb3_2" BEL
"i_Ser2MstWB/Mshreg_SerCntrlIShReg_b32_20" BEL
......@@ -239,7 +239,7 @@ TIMEGRP SysAppClk_ik = BEL "Rst_rq" BEL "i_Ser2MstWB/AckI_d31_1" BEL
"i_Ser2MstWB/Rst_xb3_2_shift25" BEL "i_Ser2MstWB/Rst_xb3_2_shift26"
BEL "i_Ser2MstWB/Rst_xb3_2_shift27" BEL
"i_Ser2MstWB/Rst_xb3_2_shift28" BEL "i_Ser2MstWB/AckI_d31_30" BEL
"FpGpIo_iob4<4>" BEL "FpGpIo_iob4<2>" BEL "SysAppClk_ok";
"FpGpIo_iob4<4>" BEL "SysAppClk_ok";
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
SCHEMATIC END;
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="1.090" best="7.243" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.264" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.419" best="7.914" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.383" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 11:00:36 2010
Mon Dec 20 15:25:04 2010
All signals are completely routed.
WARNING:ParHelpers:361 - There are 11 loadless signals in this design. This design will cause Bitgen to issue DRC
WARNING:ParHelpers:361 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
AFpgaProgClk_io_IBUF
......@@ -19,5 +19,6 @@ WARNING:ParHelpers:361 - There are 11 loadless signals in this design. This desi
AFpgaProgM_iob2<0>_IBUF
AFpgaProgM_iob2<1>_IBUF
AFpgaProgRdWr_io_IBUF
FpGpIo_iob4<1>_IBUF
......@@ -15,17 +15,17 @@
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\IVI Foundation\IVI\bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\PROGRA~2\IVIFOU~1\VISA\WinNT\Bin;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files\PuTTY</td>
</tr>
<tr>
<td>XILINX</td>
......@@ -35,13 +35,6 @@
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
......@@ -515,31 +508,31 @@
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
</tr>
</TABLE>
</BODY> </HTML>
\ No newline at end of file
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 12.3 Map M.70d (nt)
Release 12.3 Map M.70d (nt64)
Xilinx Map Application Log File for Design 'ApplicationFpga'
Design Information
......@@ -11,7 +11,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 10:58:56 2010
Mapped Date : Mon Dec 20 15:24:16 2010
Mapping design into LUTs...
Running directed packing...
......@@ -20,54 +20,54 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 26 secs
Total CPU time at the beginning of Placer: 22 secs
Total REAL time at the beginning of Placer: 10 secs
Total CPU time at the beginning of Placer: 10 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:22fc166f) REAL time: 34 secs
Phase 1.1 Initial Placement Analysis (Checksum:22fc371c) REAL time: 13 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:22fc166f) REAL time: 34 secs
Phase 2.7 Design Feasibility Check (Checksum:22fc371c) REAL time: 14 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:22fc166f) REAL time: 34 secs
Phase 3.31 Local Placement Optimization (Checksum:22fc371c) REAL time: 14 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:92c41d7) REAL time: 41 secs
(Checksum:92c6284) REAL time: 17 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:92c41d7) REAL time: 41 secs
Phase 5.36 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:92c41d7) REAL time: 41 secs
Phase 6.30 Global Clock Region Assignment (Checksum:92c6284) REAL time: 17 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:92c41d7) REAL time: 42 secs
Phase 7.3 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:92c41d7) REAL time: 42 secs
Phase 8.5 Local Placement Optimization (Checksum:92c6284) REAL time: 17 secs
Phase 9.8 Global Placement
........................
.....
Phase 9.8 Global Placement (Checksum:3716193a) REAL time: 44 secs
.............................
........
Phase 9.8 Global Placement (Checksum:ac53ebd5) REAL time: 19 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:3716193a) REAL time: 44 secs
Phase 10.5 Local Placement Optimization (Checksum:ac53ebd5) REAL time: 19 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:5ae609a5) REAL time: 44 secs
Phase 11.18 Placement Optimization (Checksum:2eb3148e) REAL time: 19 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:5ae609a5) REAL time: 44 secs
Phase 12.5 Local Placement Optimization (Checksum:2eb3148e) REAL time: 19 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:d17f7f67) REAL time: 44 secs
Phase 13.34 Placement Validation (Checksum:85180713) REAL time: 19 secs
Total REAL time to Placer completion: 47 secs
Total CPU time to Placer completion: 42 secs
Total REAL time to Placer completion: 21 secs
Total CPU time to Placer completion: 20 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
......@@ -86,6 +86,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <FpGpIo_iob4<1>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
......@@ -98,16 +100,16 @@ Design Summary
Design Summary:
Number of errors: 0
Number of warnings: 11
Number of warnings: 12
Slice Logic Utilization:
Number of Slice Registers: 330 out of 184,304 1%
Number used as Flip Flops: 330
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 257 out of 92,152 1%
Number used as logic: 233 out of 92,152 1%
Number using O6 output only: 217
Number of Slice LUTs: 264 out of 92,152 1%
Number used as logic: 238 out of 92,152 1%
Number using O6 output only: 222
Number using O5 output only: 14
Number using O5 and O6: 2
Number used as ROM: 0
......@@ -118,17 +120,17 @@ Slice Logic Utilization:
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 19
Number with same-slice register load: 18
Number used exclusively as route-thrus: 21
Number with same-slice register load: 20
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355
Number with an unused Flip Flop: 44 out of 355 12%
Number with an unused LUT: 98 out of 355 27%
Number of fully used LUT-FF pairs: 213 out of 355 60%
Number with an unused Flip Flop: 46 out of 355 12%
Number with an unused LUT: 91 out of 355 25%
Number of fully used LUT-FF pairs: 218 out of 355 61%
Number of unique control sets: 10
Number of slice register sites lost
to control set restrictions: 25 out of 184,304 1%
......@@ -170,11 +172,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.47
Average Fanout of Non-Clock Nets: 4.49
Peak Memory Usage: 380 MB
Total REAL time to MAP completion: 49 secs
Total CPU time to MAP completion: 43 secs
Peak Memory Usage: 583 MB
Total REAL time to MAP completion: 21 secs
Total CPU time to MAP completion: 21 secs
Mapping completed.
See MAP report file "ApplicationFpga_map.mrp" for details.
Release 12.3 Map M.70d (nt)
Release 12.3 Map M.70d (nt64)
Xilinx Mapping Report File for Design 'ApplicationFpga'
Design Information
......@@ -11,21 +11,21 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 10:58:56 2010
Mapped Date : Mon Dec 20 15:24:16 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 11
Number of warnings: 12
Slice Logic Utilization:
Number of Slice Registers: 330 out of 184,304 1%
Number used as Flip Flops: 330
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 257 out of 92,152 1%
Number used as logic: 233 out of 92,152 1%
Number using O6 output only: 217
Number of Slice LUTs: 264 out of 92,152 1%
Number used as logic: 238 out of 92,152 1%
Number using O6 output only: 222
Number using O5 output only: 14
Number using O5 and O6: 2
Number used as ROM: 0
......@@ -36,17 +36,17 @@ Slice Logic Utilization:
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 19
Number with same-slice register load: 18
Number used exclusively as route-thrus: 21
Number with same-slice register load: 20
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 108 out of 23,038 1%
Number of LUT Flip Flop pairs used: 355
Number with an unused Flip Flop: 44 out of 355 12%
Number with an unused LUT: 98 out of 355 27%
Number of fully used LUT-FF pairs: 213 out of 355 60%
Number with an unused Flip Flop: 46 out of 355 1