Commit bd941eab authored by Andrea Boccardi's avatar Andrea Boccardi

...

parent af702851
......@@ -17,8 +17,16 @@ module Generic4OutputRegs
output reg [31:0] Reg0Value_ob32,
output reg [31:0] Reg1Value_ob32,
output reg [31:0] Reg2Value_ob32,
output reg [31:0] Reg3Value_ob32);
output reg [31:0] Reg3Value_ob32,
output reg Writing_o,
output reg WritingReg3_o,
output reg WritingABC_o);
always @(posedge Clk_ik) begin
Writing_o <= (Cyc_i && We_i && Stb_i);
WritingABC_o <= (Cyc_i && We_i && Stb_i)&& Dat_ib32==32'h0000_0abc;
end
always @(posedge Clk_ik)
if (Rst_irq) Reg0Value_ob32 <= #1 Reg0Default;
......@@ -32,9 +40,14 @@ always @(posedge Clk_ik)
if (Rst_irq) Reg2Value_ob32 <= #1 Reg2Default;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b10) Reg2Value_ob32 <= Dat_ib32;
always @(posedge Clk_ik)
always @(posedge Clk_ik) begin
WritingReg3_o <= 1'b0;
if (Rst_irq) Reg3Value_ob32 <= #1 Reg3Default;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==(2'b11)) Reg3Value_ob32 <= Dat_ib32;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==(2'b11)) begin
Reg3Value_ob32 <= Dat_ib32;
WritingReg3_o <= 1'b1;
end
end
assign Ack_oa = Stb_i&&Cyc_i;
......
......@@ -371,10 +371,6 @@ Monostable i_ClearMonostable(
.Clk_ik(Clk_k),
.SynchOutput_oq(RstForLed));
assign FpLed_onb8[0] = VmeAccessForLed ? 1'b0 : 1'bz;
assign FpLed_onb8[1] = (|VmeIrq_ob7) ? 1'b0 : 1'bz;
assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz;
assign FpLed_onb8[3] = RstForLed ? 1'b0 : 1'bz;
assign Si57xDivided = Si57xDivider_c[23];
always @(posedge Si57x_ik) Si57xDivider_c <= #`dly Si57xDivider_c + 1'b1;
......@@ -393,7 +389,11 @@ Monostable i_WriteCycleMonostable(
.AsynchIn_ia(WriteCycle),
.Clk_ik(Clk_k),
.SynchOutput_oq(WriteCycleLed));
assign FpLed_onb8[0] = VmeAccessForLed ? 1'b0 : 1'bz;
assign FpLed_onb8[1] = (|VmeIrq_ob7) ? 1'b0 : 1'bz;
assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz;
assign FpLed_onb8[3] = RstForLed ? 1'b0 : 1'bz;
assign FpLed_onb8[4] = Si57xDivided ? 1'bz : 1'b0;
assign FpLed_onb8[5] = VcTcXoDivided ? 1'bz : 1'b0;
assign FpLed_onb8[6] = VmeSysClkDivided ? 1'bz : 1'b0;
......@@ -411,7 +411,9 @@ assign FpGpIo34OutputMode_o = 1'b1;
// Clock
//####################################
assign Clk_k= Si57x_ik;
//assign Clk_k= Si57x_ik;
assign Clk_k= VcTcXo_ik;
//#####################################
// Reset Signal Generation
......
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