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Commit c3d17ad2 authored by Andrea Boccardi's avatar Andrea Boccardi
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Small changes in the files

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trunk/firmware/XilinxISE/SystemFpga/SFpga.bld
View file @ c3d17ad2
Release 12.3 ngdbuild M.70d (nt)
Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc
SFpga.ngd
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3
SFpga.ngc SFpga.ngd
Reading NGO file "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.ngc" ...
Gathering constraint information from source properties...
......@@ -41,10 +41,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 14
Total memory usage is 88036 kilobytes
Total memory usage is 155980 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 5 sec
Total CPU time to NGDBUILD completion: 5 sec
Total REAL time to NGDBUILD completion: 4 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "SFpga.bld"...
trunk/firmware/XilinxISE/SystemFpga/SFpga.cmd_log
View file @ c3d17ad2
......@@ -69,3 +69,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
trunk/firmware/XilinxISE/SystemFpga/SFpga.ncd
View file @ c3d17ad2
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngc
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngd
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trunk/firmware/XilinxISE/SystemFpga/SFpga.ngr
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trunk/firmware/XilinxISE/SystemFpga/SFpga.pad
View file @ c3d17ad2
Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 10:02:33 2010
Fri Dec 17 11:12:54 2010
# NOTE: This file is designed to be imported into a spreadsheet program
......@@ -296,7 +296,7 @@ E14||IOBS|IO_L40N_0|UNUSED||0|||||||||
E15|||GND||||||||||||
E16|VmeP0HwLowByteOe_o|IOB|IO_L49N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E17|||VCCAUX||||||||2.5||||
E18||IOBS|IO_L51N_0|UNUSED||0|||||||||
E18|Si57xOe_o|IOB|IO_L51N_0|OUTPUT|LVCMOS33|0|12|||||LOCATED|NO|NONE|
E19|||GND||||||||||||
E20|VmeWrite_in|IOB|IO_L57N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE|
E21|||VCCO_0|||0|||||3.30||||
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.par
View file @ c3d17ad2
Release 12.3 par M.70d (nt)
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
BQPLV2:: Fri Dec 17 10:01:26 2010
PCBE13225:: Fri Dec 17 11:12:22 2010
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
......@@ -26,11 +26,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 587
Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number using O5 and O6: 158
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -42,17 +42,17 @@ Slice Logic Utilization:
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 31
Number with same-slice register load: 22
Number used exclusively as route-thrus: 32
Number with same-slice register load: 23
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -63,8 +63,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99%
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2
IOB Slave Pads: 2
......@@ -99,8 +99,8 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 22 secs
Finished initial Timing Analysis. REAL time: 22 secs
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal VmeDs_inb2<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VmeDs_inb2<2>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -152,29 +152,29 @@ WARNING:Par:288 - The signal i_Core/i_InterruptManager/Mram_int_fifo1_RAMD_D1_O
Starting Router
Phase 1 : 5204 unrouted; REAL time: 25 secs
Phase 1 : 5227 unrouted; REAL time: 12 secs
Phase 2 : 4597 unrouted; REAL time: 31 secs
Phase 2 : 4601 unrouted; REAL time: 15 secs
Phase 3 : 1889 unrouted; REAL time: 44 secs
Phase 3 : 1750 unrouted; REAL time: 21 secs
Phase 4 : 1889 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 56 secs
Phase 4 : 1750 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 26 secs
Updating file: SFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 2 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 29 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 3 secs
Total REAL time to Router completion: 1 mins 4 secs
Total CPU time to Router completion: 1 mins 2 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 30 secs
Total REAL time to Router completion: 30 secs
Total CPU time to Router completion: 29 secs
Partition Implementation Status
-------------------------------
......@@ -192,18 +192,18 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Si57x_BUFG | BUFGMUX_X2Y4| No | 217 | 0.248 | 1.696 |
| Si57x_BUFG | BUFGMUX_X2Y4| No | 229 | 0.260 | 1.710 |
+---------------------+--------------+------+------+------------+-------------+
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.083 | 1.644 |
| VmeSysClk_ik_BUFGP | BUFGMUX_X2Y9| No | 6 | 0.009 | 1.640 |
+---------------------+--------------+------+------+------------+-------------+
| VcTcXo_ik_BUFGP | BUFGMUX_X3Y16| No | 6 | 0.083 | 1.644 |
+---------------------+--------------+------+------+------------+-------------+
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 15 | 0.009 | 1.515 |
| SysAppClk_ik_BUFGP | BUFGMUX_X3Y14| No | 16 | 0.186 | 1.693 |
+---------------------+--------------+------+------+------------+-------------+
| i_Core/Rst_rq | Local| | 213 | 0.000 | 6.628 |
| i_Core/Rst_rq | Local| | 223 | 0.000 | 7.868 |
+---------------------+--------------+------+------+------------+-------------+
|i_Core/i_VmeInterfac | | | | | |
| e/stb_o | Local| | 19 | 0.000 | 4.448 |
| e/stb_o | Local| | 19 | 0.000 | 4.686 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -220,11 +220,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.399ns| 7.934ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.347ns| | 0| 0
TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 1 | SETUP | 0.435ns| 7.898ns| 0| 0
20 MHz HIGH 50% | HOLD | 0.413ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 5.459ns| 2.874ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.459ns| | 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 4.464ns| 3.869ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.442ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -237,10 +237,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 47 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 8 secs
Total CPU time to PAR completion: 1 mins 7 secs
Total REAL time to PAR completion: 32 secs
Total CPU time to PAR completion: 32 secs
Peak Memory Usage: 369 MB
Peak Memory Usage: 546 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.pcf
View file @ c3d17ad2
//! **************************************************************************
// Written by: Map M.70d on Fri Dec 17 10:01:22 2010
// Written by: Map M.70d on Fri Dec 17 11:12:18 2010
//! **************************************************************************
SCHEMATIC START;
......@@ -255,6 +255,7 @@ COMP "DdsF_ob2<1>" LOCATE = SITE "A2" LEVEL 1;
COMP "DdsDrOver_i" LOCATE = SITE "G13" LEVEL 1;
COMP "PllFmc2Synch_on" LOCATE = SITE "V12" LEVEL 1;
COMP "DdsTxEnable_o" LOCATE = SITE "G8" LEVEL 1;
COMP "Si57xOe_o" LOCATE = SITE "E18" LEVEL 1;
COMP "VmeP0BunchSelectDir_o" LOCATE = SITE "G15" LEVEL 1;
COMP "VAdjSClk_ok" LOCATE = SITE "J2" LEVEL 1;
COMP "PllDacClrn_orn" LOCATE = SITE "Y21" LEVEL 1;
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.ptwx
View file @ c3d17ad2
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.399" best="7.934" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.347" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.459" best="2.874" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.459" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.435" best="7.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="4.464" best="3.869" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.442" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
trunk/firmware/XilinxISE/SystemFpga/SFpga.syr
View file @ c3d17ad2
Release 12.3 - xst M.70d (nt)
Release 12.3 - xst M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.16 secs
Total CPU time to Xst completion: 0.20 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.16 secs
Total CPU time to Xst completion: 0.20 secs
--> Reading design: SFpga.prj
......@@ -303,7 +303,6 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
Found 1-bit tristate buffer for signal <DdrDQ_iob16<1>> created at line 315
Found 1-bit tristate buffer for signal <DdrDQ_iob16<0>> created at line 315
Found 1-bit tristate buffer for signal <Si57xSDa_io> created at line 338
Found 1-bit tristate buffer for signal <Si57xOe_o> created at line 339
Found 1-bit tristate buffer for signal <DdsIOUpdate_io> created at line 347
Found 1-bit tristate buffer for signal <FpLed_onb8<0>> created at line 374
Found 1-bit tristate buffer for signal <FpLed_onb8<1>> created at line 375
......@@ -320,7 +319,7 @@ WARNING:Xst:653 - Signal <Gbit4Sys2App_o> is used but never assigned. This sourc
inferred 3 Adder/Subtractor(s).
inferred 69 D-type flip-flop(s).
inferred 1 Multiplexer(s).
inferred 34 Tristate(s).
inferred 33 Tristate(s).
Unit <SystemFpga> synthesized.
Synthesizing Unit <Monostable>.
......@@ -330,7 +329,7 @@ Synthesizing Unit <Monostable>.
Found 20-bit register for signal <Counter_c>.
Found 1-bit register for signal <SynchOutput_oq>.
Found 1-bit register for signal <AsynchIn_ax>.
Found 20-bit adder for signal <Counter_c[19]_GND_26_o_add_6_OUT> created at line 20.
Found 20-bit adder for signal <Counter_c[19]_GND_25_o_add_6_OUT> created at line 20.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 25 D-type flip-flop(s).
......@@ -344,7 +343,7 @@ Synthesizing Unit <Debouncer>.
Found 16-bit register for signal <Counter_c>.
Found 1-bit register for signal <DebouncedSignal_oq>.
Found 3-bit register for signal <BouncingSignal_x>.
Found 16-bit adder for signal <Counter_c[15]_GND_35_o_add_7_OUT> created at line 38.
Found 16-bit adder for signal <Counter_c[15]_GND_34_o_add_7_OUT> created at line 38.
Found 1-bit comparator equal for signal <n0003> created at line 31
Summary:
inferred 1 Adder/Subtractor(s).
......@@ -394,9 +393,9 @@ Synthesizing Unit <VmeInterfaceWB>.
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 9-bit adder for signal <AckTimeout_c[8]_GND_36_o_add_16_OUT> created at line 100.
Found 22-bit adder for signal <adr_o[21]_GND_36_o_add_48_OUT> created at line 200.
Found 1-bit 4-to-1 multiplexer for signal <_n0291> created at line 148.
Found 9-bit adder for signal <AckTimeout_c[8]_GND_35_o_add_16_OUT> created at line 100.
Found 22-bit adder for signal <adr_o[21]_GND_35_o_add_48_OUT> created at line 200.
Found 1-bit 4-to-1 multiplexer for signal <_n0284> created at line 148.
Found 1-bit 4-to-1 multiplexer for signal <_n0316> created at line 148.
Found 1-bit tristate buffer for signal <vme_data<31>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<30>> created at line 110
......@@ -430,7 +429,7 @@ Synthesizing Unit <VmeInterfaceWB>.
Found 1-bit tristate buffer for signal <vme_data<2>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<1>> created at line 110
Found 1-bit tristate buffer for signal <vme_data<0>> created at line 110
Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_36_o_equal_12_o> created at line 75
Found 8-bit comparator equal for signal <VmeBaseAddr[7]_GND_35_o_equal_12_o> created at line 75
Found 3-bit comparator equal for signal <vme_addr[3]_intlev_reg[2]_equal_43_o> created at line 178
Summary:
inferred 2 Adder/Subtractor(s).
......@@ -462,10 +461,10 @@ WARNING:Xst:647 - Input <Dat_ib32<30:11>> is never used. This port will be prese
Found 1-bit register for signal <fifo_empty>.
Found 1-bit register for signal <Stb_d>.
Found 1-bit register for signal <osc_clk>.
Found 4-bit subtractor for signal <int_counter[3]_GND_69_o_sub_23_OUT> created at line 101.
Found 4-bit adder for signal <int_counter[3]_GND_69_o_add_20_OUT> created at line 99.
Found 3-bit adder for signal <int_pointer_w[2]_GND_69_o_add_29_OUT> created at line 115.
Found 3-bit adder for signal <int_pointer_r[2]_GND_69_o_add_31_OUT> created at line 118.
Found 4-bit subtractor for signal <int_counter[3]_GND_68_o_sub_23_OUT> created at line 101.
Found 4-bit adder for signal <int_counter[3]_GND_68_o_add_20_OUT> created at line 99.
Found 3-bit adder for signal <int_pointer_w[2]_GND_68_o_add_29_OUT> created at line 115.
Found 3-bit adder for signal <int_pointer_r[2]_GND_68_o_add_31_OUT> created at line 118.
Found 32-bit 4-to-1 multiplexer for signal <Dat_oab32> created at line 165.
Found 3-bit comparator equal for signal <int_pointer_w[2]_int_pointer_r[2]_equal_42_o> created at line 132
Found 3-bit comparator equal for signal <n0078> created at line 134
......@@ -588,8 +587,8 @@ Synthesizing Unit <SpiMasterWB>.
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 12-bit adder for signal <TxCounter_cb12[11]_GND_78_o_add_40_OUT> created at line 138.
Found 16-bit adder for signal <TimeCounter_cb16[15]_GND_78_o_add_67_OUT> created at line 163.
Found 12-bit adder for signal <TxCounter_cb12[11]_GND_77_o_add_40_OUT> created at line 138.
Found 16-bit adder for signal <TimeCounter_cb16[15]_GND_77_o_add_67_OUT> created at line 163.
Found 1-bit 32-to-1 multiplexer for signal <a_SpiChannel_b5[4]_MiSo_ib32[31]_Mux_56_o> created at line 150.
Found 32-bit 7-to-1 multiplexer for signal <Dat_oab32> created at line 185.
Found 16-bit comparator equal for signal <TimeCounter_cb16[15]_a_WaitTime_b16[15]_equal_9_o> created at line 77
......@@ -650,8 +649,8 @@ Macro Statistics
5-bit 2-to-1 multiplexer : 1
7-bit 2-to-1 multiplexer : 1
9-bit 2-to-1 multiplexer : 1
# Tristates : 66
1-bit tristate buffer : 66
# Tristates : 65
1-bit tristate buffer : 65
# FSMs : 2
# Xors : 4
1-bit xor3 : 2
......@@ -902,9 +901,9 @@ Primitive and Black Box Usage:
# IBUFGDS : 6
# IOBUF : 32
# IOBUFDS : 2
# OBUF : 151
# OBUF : 152
# OBUFDS : 3
# OBUFT : 34
# OBUFT : 33
Device utilization summary:
---------------------------
......@@ -997,8 +996,8 @@ Delay: 8.328ns (Levels of Logic = 5)
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 2 0.525 1.047 i_Core/i_VmeInterface/adr_o_21_1 (i_Core/i_VmeInterface/adr_o_21_1)
LUT6:I1->O 4 0.254 0.912 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o12)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_4_o1)
LUT6:I1->O 4 0.254 0.912 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o13 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12)
LUT4:I1->O 1 0.235 0.688 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1 (i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1)
LUT5:I3->O 5 0.250 0.715 i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11 (i_Core/StbSpiMaster)
LUT6:I5->O 58 0.254 1.601 i_Core/i_AddressDecoderWB/Ack_o (i_Core/AckMaster)
LUT3:I2->O 32 0.254 1.291 i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o2 (i_Core/i_VmeInterface/NewAck_a_AckTimeout_c[8]_OR_27_o)
......@@ -1176,8 +1175,8 @@ Offset: 8.362ns (Levels of Logic = 6)
---------------------------------------- ------------
IBUF:I->O 2 1.228 1.047 VmeGa_ib5n_0_IBUF (VmeGa_ib5n_0_IBUF)
LUT6:I1->O 5 0.254 0.943 i_Core/i_VmeInterface/gap_error1 (i_Core/i_VmeInterface/gap_error)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o311 (N5)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o87_SW0 (N259)
LUT4:I1->O 2 0.235 0.725 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o311 (N5)
LUT6:I4->O 1 0.250 0.808 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_35_o_equal_12_o87_SW0 (N259)
LUT6:I3->O 12 0.235 0.909 i_Core/i_VmeInterface/selected (i_Core/i_VmeInterface/selected)
LUT5:I4->O 24 0.254 1.172 i_Core/i_VmeInterface/_n0350_inv1 (i_Core/i_VmeInterface/_n0350_inv)
FDRE:CE 0.302 i_Core/i_VmeInterface/adr_o_0
......@@ -1344,12 +1343,12 @@ i_Core/i_VmeInterface/stb_o| 2.049| | | |
=========================================================================
Total REAL time to Xst completion: 27.00 secs
Total CPU time to Xst completion: 26.61 secs
Total REAL time to Xst completion: 19.00 secs
Total CPU time to Xst completion: 19.43 secs
-->
Total memory usage is 154724 kilobytes
Total memory usage is 279568 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 126 ( 0 filtered)
......
trunk/firmware/XilinxISE/SystemFpga/SFpga.twr
View file @ c3d17ad2
--------------------------------------------------------------------------------
Release 12.3 Trace (nt)
Release 12.3 Trace (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
Design file: SFpga.ncd
Physical constraint file: SFpga.pcf
......@@ -26,19 +26,19 @@ INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
================================================================================
Timing constraint: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
44725 paths analyzed, 2980 endpoints analyzed, 0 failing endpoints
44725 paths analyzed, 2978 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 7.934ns.
Minimum period is 7.898ns.
--------------------------------------------------------------------------------
Paths for end point i_Core/i_VmeInterface/state_FSM_FFd2 (SLICE_X85Y108.A6), 108 paths
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_6 (SLICE_X59Y78.C4), 310 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.399ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_5 (FF)
Destination: i_Core/i_VmeInterface/state_FSM_FFd2 (FF)
Slack (setup path): 0.435ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/Config1_qb32_0 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_6 (FF)
Requirement: 8.333ns
Data Path Delay: 7.877ns (Levels of Logic = 6)
Clock Path Skew: -0.022ns (0.252 - 0.274)
Data Path Delay: 8.022ns (Levels of Logic = 5)
Clock Path Skew: 0.159ns (0.905 - 0.746)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -49,42 +49,40 @@ Slack (setup path): 0.399ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_5 to i_Core/i_VmeInterface/state_FSM_FFd2
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/Config1_qb32_0 to i_Core/i_SpiMasterWB/ShiftIn_qb32_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y96.AQ Tcko 0.525 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_5
SLICE_X85Y95.C2 net (fanout=4) 1.133 i_Core/i_VmeInterface/adr_o<5>
SLICE_X85Y95.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o12
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o11
SLICE_X85Y95.A6 net (fanout=4) 0.327 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o1
SLICE_X85Y95.A Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o12
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_4_o1_1
SLICE_X81Y90.B5 net (fanout=1) 0.955 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_4_o1
SLICE_X81Y90.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X81Y90.A5 net (fanout=5) 0.233 i_Core/StbSpiMaster
SLICE_X81Y90.A Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Ack_o
SLICE_X85Y108.B5 net (fanout=57) 2.491 i_Core/AckMaster
SLICE_X85Y108.B Tilo 0.259 i_Core/i_VmeInterface/state_FSM_FFd2
i_Core/i_VmeInterface/state_FSM_FFd2-In2
SLICE_X85Y108.A6 net (fanout=1) 0.545 i_Core/i_VmeInterface/state_FSM_FFd2-In2
SLICE_X85Y108.CLK Tas 0.373 i_Core/i_VmeInterface/state_FSM_FFd2
i_Core/i_VmeInterface/state_FSM_FFd2-In3
i_Core/i_VmeInterface/state_FSM_FFd2
SLICE_X69Y74.AQ Tcko 0.430 i_Core/i_SpiMasterWB/Config1_qb32<19>
i_Core/i_SpiMasterWB/Config1_qb32_0
SLICE_X67Y74.A4 net (fanout=2) 1.775 i_Core/i_SpiMasterWB/Config1_qb32<0>
SLICE_X67Y74.A Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<2>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o122
SLICE_X70Y69.C5 net (fanout=3) 1.434 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121
SLICE_X70Y69.CMUX Topcc 0.441 N261
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261
SLICE_X70Y71.A Tilo 0.235 N299
i_Core/i_SpiMasterWB/_n0817_inv_SW0
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X59Y78.C4 net (fanout=32) 0.637 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X59Y78.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<6>
i_Core/i_SpiMasterWB/ShiftIn_qb32_6_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_6
------------------------------------------------- ---------------------------
Total 7.877ns (2.193ns logic, 5.684ns route)
(27.8% logic, 72.2% route)
Total 8.022ns (1.992ns logic, 6.030ns route)
(24.8% logic, 75.2% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.416ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_5 (FF)
Destination: i_Core/i_VmeInterface/state_FSM_FFd2 (FF)
Slack (setup path): 0.738ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_5 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_6 (FF)
Requirement: 8.333ns
Data Path Delay: 7.860ns (Levels of Logic = 5)
Clock Path Skew: -0.022ns (0.252 - 0.274)
Data Path Delay: 7.553ns (Levels of Logic = 5)
Clock Path Skew: -0.007ns (0.166 - 0.173)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -95,39 +93,40 @@ Slack (setup path): 0.416ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_5 to i_Core/i_VmeInterface/state_FSM_FFd2
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_5 to i_Core/i_SpiMasterWB/ShiftIn_qb32_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y96.AQ Tcko 0.525 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_5
SLICE_X85Y95.C2 net (fanout=4) 1.133 i_Core/i_VmeInterface/adr_o<5>
SLICE_X85Y95.C Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o12
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o11
SLICE_X80Y91.A4 net (fanout=4) 0.783 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o1
SLICE_X80Y91.A Tilo 0.254 i_Core/i_Generic4OutputRegs/Cyc_i_Adr_ib2[1]_AND_148_o
i_Core/i_AddressDecoderWB/StbGenericOutputRegs_o1
SLICE_X81Y90.A1 net (fanout=4) 0.979 i_Core/StbGenericOutputRegs
SLICE_X81Y90.A Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Ack_o
SLICE_X85Y108.B5 net (fanout=57) 2.491 i_Core/AckMaster
SLICE_X85Y108.B Tilo 0.259 i_Core/i_VmeInterface/state_FSM_FFd2
i_Core/i_VmeInterface/state_FSM_FFd2-In2
SLICE_X85Y108.A6 net (fanout=1) 0.545 i_Core/i_VmeInterface/state_FSM_FFd2-In2
SLICE_X85Y108.CLK Tas 0.373 i_Core/i_VmeInterface/state_FSM_FFd2
i_Core/i_VmeInterface/state_FSM_FFd2-In3
i_Core/i_VmeInterface/state_FSM_FFd2
SLICE_X58Y76.DQ Tcko 0.476 i_Core/i_SpiMasterWB/TxCounter_cb12<5>
i_Core/i_SpiMasterWB/TxCounter_cb12_5
SLICE_X66Y74.B6 net (fanout=3) 1.068 i_Core/i_SpiMasterWB/TxCounter_cb12<5>
SLICE_X66Y74.B Tilo 0.235 i_Core/i_SpiMasterWB/Config1_qb32<6>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o124
SLICE_X70Y69.C4 net (fanout=3) 1.650 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o123
SLICE_X70Y69.CMUX Topcc 0.441 N261
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261
SLICE_X70Y71.A Tilo 0.235 N299
i_Core/i_SpiMasterWB/_n0817_inv_SW0
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X59Y78.C4 net (fanout=32) 0.637 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X59Y78.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<6>
i_Core/i_SpiMasterWB/ShiftIn_qb32_6_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_6
------------------------------------------------- ---------------------------
Total 7.860ns (1.929ns logic, 5.931ns route)
(24.5% logic, 75.5% route)
Total 7.553ns (2.014ns logic, 5.539ns route)
(26.7% logic, 73.3% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.430ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_12 (FF)
Destination: i_Core/i_VmeInterface/state_FSM_FFd2 (FF)
Slack (setup path): 0.795ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_13 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_6 (FF)
Requirement: 8.333ns
Data Path Delay: 7.847ns (Levels of Logic = 5)
Clock Path Skew: -0.021ns (0.252 - 0.273)
Data Path Delay: 7.598ns (Levels of Logic = 6)
Clock Path Skew: 0.095ns (0.994 - 0.899)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -138,42 +137,45 @@ Slack (setup path): 0.430ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_12 to i_Core/i_VmeInterface/state_FSM_FFd2
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_13 to i_Core/i_SpiMasterWB/ShiftIn_qb32_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X84Y97.CQ Tcko 0.525 i_Core/i_VmeInterface/adr_o<6>
i_Core/i_VmeInterface/adr_o_12
SLICE_X85Y95.B4 net (fanout=4) 0.862 i_Core/i_VmeInterface/adr_o<12>
SLICE_X85Y95.B Tilo 0.259 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o12
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o12
SLICE_X80Y91.A1 net (fanout=4) 1.041 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_71_o_equal_1_o11
SLICE_X80Y91.A Tilo 0.254 i_Core/i_Generic4OutputRegs/Cyc_i_Adr_ib2[1]_AND_148_o
i_Core/i_AddressDecoderWB/StbGenericOutputRegs_o1
SLICE_X81Y90.A1 net (fanout=4) 0.979 i_Core/StbGenericOutputRegs
SLICE_X81Y90.A Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Ack_o
SLICE_X85Y108.B5 net (fanout=57) 2.491 i_Core/AckMaster
SLICE_X85Y108.B Tilo 0.259 i_Core/i_VmeInterface/state_FSM_FFd2
i_Core/i_VmeInterface/state_FSM_FFd2-In2
SLICE_X85Y108.A6 net (fanout=1) 0.545 i_Core/i_VmeInterface/state_FSM_FFd2-In2
SLICE_X85Y108.CLK Tas 0.373 i_Core/i_VmeInterface/state_FSM_FFd2
i_Core/i_VmeInterface/state_FSM_FFd2-In3
i_Core/i_VmeInterface/state_FSM_FFd2
SLICE_X79Y97.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_13
SLICE_X81Y97.B1 net (fanout=4) 0.741 i_Core/i_VmeInterface/adr_o<13>
SLICE_X81Y97.B Tilo 0.259 i_Core/i_VmeInterface/adr_o<10>
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12
SLICE_X81Y97.A6 net (fanout=4) 0.554 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X81Y97.A Tilo 0.259 i_Core/i_VmeInterface/adr_o<10>
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
SLICE_X75Y88.B3 net (fanout=1) 1.560 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X75Y88.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X60Y77.C6 net (fanout=5) 1.716 i_Core/StbSpiMaster
SLICE_X60Y77.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X60Y77.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X59Y78.C4 net (fanout=32) 0.637 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X59Y78.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<6>
i_Core/i_SpiMasterWB/ShiftIn_qb32_6_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_6
------------------------------------------------- ---------------------------
Total 7.847ns (1.929ns logic, 5.918ns route)
(24.6% logic, 75.4% route)
Total 7.598ns (2.089ns logic, 5.509ns route)
(27.5% logic, 72.5% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_VmeInterface/adr_o_5 (SLICE_X84Y96.CE), 15 paths
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (SLICE_X63Y76.C6), 310 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.888ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/VmeBaseAddr_6 (FF)
Destination: i_Core/i_VmeInterface/adr_o_5 (FF)
Slack (setup path): 0.442ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/Config1_qb32_0 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF)
Requirement: 8.333ns
Data Path Delay: 7.433ns (Levels of Logic = 3)
Clock Path Skew: 0.023ns (0.780 - 0.757)
Data Path Delay: 8.012ns (Levels of Logic = 5)
Clock Path Skew: 0.156ns (0.902 - 0.746)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -184,35 +186,40 @@ Slack (setup path): 0.888ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_6 to i_Core/i_VmeInterface/adr_o_5
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/Config1_qb32_0 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X126Y127.CQ Tcko 0.476 i_Core/i_VmeInterface/VmeBaseAddr<6>
i_Core/i_VmeInterface/VmeBaseAddr_6
SLICE_X126Y126.A6 net (fanout=1) 0.527 i_Core/i_VmeInterface/VmeBaseAddr<6>
SLICE_X126Y126.A Tilo 0.235 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o86
SLICE_X85Y100.C6 net (fanout=2) 4.055 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
SLICE_X85Y100.C Tilo 0.259 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/selected
SLICE_X85Y100.D5 net (fanout=12) 0.258 i_Core/i_VmeInterface/selected
SLICE_X85Y100.DMUX Tilo 0.337 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/_n0350_inv1
SLICE_X84Y96.CE net (fanout=10) 0.973 i_Core/i_VmeInterface/_n0350_inv
SLICE_X84Y96.CLK Tceck 0.313 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_5
SLICE_X69Y74.AQ Tcko 0.430 i_Core/i_SpiMasterWB/Config1_qb32<19>
i_Core/i_SpiMasterWB/Config1_qb32_0
SLICE_X67Y74.A4 net (fanout=2) 1.775 i_Core/i_SpiMasterWB/Config1_qb32<0>
SLICE_X67Y74.A Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<2>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o122
SLICE_X70Y69.C5 net (fanout=3) 1.434 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121
SLICE_X70Y69.CMUX Topcc 0.441 N261
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261
SLICE_X70Y71.A Tilo 0.235 N299
i_Core/i_SpiMasterWB/_n0817_inv_SW0
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y76.C6 net (fanout=32) 0.627 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y76.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16>
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_16
------------------------------------------------- ---------------------------
Total 7.433ns (1.620ns logic, 5.813ns route)
(21.8% logic, 78.2% route)
Total 8.012ns (1.992ns logic, 6.020ns route)
(24.9% logic, 75.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.949ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/VmeBaseAddr_5 (FF)
Destination: i_Core/i_VmeInterface/adr_o_5 (FF)
Slack (setup path): 0.740ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_5 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF)
Requirement: 8.333ns
Data Path Delay: 7.372ns (Levels of Logic = 3)
Clock Path Skew: 0.023ns (0.780 - 0.757)
Data Path Delay: 7.543ns (Levels of Logic = 5)
Clock Path Skew: -0.015ns (0.254 - 0.269)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -223,35 +230,40 @@ Slack (setup path): 0.949ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_5 to i_Core/i_VmeInterface/adr_o_5
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_5 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X126Y127.BQ Tcko 0.476 i_Core/i_VmeInterface/VmeBaseAddr<6>
i_Core/i_VmeInterface/VmeBaseAddr_5
SLICE_X126Y126.A4 net (fanout=1) 0.466 i_Core/i_VmeInterface/VmeBaseAddr<5>
SLICE_X126Y126.A Tilo 0.235 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o86
SLICE_X85Y100.C6 net (fanout=2) 4.055 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
SLICE_X85Y100.C Tilo 0.259 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/selected
SLICE_X85Y100.D5 net (fanout=12) 0.258 i_Core/i_VmeInterface/selected
SLICE_X85Y100.DMUX Tilo 0.337 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/_n0350_inv1
SLICE_X84Y96.CE net (fanout=10) 0.973 i_Core/i_VmeInterface/_n0350_inv
SLICE_X84Y96.CLK Tceck 0.313 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_5
SLICE_X58Y76.DQ Tcko 0.476 i_Core/i_SpiMasterWB/TxCounter_cb12<5>
i_Core/i_SpiMasterWB/TxCounter_cb12_5
SLICE_X66Y74.B6 net (fanout=3) 1.068 i_Core/i_SpiMasterWB/TxCounter_cb12<5>
SLICE_X66Y74.B Tilo 0.235 i_Core/i_SpiMasterWB/Config1_qb32<6>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o124
SLICE_X70Y69.C4 net (fanout=3) 1.650 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o123
SLICE_X70Y69.CMUX Topcc 0.441 N261
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261
SLICE_X70Y71.A Tilo 0.235 N299
i_Core/i_SpiMasterWB/_n0817_inv_SW0
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y76.C6 net (fanout=32) 0.627 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y76.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16>
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_16
------------------------------------------------- ---------------------------
Total 7.372ns (1.620ns logic, 5.752ns route)
(22.0% logic, 78.0% route)
Total 7.543ns (2.014ns logic, 5.529ns route)
(26.7% logic, 73.3% route)
--------------------------------------------------------------------------------
Slack (setup path): 1.042ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/VmeBaseAddr_7 (FF)
Destination: i_Core/i_VmeInterface/adr_o_5 (FF)
Slack (setup path): 0.802ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_13 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_16 (FF)
Requirement: 8.333ns
Data Path Delay: 7.281ns (Levels of Logic = 3)
Clock Path Skew: 0.025ns (0.780 - 0.755)
Data Path Delay: 7.588ns (Levels of Logic = 6)
Clock Path Skew: 0.092ns (0.991 - 0.899)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -262,38 +274,45 @@ Slack (setup path): 1.042ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_7 to i_Core/i_VmeInterface/adr_o_5
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_13 to i_Core/i_SpiMasterWB/ShiftIn_qb32_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X126Y125.DQ Tcko 0.476 i_Core/i_VmeInterface/VmeBaseAddr<7>
i_Core/i_VmeInterface/VmeBaseAddr_7
SLICE_X126Y126.A5 net (fanout=1) 0.375 i_Core/i_VmeInterface/VmeBaseAddr<7>
SLICE_X126Y126.A Tilo 0.235 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o86
SLICE_X85Y100.C6 net (fanout=2) 4.055 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
SLICE_X85Y100.C Tilo 0.259 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/selected
SLICE_X85Y100.D5 net (fanout=12) 0.258 i_Core/i_VmeInterface/selected
SLICE_X85Y100.DMUX Tilo 0.337 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/_n0350_inv1
SLICE_X84Y96.CE net (fanout=10) 0.973 i_Core/i_VmeInterface/_n0350_inv
SLICE_X84Y96.CLK Tceck 0.313 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_5
SLICE_X79Y97.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_13
SLICE_X81Y97.B1 net (fanout=4) 0.741 i_Core/i_VmeInterface/adr_o<13>
SLICE_X81Y97.B Tilo 0.259 i_Core/i_VmeInterface/adr_o<10>
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12
SLICE_X81Y97.A6 net (fanout=4) 0.554 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X81Y97.A Tilo 0.259 i_Core/i_VmeInterface/adr_o<10>
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
SLICE_X75Y88.B3 net (fanout=1) 1.560 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X75Y88.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X60Y77.C6 net (fanout=5) 1.716 i_Core/StbSpiMaster
SLICE_X60Y77.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X60Y77.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y76.C6 net (fanout=32) 0.627 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X63Y76.CLK Tas 0.373 i_Core/i_SpiMasterWB/ShiftIn_qb32<16>
i_Core/i_SpiMasterWB/ShiftIn_qb32_16_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_16
------------------------------------------------- ---------------------------
Total 7.281ns (1.620ns logic, 5.661ns route)
(22.2% logic, 77.8% route)
Total 7.588ns (2.089ns logic, 5.499ns route)
(27.5% logic, 72.5% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_VmeInterface/adr_o_14 (SLICE_X84Y96.CE), 15 paths
Paths for end point i_Core/i_SpiMasterWB/ShiftIn_qb32_22 (SLICE_X62Y76.C6), 310 paths
--------------------------------------------------------------------------------
Slack (setup path): 0.932ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/VmeBaseAddr_6 (FF)
Destination: i_Core/i_VmeInterface/adr_o_14 (FF)
Slack (setup path): 0.453ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/Config1_qb32_0 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_22 (FF)
Requirement: 8.333ns
Data Path Delay: 7.389ns (Levels of Logic = 3)
Clock Path Skew: 0.023ns (0.780 - 0.757)
Data Path Delay: 8.001ns (Levels of Logic = 5)
Clock Path Skew: 0.156ns (0.902 - 0.746)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -304,35 +323,40 @@ Slack (setup path): 0.932ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_6 to i_Core/i_VmeInterface/adr_o_14
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/Config1_qb32_0 to i_Core/i_SpiMasterWB/ShiftIn_qb32_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X126Y127.CQ Tcko 0.476 i_Core/i_VmeInterface/VmeBaseAddr<6>
i_Core/i_VmeInterface/VmeBaseAddr_6
SLICE_X126Y126.A6 net (fanout=1) 0.527 i_Core/i_VmeInterface/VmeBaseAddr<6>
SLICE_X126Y126.A Tilo 0.235 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o86
SLICE_X85Y100.C6 net (fanout=2) 4.055 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
SLICE_X85Y100.C Tilo 0.259 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/selected
SLICE_X85Y100.D5 net (fanout=12) 0.258 i_Core/i_VmeInterface/selected
SLICE_X85Y100.DMUX Tilo 0.337 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/_n0350_inv1
SLICE_X84Y96.CE net (fanout=10) 0.973 i_Core/i_VmeInterface/_n0350_inv
SLICE_X84Y96.CLK Tceck 0.269 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_14
SLICE_X69Y74.AQ Tcko 0.430 i_Core/i_SpiMasterWB/Config1_qb32<19>
i_Core/i_SpiMasterWB/Config1_qb32_0
SLICE_X67Y74.A4 net (fanout=2) 1.775 i_Core/i_SpiMasterWB/Config1_qb32<0>
SLICE_X67Y74.A Tilo 0.259 i_Core/i_SpiMasterWB/Config1_qb32<2>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o122
SLICE_X70Y69.C5 net (fanout=3) 1.434 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o121
SLICE_X70Y69.CMUX Topcc 0.441 N261
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261
SLICE_X70Y71.A Tilo 0.235 N299
i_Core/i_SpiMasterWB/_n0817_inv_SW0
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X62Y76.C6 net (fanout=32) 0.640 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X62Y76.CLK Tas 0.349 i_Core/i_SpiMasterWB/ShiftIn_qb32<23>
i_Core/i_SpiMasterWB/ShiftIn_qb32_22_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_22
------------------------------------------------- ---------------------------
Total 7.389ns (1.576ns logic, 5.813ns route)
(21.3% logic, 78.7% route)
Total 8.001ns (1.968ns logic, 6.033ns route)
(24.6% logic, 75.4% route)
--------------------------------------------------------------------------------
Slack (setup path): 0.993ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/VmeBaseAddr_5 (FF)
Destination: i_Core/i_VmeInterface/adr_o_14 (FF)
Slack (setup path): 0.751ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_SpiMasterWB/TxCounter_cb12_5 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_22 (FF)
Requirement: 8.333ns
Data Path Delay: 7.328ns (Levels of Logic = 3)
Clock Path Skew: 0.023ns (0.780 - 0.757)
Data Path Delay: 7.532ns (Levels of Logic = 5)
Clock Path Skew: -0.015ns (0.254 - 0.269)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -343,35 +367,40 @@ Slack (setup path): 0.993ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_5 to i_Core/i_VmeInterface/adr_o_14
Maximum Data Path at Slow Process Corner: i_Core/i_SpiMasterWB/TxCounter_cb12_5 to i_Core/i_SpiMasterWB/ShiftIn_qb32_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X126Y127.BQ Tcko 0.476 i_Core/i_VmeInterface/VmeBaseAddr<6>
i_Core/i_VmeInterface/VmeBaseAddr_5
SLICE_X126Y126.A4 net (fanout=1) 0.466 i_Core/i_VmeInterface/VmeBaseAddr<5>
SLICE_X126Y126.A Tilo 0.235 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o86
SLICE_X85Y100.C6 net (fanout=2) 4.055 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
SLICE_X85Y100.C Tilo 0.259 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/selected
SLICE_X85Y100.D5 net (fanout=12) 0.258 i_Core/i_VmeInterface/selected
SLICE_X85Y100.DMUX Tilo 0.337 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/_n0350_inv1
SLICE_X84Y96.CE net (fanout=10) 0.973 i_Core/i_VmeInterface/_n0350_inv
SLICE_X84Y96.CLK Tceck 0.269 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_14
SLICE_X58Y76.DQ Tcko 0.476 i_Core/i_SpiMasterWB/TxCounter_cb12<5>
i_Core/i_SpiMasterWB/TxCounter_cb12_5
SLICE_X66Y74.B6 net (fanout=3) 1.068 i_Core/i_SpiMasterWB/TxCounter_cb12<5>
SLICE_X66Y74.B Tilo 0.235 i_Core/i_SpiMasterWB/Config1_qb32<6>
i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o124
SLICE_X70Y69.C4 net (fanout=3) 1.650 i_Core/i_SpiMasterWB/TxCounter_cb12[11]_a_RegisterLenght_b12[11]_equal_14_o123
SLICE_X70Y69.CMUX Topcc 0.441 N261
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_lut
i_Core/i_SpiMasterWB/_n0817_inv_SW0_SW0_cy
SLICE_X70Y71.A6 net (fanout=1) 0.526 N261
SLICE_X70Y71.A Tilo 0.235 N299
i_Core/i_SpiMasterWB/_n0817_inv_SW0
SLICE_X60Y77.B2 net (fanout=1) 1.658 N84
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X62Y76.C6 net (fanout=32) 0.640 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X62Y76.CLK Tas 0.349 i_Core/i_SpiMasterWB/ShiftIn_qb32<23>
i_Core/i_SpiMasterWB/ShiftIn_qb32_22_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_22
------------------------------------------------- ---------------------------
Total 7.328ns (1.576ns logic, 5.752ns route)
(21.5% logic, 78.5% route)
Total 7.532ns (1.990ns logic, 5.542ns route)
(26.4% logic, 73.6% route)
--------------------------------------------------------------------------------
Slack (setup path): 1.086ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/VmeBaseAddr_7 (FF)
Destination: i_Core/i_VmeInterface/adr_o_14 (FF)
Slack (setup path): 0.813ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_VmeInterface/adr_o_13 (FF)
Destination: i_Core/i_SpiMasterWB/ShiftIn_qb32_22 (FF)
Requirement: 8.333ns
Data Path Delay: 7.237ns (Levels of Logic = 3)
Clock Path Skew: 0.025ns (0.780 - 0.755)
Data Path Delay: 7.577ns (Levels of Logic = 6)
Clock Path Skew: 0.092ns (0.991 - 0.899)
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -382,111 +411,121 @@ Slack (setup path): 1.086ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/VmeBaseAddr_7 to i_Core/i_VmeInterface/adr_o_14
Maximum Data Path at Slow Process Corner: i_Core/i_VmeInterface/adr_o_13 to i_Core/i_SpiMasterWB/ShiftIn_qb32_22
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X126Y125.DQ Tcko 0.476 i_Core/i_VmeInterface/VmeBaseAddr<7>
i_Core/i_VmeInterface/VmeBaseAddr_7
SLICE_X126Y126.A5 net (fanout=1) 0.375 i_Core/i_VmeInterface/VmeBaseAddr<7>
SLICE_X126Y126.A Tilo 0.235 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o86
SLICE_X85Y100.C6 net (fanout=2) 4.055 i_Core/i_VmeInterface/VmeBaseAddr[7]_GND_36_o_equal_12_o85
SLICE_X85Y100.C Tilo 0.259 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/selected
SLICE_X85Y100.D5 net (fanout=12) 0.258 i_Core/i_VmeInterface/selected
SLICE_X85Y100.DMUX Tilo 0.337 i_Core/i_VmeInterface/as_shr<1>
i_Core/i_VmeInterface/_n0350_inv1
SLICE_X84Y96.CE net (fanout=10) 0.973 i_Core/i_VmeInterface/_n0350_inv
SLICE_X84Y96.CLK Tceck 0.269 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_14
SLICE_X79Y97.BQ Tcko 0.430 i_Core/i_VmeInterface/adr_o<15>
i_Core/i_VmeInterface/adr_o_13
SLICE_X81Y97.B1 net (fanout=4) 0.741 i_Core/i_VmeInterface/adr_o<13>
SLICE_X81Y97.B Tilo 0.259 i_Core/i_VmeInterface/adr_o<10>
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o12
SLICE_X81Y97.A6 net (fanout=4) 0.554 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_1_o11
SLICE_X81Y97.A Tilo 0.259 i_Core/i_VmeInterface/adr_o<10>
i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1_1
SLICE_X75Y88.B3 net (fanout=1) 1.560 i_Core/i_AddressDecoderWB/Adr_ib22[21]_GND_70_o_equal_4_o1
SLICE_X75Y88.B Tilo 0.259 i_Core/i_VmeInterface/ack_d
i_Core/i_AddressDecoderWB/Mmux_StbSpiMaster_o11
SLICE_X60Y77.C6 net (fanout=5) 1.716 i_Core/StbSpiMaster
SLICE_X60Y77.C Tilo 0.255 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0649_inv11_1
SLICE_X60Y77.B4 net (fanout=1) 0.301 i_Core/i_SpiMasterWB/_n0649_inv11
SLICE_X60Y77.B Tilo 0.254 i_Core/i_SpiMasterWB/ShiftIn_qb32<31>
i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X62Y76.C6 net (fanout=32) 0.640 i_Core/i_SpiMasterWB/_n0817_inv
SLICE_X62Y76.CLK Tas 0.349 i_Core/i_SpiMasterWB/ShiftIn_qb32<23>
i_Core/i_SpiMasterWB/ShiftIn_qb32_22_rstpot
i_Core/i_SpiMasterWB/ShiftIn_qb32_22
------------------------------------------------- ---------------------------
Total 7.237ns (1.576ns logic, 5.661ns route)
(21.8% logic, 78.2% route)
Total 7.577ns (2.065ns logic, 5.512ns route)
(27.3% logic, 72.7% route)
--------------------------------------------------------------------------------
Hold Paths: TS_Si57x_ik = PERIOD TIMEGRP "Si57x_ik" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMA (SLICE_X76Y88.D2), 1 path
Paths for end point i_Core/i_VmeInterface/dat_o_15 (SLICE_X82Y96.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.347ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_InterruptManager/int_pointer_w_1 (FF)
Destination: i_Core/i_InterruptManager/Mram_int_fifo1_RAMA (RAM)
Slack (hold path): 0.413ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_VmeInterface/dat_o_15 (FF)
Destination: i_Core/i_VmeInterface/dat_o_15 (FF)
Requirement: 0.000ns
Data Path Delay: 0.352ns (Levels of Logic = 0)
Clock Path Skew: 0.005ns (0.068 - 0.063)
Data Path Delay: 0.413ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_1 to i_Core/i_InterruptManager/Mram_int_fifo1_RAMA
Minimum Data Path at Fast Process Corner: i_Core/i_VmeInterface/dat_o_15 to i_Core/i_VmeInterface/dat_o_15
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y88.BMUX Tshcko 0.238 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_InterruptManager/int_pointer_w_1
SLICE_X76Y88.D2 net (fanout=8) 0.409 i_Core/i_InterruptManager/int_pointer_w<1>
SLICE_X76Y88.CLK Tah (-Th) 0.295 i_Core/i_InterruptManager/_n0165<5>
i_Core/i_InterruptManager/Mram_int_fifo1_RAMA
SLICE_X82Y96.DQ Tcko 0.200 i_Core/i_VmeInterface/dat_o<15>
i_Core/i_VmeInterface/dat_o_15
SLICE_X82Y96.D6 net (fanout=8) 0.023 i_Core/i_VmeInterface/dat_o<15>
SLICE_X82Y96.CLK Tah (-Th) -0.190 i_Core/i_VmeInterface/dat_o<15>
i_Core/i_VmeInterface/dat_o_15_dpot
i_Core/i_VmeInterface/dat_o_15
------------------------------------------------- ---------------------------
Total 0.352ns (-0.057ns logic, 0.409ns route)
(-16.2% logic, 116.2% route)
Total 0.413ns (0.390ns logic, 0.023ns route)
(94.4% logic, 5.6% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1 (SLICE_X76Y88.D2), 1 path
Paths for end point i_Core/i_VmeInterface/dat_o_19 (SLICE_X82Y92.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.347ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_InterruptManager/int_pointer_w_1 (FF)
Destination: i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1 (RAM)
Slack (hold path): 0.416ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_VmeInterface/dat_o_19 (FF)
Destination: i_Core/i_VmeInterface/dat_o_19 (FF)
Requirement: 0.000ns
Data Path Delay: 0.352ns (Levels of Logic = 0)
Clock Path Skew: 0.005ns (0.068 - 0.063)
Data Path Delay: 0.416ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_1 to i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1
Minimum Data Path at Fast Process Corner: i_Core/i_VmeInterface/dat_o_19 to i_Core/i_VmeInterface/dat_o_19
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y88.BMUX Tshcko 0.238 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_InterruptManager/int_pointer_w_1
SLICE_X76Y88.D2 net (fanout=8) 0.409 i_Core/i_InterruptManager/int_pointer_w<1>
SLICE_X76Y88.CLK Tah (-Th) 0.295 i_Core/i_InterruptManager/_n0165<5>
i_Core/i_InterruptManager/Mram_int_fifo1_RAMA_D1
SLICE_X82Y92.DQ Tcko 0.200 i_Core/i_VmeInterface/dat_o<19>
i_Core/i_VmeInterface/dat_o_19
SLICE_X82Y92.D6 net (fanout=8) 0.026 i_Core/i_VmeInterface/dat_o<19>
SLICE_X82Y92.CLK Tah (-Th) -0.190 i_Core/i_VmeInterface/dat_o<19>
i_Core/i_VmeInterface/dat_o_19_dpot
i_Core/i_VmeInterface/dat_o_19
------------------------------------------------- ---------------------------
Total 0.352ns (-0.057ns logic, 0.409ns route)
(-16.2% logic, 116.2% route)
Total 0.416ns (0.390ns logic, 0.026ns route)
(93.8% logic, 6.3% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_InterruptManager/Mram_int_fifo1_RAMB (SLICE_X76Y88.D2), 1 path
Paths for end point i_Core/i_VmeInterface/VmeDOe_o (SLICE_X70Y98.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.347ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_InterruptManager/int_pointer_w_1 (FF)
Destination: i_Core/i_InterruptManager/Mram_int_fifo1_RAMB (RAM)
Slack (hold path): 0.417ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_VmeInterface/VmeDOe_o (FF)
Destination: i_Core/i_VmeInterface/VmeDOe_o (FF)
Requirement: 0.000ns
Data Path Delay: 0.352ns (Levels of Logic = 0)
Clock Path Skew: 0.005ns (0.068 - 0.063)
Data Path Delay: 0.417ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: Si57x_BUFG rising at 0.000ns
Destination Clock: Si57x_BUFG rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_InterruptManager/int_pointer_w_1 to i_Core/i_InterruptManager/Mram_int_fifo1_RAMB
Minimum Data Path at Fast Process Corner: i_Core/i_VmeInterface/VmeDOe_o to i_Core/i_VmeInterface/VmeDOe_o
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y88.BMUX Tshcko 0.238 i_Core/i_InterruptManager/int_pointer_w<2>
i_Core/i_InterruptManager/int_pointer_w_1
SLICE_X76Y88.D2 net (fanout=8) 0.409 i_Core/i_InterruptManager/int_pointer_w<1>
SLICE_X76Y88.CLK Tah (-Th) 0.295 i_Core/i_InterruptManager/_n0165<5>
i_Core/i_InterruptManager/Mram_int_fifo1_RAMB
SLICE_X70Y98.AQ Tcko 0.200 i_Core/i_VmeInterface/VmeDOe_o
i_Core/i_VmeInterface/VmeDOe_o
SLICE_X70Y98.A6 net (fanout=2) 0.027 i_Core/i_VmeInterface/VmeDOe_o
SLICE_X70Y98.CLK Tah (-Th) -0.190 i_Core/i_VmeInterface/VmeDOe_o
i_Core/i_VmeInterface/Mmux__n031611
i_Core/i_VmeInterface/VmeDOe_o
------------------------------------------------- ---------------------------
Total 0.352ns (-0.057ns logic, 0.409ns route)
(-16.2% logic, 116.2% route)
Total 0.417ns (0.390ns logic, 0.027ns route)
(93.5% logic, 6.5% route)
--------------------------------------------------------------------------------
......@@ -505,7 +544,7 @@ Slack: 6.934ns (period - min period limit)
Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/i_Debouncer/BouncingSignal_x<2>/CLK
Logical resource: i_Core/i_Debouncer/Mshreg_BouncingSignal_x_2/CLK
Location pin: SLICE_X26Y34.CLK
Location pin: SLICE_X26Y36.CLK
Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
Slack: 6.934ns (period - min period limit)
......@@ -513,7 +552,7 @@ Slack: 6.934ns (period - min period limit)
Min period limit: 1.399ns (714.796MHz) (Tcp)
Physical resource: i_Core/VmeSysReset_dx<1>/CLK
Logical resource: i_Core/i_Slv2SerWB/Mshreg_AckI_xb3_0/CLK
Location pin: SLICE_X68Y102.CLK
Location pin: SLICE_X72Y109.CLK
Clock network: Si57x_BUFG
--------------------------------------------------------------------------------
......@@ -523,17 +562,17 @@ Timing constraint: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH
129 paths analyzed, 97 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 2.874ns.
Minimum period is 3.869ns.
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_28 (SLICE_X68Y90.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_28 (SLICE_X66Y91.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 5.459ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 4.464ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_28 (FF)
Requirement: 8.333ns
Data Path Delay: 2.819ns (Levels of Logic = 1)
Clock Path Skew: -0.020ns (0.249 - 0.269)
Data Path Delay: 3.807ns (Levels of Logic = 1)
Clock Path Skew: -0.027ns (1.040 - 1.067)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -548,25 +587,25 @@ Slack (setup path): 5.459ns (requirement - (data path - clock path skew + un
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X70Y93.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X42Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X73Y93.A3 net (fanout=1) 0.559 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X73Y93.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X54Y99.A3 net (fanout=1) 1.189 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X68Y90.CE net (fanout=6) 1.212 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y90.CLK Tceck 0.313 i_Core/i_Slv2SerWB/Dat_xb32<31>
SLICE_X66Y91.CE net (fanout=7) 1.593 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X66Y91.CLK Tceck 0.314 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_28
------------------------------------------------- ---------------------------
Total 2.819ns (1.048ns logic, 1.771ns route)
(37.2% logic, 62.8% route)
Total 3.807ns (1.025ns logic, 2.782ns route)
(26.9% logic, 73.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 5.514ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 4.521ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_28 (FF)
Requirement: 8.333ns
Data Path Delay: 2.764ns (Levels of Logic = 1)
Clock Path Skew: -0.020ns (0.249 - 0.269)
Data Path Delay: 3.750ns (Levels of Logic = 1)
Clock Path Skew: -0.027ns (1.040 - 1.067)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -581,28 +620,28 @@ Slack (setup path): 5.514ns (requirement - (data path - clock path skew + un
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X70Y93.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X42Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X73Y93.A4 net (fanout=2) 0.504 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X73Y93.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X54Y99.A4 net (fanout=2) 1.132 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X68Y90.CE net (fanout=6) 1.212 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y90.CLK Tceck 0.313 i_Core/i_Slv2SerWB/Dat_xb32<31>
SLICE_X66Y91.CE net (fanout=7) 1.593 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X66Y91.CLK Tceck 0.314 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_28
------------------------------------------------- ---------------------------
Total 2.764ns (1.048ns logic, 1.716ns route)
(37.9% logic, 62.1% route)
Total 3.750ns (1.025ns logic, 2.725ns route)
(27.3% logic, 72.7% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_30 (SLICE_X68Y90.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_16 (SLICE_X68Y101.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 5.503ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 4.473ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_30 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_16 (FF)
Requirement: 8.333ns
Data Path Delay: 2.775ns (Levels of Logic = 1)
Clock Path Skew: -0.020ns (0.249 - 0.269)
Data Path Delay: 3.622ns (Levels of Logic = 1)
Clock Path Skew: -0.203ns (0.770 - 0.973)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -613,29 +652,29 @@ Slack (setup path): 5.503ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_30
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_2 to i_Core/i_Slv2SerWB/Dat_xb32_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X70Y93.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X42Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X73Y93.A3 net (fanout=1) 0.559 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X73Y93.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X54Y99.A3 net (fanout=1) 1.189 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X68Y90.CE net (fanout=6) 1.212 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y90.CLK Tceck 0.269 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_30
SLICE_X68Y101.CE net (fanout=7) 1.409 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y101.CLK Tceck 0.313 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_16
------------------------------------------------- ---------------------------
Total 2.775ns (1.004ns logic, 1.771ns route)
(36.2% logic, 63.8% route)
Total 3.622ns (1.024ns logic, 2.598ns route)
(28.3% logic, 71.7% route)
--------------------------------------------------------------------------------
Slack (setup path): 5.558ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 4.530ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_30 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_16 (FF)
Requirement: 8.333ns
Data Path Delay: 2.720ns (Levels of Logic = 1)
Clock Path Skew: -0.020ns (0.249 - 0.269)
Data Path Delay: 3.565ns (Levels of Logic = 1)
Clock Path Skew: -0.203ns (0.770 - 0.973)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -646,32 +685,32 @@ Slack (setup path): 5.558ns (requirement - (data path - clock path skew + un
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_30
Maximum Data Path at Slow Process Corner: i_Core/i_Slv2SerWB/AckI_d3_1 to i_Core/i_Slv2SerWB/Dat_xb32_16
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X70Y93.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X42Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X73Y93.A4 net (fanout=2) 0.504 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X73Y93.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X54Y99.A4 net (fanout=2) 1.132 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X68Y90.CE net (fanout=6) 1.212 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y90.CLK Tceck 0.269 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_30
SLICE_X68Y101.CE net (fanout=7) 1.409 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y101.CLK Tceck 0.313 i_Core/i_Slv2SerWB/Dat_xb32<19>
i_Core/i_Slv2SerWB/Dat_xb32_16
------------------------------------------------- ---------------------------
Total 2.720ns (1.004ns logic, 1.716ns route)
(36.9% logic, 63.1% route)
Total 3.565ns (1.024ns logic, 2.541ns route)
(28.7% logic, 71.3% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_31 (SLICE_X68Y90.CE), 2 paths
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_31 (SLICE_X66Y91.CE), 2 paths
--------------------------------------------------------------------------------
Slack (setup path): 5.506ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 4.487ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_2 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_31 (FF)
Requirement: 8.333ns
Data Path Delay: 2.772ns (Levels of Logic = 1)
Clock Path Skew: -0.020ns (0.249 - 0.269)
Data Path Delay: 3.784ns (Levels of Logic = 1)
Clock Path Skew: -0.027ns (1.040 - 1.067)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -686,25 +725,25 @@ Slack (setup path): 5.506ns (requirement - (data path - clock path skew + un
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X70Y93.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X42Y101.CQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_2
SLICE_X73Y93.A3 net (fanout=1) 0.559 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X73Y93.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X54Y99.A3 net (fanout=1) 1.189 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X68Y90.CE net (fanout=6) 1.212 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y90.CLK Tceck 0.266 i_Core/i_Slv2SerWB/Dat_xb32<31>
SLICE_X66Y91.CE net (fanout=7) 1.593 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X66Y91.CLK Tceck 0.291 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_31
------------------------------------------------- ---------------------------
Total 2.772ns (1.001ns logic, 1.771ns route)
(36.1% logic, 63.9% route)
Total 3.784ns (1.002ns logic, 2.782ns route)
(26.5% logic, 73.5% route)
--------------------------------------------------------------------------------
Slack (setup path): 5.561ns (requirement - (data path - clock path skew + uncertainty))
Slack (setup path): 4.544ns (requirement - (data path - clock path skew + uncertainty))
Source: i_Core/i_Slv2SerWB/AckI_d3_1 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_31 (FF)
Requirement: 8.333ns
Data Path Delay: 2.717ns (Levels of Logic = 1)
Clock Path Skew: -0.020ns (0.249 - 0.269)
Data Path Delay: 3.727ns (Levels of Logic = 1)
Clock Path Skew: -0.027ns (1.040 - 1.067)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.035ns
......@@ -719,101 +758,101 @@ Slack (setup path): 5.561ns (requirement - (data path - clock path skew + un
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X70Y93.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
SLICE_X42Y101.BQ Tcko 0.476 i_Core/i_Slv2SerWB/AckI_d3<2>
i_Core/i_Slv2SerWB/AckI_d3_1
SLICE_X73Y93.A4 net (fanout=2) 0.504 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X73Y93.A Tilo 0.259 i_Core/i_Slv2SerWB/Dat_xb32<3>
SLICE_X54Y99.A4 net (fanout=2) 1.132 i_Core/i_Slv2SerWB/AckI_d3<1>
SLICE_X54Y99.A Tilo 0.235 i_Core/i_Slv2SerWB/Dat_xb32<3>
i_Core/i_Slv2SerWB/NewAckI_a<2>1
SLICE_X68Y90.CE net (fanout=6) 1.212 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X68Y90.CLK Tceck 0.266 i_Core/i_Slv2SerWB/Dat_xb32<31>
SLICE_X66Y91.CE net (fanout=7) 1.593 i_Core/i_Slv2SerWB/NewAckI_a
SLICE_X66Y91.CLK Tceck 0.291 i_Core/i_Slv2SerWB/Dat_xb32<31>
i_Core/i_Slv2SerWB/Dat_xb32_31
------------------------------------------------- ---------------------------
Total 2.717ns (1.001ns logic, 1.716ns route)
(36.8% logic, 63.2% route)
Total 3.727ns (1.002ns logic, 2.725ns route)
(26.9% logic, 73.1% route)
--------------------------------------------------------------------------------
Hold Paths: TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/DatInShReg_b32_19 (SLICE_X72Y95.DX), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_14 (SLICE_X66Y101.CX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.459ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_20 (FF)
Destination: i_Core/i_Slv2SerWB/DatInShReg_b32_19 (FF)
Slack (hold path): 0.442ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_14 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_14 (FF)
Requirement: 0.000ns
Data Path Delay: 0.462ns (Levels of Logic = 0)
Clock Path Skew: 0.003ns (0.045 - 0.042)
Data Path Delay: 0.442ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_20 to i_Core/i_Slv2SerWB/DatInShReg_b32_19
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_14 to i_Core/i_Slv2SerWB/Dat_xb32_14
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X73Y94.AQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<23>
i_Core/i_Slv2SerWB/DatInShReg_b32_20
SLICE_X72Y95.DX net (fanout=2) 0.223 i_Core/i_Slv2SerWB/DatInShReg_b32<20>
SLICE_X72Y95.CLK Tckdi (-Th) -0.041 i_Core/i_Slv2SerWB/DatInShReg_b32<19>
i_Core/i_Slv2SerWB/DatInShReg_b32_19
SLICE_X66Y100.CQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<15>
i_Core/i_Slv2SerWB/DatInShReg_b32_14
SLICE_X66Y101.CX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<14>
SLICE_X66Y101.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<15>
i_Core/i_Slv2SerWB/Dat_xb32_14
------------------------------------------------- ---------------------------
Total 0.462ns (0.239ns logic, 0.223ns route)
(51.7% logic, 48.3% route)
Total 0.442ns (0.248ns logic, 0.194ns route)
(56.1% logic, 43.9% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/DatInShReg_b32_11 (SLICE_X76Y94.DX), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_15 (SLICE_X66Y101.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.468ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_12 (FF)
Destination: i_Core/i_Slv2SerWB/DatInShReg_b32_11 (FF)
Slack (hold path): 0.442ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_15 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_15 (FF)
Requirement: 0.000ns
Data Path Delay: 0.472ns (Levels of Logic = 0)
Clock Path Skew: 0.004ns (0.078 - 0.074)
Data Path Delay: 0.442ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_12 to i_Core/i_Slv2SerWB/DatInShReg_b32_11
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_15 to i_Core/i_Slv2SerWB/Dat_xb32_15
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y94.AQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<15>
i_Core/i_Slv2SerWB/DatInShReg_b32_12
SLICE_X76Y94.DX net (fanout=2) 0.231 i_Core/i_Slv2SerWB/DatInShReg_b32<12>
SLICE_X76Y94.CLK Tckdi (-Th) -0.041 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_11
SLICE_X66Y100.DQ Tcko 0.200 i_Core/i_Slv2SerWB/DatInShReg_b32<15>
i_Core/i_Slv2SerWB/DatInShReg_b32_15
SLICE_X66Y101.DX net (fanout=2) 0.194 i_Core/i_Slv2SerWB/DatInShReg_b32<15>
SLICE_X66Y101.CLK Tckdi (-Th) -0.048 i_Core/i_Slv2SerWB/Dat_xb32<15>
i_Core/i_Slv2SerWB/Dat_xb32_15
------------------------------------------------- ---------------------------
Total 0.472ns (0.241ns logic, 0.231ns route)
(51.1% logic, 48.9% route)
Total 0.442ns (0.248ns logic, 0.194ns route)
(56.1% logic, 43.9% route)
--------------------------------------------------------------------------------
Paths for end point i_Core/i_Slv2SerWB/DatInShReg_b32_27 (SLICE_X69Y91.DX), 1 path
Paths for end point i_Core/i_Slv2SerWB/Dat_xb32_8 (SLICE_X61Y99.AX), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.470ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_28 (FF)
Destination: i_Core/i_Slv2SerWB/DatInShReg_b32_27 (FF)
Slack (hold path): 0.451ns (requirement - (clock path skew + uncertainty - data path))
Source: i_Core/i_Slv2SerWB/DatInShReg_b32_8 (FF)
Destination: i_Core/i_Slv2SerWB/Dat_xb32_8 (FF)
Requirement: 0.000ns
Data Path Delay: 0.474ns (Levels of Logic = 0)
Clock Path Skew: 0.004ns (0.039 - 0.035)
Data Path Delay: 0.455ns (Levels of Logic = 0)
Clock Path Skew: 0.004ns (0.040 - 0.036)
Source Clock: SysAppClk_ik_BUFGP rising at 0.000ns
Destination Clock: SysAppClk_ik_BUFGP rising at 8.333ns
Clock Uncertainty: 0.000ns
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_28 to i_Core/i_Slv2SerWB/DatInShReg_b32_27
Minimum Data Path at Fast Process Corner: i_Core/i_Slv2SerWB/DatInShReg_b32_8 to i_Core/i_Slv2SerWB/Dat_xb32_8
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X69Y90.AQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<31>
i_Core/i_Slv2SerWB/DatInShReg_b32_28
SLICE_X69Y91.DX net (fanout=2) 0.217 i_Core/i_Slv2SerWB/DatInShReg_b32<28>
SLICE_X69Y91.CLK Tckdi (-Th) -0.059 i_Core/i_Slv2SerWB/DatInShReg_b32<27>
i_Core/i_Slv2SerWB/DatInShReg_b32_27
SLICE_X61Y100.AQ Tcko 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<11>
i_Core/i_Slv2SerWB/DatInShReg_b32_8
SLICE_X61Y99.AX net (fanout=2) 0.198 i_Core/i_Slv2SerWB/DatInShReg_b32<8>
SLICE_X61Y99.CLK Tckdi (-Th) -0.059 i_Core/i_Slv2SerWB/Dat_xb32<11>
i_Core/i_Slv2SerWB/Dat_xb32_8
------------------------------------------------- ---------------------------
Total 0.474ns (0.257ns logic, 0.217ns route)
(54.2% logic, 45.8% route)
Total 0.455ns (0.257ns logic, 0.198ns route)
(56.5% logic, 43.5% route)
--------------------------------------------------------------------------------
......@@ -830,17 +869,17 @@ Slack: 5.833ns (period - min period limit)
Slack: 7.853ns (period - min period limit)
Period: 8.333ns
Min period limit: 0.480ns (2083.333MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/Dat_xb32<31>/CLK
Logical resource: i_Core/i_Slv2SerWB/Dat_xb32_28/CK
Location pin: SLICE_X68Y90.CLK
Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<23>/CLK
Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_20/CK
Location pin: SLICE_X68Y99.CLK
Clock network: SysAppClk_ik_BUFGP
--------------------------------------------------------------------------------
Slack: 7.853ns (period - min period limit)
Period: 8.333ns
Min period limit: 0.480ns (2083.333MHz) (Tcp)
Physical resource: i_Core/i_Slv2SerWB/Dat_xb32<31>/CLK
Logical resource: i_Core/i_Slv2SerWB/Dat_xb32_29/CK
Location pin: SLICE_X68Y90.CLK
Physical resource: i_Core/i_Slv2SerWB/DatInShReg_b32<23>/CLK
Logical resource: i_Core/i_Slv2SerWB/DatInShReg_b32_21/CK
Location pin: SLICE_X68Y99.CLK
Clock network: SysAppClk_ik_BUFGP
--------------------------------------------------------------------------------
......@@ -857,8 +896,8 @@ Clock to Setup on destination clock Si57x_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 7.934| | | |
Si57x_ikn | 7.934| | | |
Si57x_ik | 7.898| | | |
Si57x_ikn | 7.898| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock Si57x_ikn
......@@ -866,8 +905,8 @@ Clock to Setup on destination clock Si57x_ikn
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Si57x_ik | 7.934| | | |
Si57x_ikn | 7.934| | | |
Si57x_ik | 7.898| | | |
Si57x_ikn | 7.898| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock SysAppClk_ik
......@@ -875,7 +914,7 @@ Clock to Setup on destination clock SysAppClk_ik
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
SysAppClk_ik | 2.874| | | |
SysAppClk_ik | 3.869| | | |
---------------+---------+---------+---------+---------+
......@@ -884,23 +923,23 @@ Timing summary:
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 44854 paths, 0 nets, and 4258 connections
Constraints cover 44854 paths, 0 nets, and 4274 connections
Design statistics:
Minimum period: 7.934ns{1} (Maximum frequency: 126.040MHz)
Minimum period: 7.898ns{1} (Maximum frequency: 126.614MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Fri Dec 17 10:03:01 2010
Analysis completed Fri Dec 17 11:13:07 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 273 MB
Peak Memory Usage: 389 MB
trunk/firmware/XilinxISE/SystemFpga/SFpga.twx
View file @ c3d17ad2
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga.unroutes
View file @ c3d17ad2
Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 10:02:34 2010
Fri Dec 17 11:12:54 2010
All signals are completely routed.
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_envsettings.html
View file @ c3d17ad2
......@@ -15,17 +15,17 @@
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.PSC1;<br>.PSC1</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt;<br>C:\WINNT\system32;<br>C:\WINNT;<br>C:\WINNT\System32\Wbem;<br>C:\Cadence\Psd\tools\bin;<br>c:\cadence\psd\tools\jre\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>c:\altera\90\quartus\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\WINNT\system32\WindowsPowerShell\v1.0;<br>C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Modeltech_6.3d\win32</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\bin\nt64;<br>C:\Xilinx\12.3\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\</td>
</tr>
<tr>
<td>XILINX</td>
......@@ -35,13 +35,6 @@
<td>C:\Xilinx\12.3\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
<td>C:\Xilinx\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
<td>C:\Xilinx\12.3\ISE_DS\ISE</td>
......@@ -515,31 +508,31 @@
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td> Intel(R) Pentium(R) D CPU 3.40GHz/3389 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
<td>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz/3158 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>bqplv2</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
<td>PCBE13225</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft Windows XP Professional</td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
<td>Microsoft </td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>Service Pack 3 (build 2600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
<td>major release (build 7600)</td>
</tr>
</TABLE>
</BODY> </HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_guide.ncd
View file @ c3d17ad2
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.map
View file @ c3d17ad2
Release 12.3 Map M.70d (nt)
Release 12.3 Map M.70d (nt64)
Xilinx Map Application Log File for Design 'SFpga'
Design Information
......@@ -10,7 +10,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 09:59:57 2010
Mapped Date : Fri Dec 17 11:11:25 2010
Mapping design into LUTs...
WARNING:MapLib:701 - Signal PllFmc12SFpga_ik connected to top level port
......@@ -79,8 +79,6 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed.
WARNING:MapLib:701 - Signal Si57xOe_o connected to top level port Si57xOe_o has
been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
......@@ -91,20 +89,20 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 26 secs
Total CPU time at the beginning of Placer: 26 secs
Total REAL time at the beginning of Placer: 16 secs
Total CPU time at the beginning of Placer: 12 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 1.1 Initial Placement Analysis (Checksum:fbd9bf1c) REAL time: 21 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 329 IOs, 327 are locked
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 2.7 Design Feasibility Check (Checksum:fbd9bf1c) REAL time: 22 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:f1e9a8bb) REAL time: 34 secs
Phase 3.31 Local Placement Optimization (Checksum:fbd9bf1c) REAL time: 22 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
......@@ -122,42 +120,42 @@ WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:2c046bcb) REAL time: 47 secs
(Checksum:b9a90c54) REAL time: 29 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:2c046bcb) REAL time: 47 secs
Phase 5.36 Local Placement Optimization (Checksum:b9a90c54) REAL time: 29 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:2c046bcb) REAL time: 47 secs
Phase 6.30 Global Clock Region Assignment (Checksum:b9a90c54) REAL time: 29 secs
Phase 7.3 Local Placement Optimization
...
Phase 7.3 Local Placement Optimization (Checksum:e20e3683) REAL time: 48 secs
Phase 7.3 Local Placement Optimization (Checksum:5a4374ed) REAL time: 30 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:2c14b62b) REAL time: 49 secs
Phase 8.5 Local Placement Optimization (Checksum:b9b9c566) REAL time: 30 secs
Phase 9.8 Global Placement
.............
................
...
.......................
.....
Phase 9.8 Global Placement (Checksum:ae7774fb) REAL time: 1 mins
................
......
Phase 9.8 Global Placement (Checksum:94595592) REAL time: 36 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:ae7774fb) REAL time: 1 mins 1 secs
Phase 10.5 Local Placement Optimization (Checksum:94595592) REAL time: 36 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:fe895bce) REAL time: 1 mins 14 secs
Phase 11.18 Placement Optimization (Checksum:df505277) REAL time: 47 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:fe895bce) REAL time: 1 mins 14 secs
Phase 12.5 Local Placement Optimization (Checksum:df505277) REAL time: 47 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:b38174ec) REAL time: 1 mins 14 secs
Phase 13.34 Placement Validation (Checksum:967c17e4) REAL time: 47 secs
Total REAL time to Placer completion: 1 mins 23 secs
Total CPU time to Placer completion: 1 mins 22 secs
Total REAL time to Placer completion: 52 secs
Total CPU time to Placer completion: 47 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
......@@ -261,18 +259,18 @@ Design Summary
Design Summary:
Number of errors: 0
Number of warnings: 84
Number of warnings: 83
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 587
Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number using O5 and O6: 158
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -284,17 +282,17 @@ Slice Logic Utilization:
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 31
Number with same-slice register load: 22
Number used exclusively as route-thrus: 32
Number with same-slice register load: 23
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of unique control sets: 32
Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1%
......@@ -306,8 +304,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99%
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2
IOB Slave Pads: 2
......@@ -338,11 +336,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.03
Average Fanout of Non-Clock Nets: 3.02
Peak Memory Usage: 406 MB
Total REAL time to MAP completion: 1 mins 26 secs
Total CPU time to MAP completion: 1 mins 25 secs
Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 54 secs
Total CPU time to MAP completion: 49 secs
Mapping completed.
See MAP report file "SFpga_map.mrp" for details.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.mrp
View file @ c3d17ad2
Release 12.3 Map M.70d (nt)
Release 12.3 Map M.70d (nt64)
Xilinx Mapping Report File for Design 'SFpga'
Design Information
......@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Fri Dec 17 09:59:57 2010
Mapped Date : Fri Dec 17 11:11:25 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 84
Number of warnings: 83
Slice Logic Utilization:
Number of Slice Registers: 796 out of 184,304 1%
Number used as Flip Flops: 796
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 941 out of 92,152 1%
Number used as logic: 899 out of 92,152 1%
Number using O6 output only: 587
Number of Slice LUTs: 934 out of 92,152 1%
Number used as logic: 891 out of 92,152 1%
Number using O6 output only: 571
Number using O5 output only: 154
Number using O5 and O6: 158
Number using O5 and O6: 166
Number used as ROM: 0
Number used as Memory: 11 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -38,17 +38,17 @@ Slice Logic Utilization:
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 31
Number with same-slice register load: 22
Number used exclusively as route-thrus: 32
Number with same-slice register load: 23
Number with same-slice carry load: 9
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 363 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,084
Number with an unused Flip Flop: 369 out of 1,084 34%
Number with an unused LUT: 143 out of 1,084 13%
Number of fully used LUT-FF pairs: 572 out of 1,084 52%
Number of occupied Slices: 374 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,101
Number with an unused Flip Flop: 386 out of 1,101 35%
Number with an unused LUT: 167 out of 1,101 15%
Number of fully used LUT-FF pairs: 548 out of 1,101 49%
Number of unique control sets: 32
Number of slice register sites lost
to control set restrictions: 85 out of 184,304 1%
......@@ -60,8 +60,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 329 out of 396 83%
Number of LOCed IOBs: 327 out of 329 99%
Number of bonded IOBs: 330 out of 396 83%
Number of LOCed IOBs: 328 out of 330 99%
IOB Master Pads: 2
IOB Slave Pads: 2
......@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.03
Average Fanout of Non-Clock Nets: 3.02
Peak Memory Usage: 406 MB
Total REAL time to MAP completion: 1 mins 26 secs
Total CPU time to MAP completion: 1 mins 25 secs
Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 54 secs
Total CPU time to MAP completion: 49 secs
Table of Contents
-----------------
......@@ -185,8 +185,6 @@ WARNING:MapLib:701 - Signal Fmc1SDa_io connected to top level port Fmc1SDa_io
has been removed.
WARNING:MapLib:701 - Signal Fmc2SDa_io connected to top level port Fmc2SDa_io
has been removed.
WARNING:MapLib:701 - Signal Si57xOe_o connected to top level port Si57xOe_o has
been removed.
WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
......@@ -320,16 +318,16 @@ INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 329 IOs, 327 are locked
INFO:Place:834 - Only a subset of IOs are locked. Out of 330 IOs, 328 are locked
and 2 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
69 block(s) removed
67 block(s) removed
2 block(s) optimized away
38 signal(s) removed
37 signal(s) removed
Section 5 - Removed Logic
-------------------------
......@@ -411,8 +409,6 @@ The signal "DdrDQ_iob16<0>" is unused and has been removed.
Unused block "DdrDQ_iob16_0_OBUFT" (TRI) removed.
The signal "Si57xSDa_io" is unused and has been removed.
Unused block "Si57xSDa_io_OBUFT" (TRI) removed.
The signal "Si57xOe_o" is unused and has been removed.
Unused block "Si57xOe_o_OBUFT" (TRI) removed.
The signal "AFpgaProgDone_io" is unused and has been removed.
Unused block "AFpgaProgDone_io_OBUFT" (TRI) removed.
The signal "AFpgaProgProgram_o" is unused and has been removed.
......@@ -451,7 +447,6 @@ Unused block "DdsIOUpdate_io" (PAD) removed.
Unused block "Fmc1SDa_io" (PAD) removed.
Unused block "Fmc2SDa_io" (PAD) removed.
Unused block "Sfp2ModeDef2_io" (PAD) removed.
Unused block "Si57xOe_o" (PAD) removed.
Unused block "Si57xSDa_io" (PAD) removed.
Unused block "VAdjInhibit_ozn" (PAD) removed.
Unused block "WRModeDef2_io" (PAD) removed.
......@@ -657,6 +652,7 @@ Section 6 - IOB Properties
| Sfp2RateSelect | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2TxDisable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Sfp2TxFault_i | IOB | INPUT | LVCMOS33 | | | | | | |
| Si57xOe_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Si57xSCl_ok | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| Si57x_ik | IOB | INPUT | LVDS_33 | TRUE | | | | | |
| Si57x_ikn | IOB | INPUT | LVDS_33 | TRUE | | | | | |
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ncd
View file @ c3d17ad2
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.ngm
View file @ c3d17ad2
This source diff could not be displayed because it is too large. You can view the blob instead.
trunk/firmware/XilinxISE/SystemFpga/SFpga_map.xrpt
View file @ c3d17ad2
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Fri Dec 17 10:01:24 2010">
<application stringID="Map" timeStamp="Fri Dec 17 11:12:20 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -74,10 +70,10 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="919">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="911">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="154"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="587"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="158"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="571"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="166"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
......@@ -97,7 +93,7 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="396" dataType="int" stringID="MAP_AGG_BONDED_IO" value="329"/>
<item AVAILABLE="396" dataType="int" stringID="MAP_AGG_BONDED_IO" value="330"/>
<item AVAILABLE="180" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
......@@ -119,10 +115,10 @@
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="84"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="415420"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="1 mins 26 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="1 mins 25 secs "/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="83"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="644084"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="54 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="49 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="184304" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="796">
......@@ -131,10 +127,10 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="941">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="934">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="154"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="587"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="158"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="571"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="166"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
......@@ -148,25 +144,25 @@
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="3"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="22"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="23"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="22"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="23"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="9"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="363">
<item AVAILABLE="23038" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="374">
<item AVAILABLE="6099" dataType="int" stringID="MAP_NUM_SLICEL" value="70"/>
<item AVAILABLE="5420" dataType="int" stringID="MAP_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="289"/>
<item AVAILABLE="11519" dataType="int" stringID="MAP_NUM_SLICEX" value="300"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1084">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="369"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="143"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="572"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="1101">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="386"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="167"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="548"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
<item AVAILABLE="396" dataType="int" stringID="MAP_AGG_BONDED_IO" value="329"/>
<item AVAILABLE="396" dataType="int" stringID="MAP_AGG_BONDED_IO" value="330"/>
<item AVAILABLE="180" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
......@@ -1508,7 +1504,7 @@
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="185">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Si57xSCl_ok"/>
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Si57xOe_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
......@@ -1516,38 +1512,46 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="186">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Si57xSCl_ok"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="187">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Si57x_ik"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVDS_33"/>
<item label="Diff&#xA;Term" stringID="DIFF_TERM" value="TRUE"/>
</row>
<row stringID="row" value="187">
<row stringID="row" value="188">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Si57x_ikn"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVDS_33"/>
<item label="Diff&#xA;Term" stringID="DIFF_TERM" value="TRUE"/>
</row>
<row stringID="row" value="188">
<row stringID="row" value="189">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Switch_ib2&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="189">
<row stringID="row" value="190">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Switch_ib2&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="190">
<row stringID="row" value="191">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SysAppClk_ik"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="191">
<row stringID="row" value="192">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SysAppClk_ok"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1555,7 +1559,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="192">
<row stringID="row" value="193">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SysAppSlow_iob2&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1563,7 +1567,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="193">
<row stringID="row" value="194">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="SysAppSlow_iob2&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1571,19 +1575,19 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="194">
<row stringID="row" value="195">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="TempIdDQ_io"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="195">
<row stringID="row" value="196">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="UseGa_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="196">
<row stringID="row" value="197">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VAdcCs_on"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1591,7 +1595,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="197">
<row stringID="row" value="198">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VAdcDin_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1599,13 +1603,13 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="198">
<row stringID="row" value="199">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VAdcDout_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="199">
<row stringID="row" value="200">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VAdcSClk_ok"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1613,7 +1617,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="200">
<row stringID="row" value="201">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VAdjCs_on"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1621,7 +1625,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="201">
<row stringID="row" value="202">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VAdjDin_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1629,7 +1633,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="202">
<row stringID="row" value="203">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VAdjSClk_ok"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1637,7 +1641,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="203">
<row stringID="row" value="204">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VAdjSpi_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1645,13 +1649,13 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="204">
<row stringID="row" value="205">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VcTcXo_ik"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="205">
<row stringID="row" value="206">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeADirVfcToVme_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1659,7 +1663,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="206">
<row stringID="row" value="207">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeAOeN_oen"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1667,235 +1671,235 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="207">
<row stringID="row" value="208">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="208">
<row stringID="row" value="209">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="209">
<row stringID="row" value="210">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="210">
<row stringID="row" value="211">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="211">
<row stringID="row" value="212">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="212">
<row stringID="row" value="213">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="213">
<row stringID="row" value="214">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="214">
<row stringID="row" value="215">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;8>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="215">
<row stringID="row" value="216">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;9>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="216">
<row stringID="row" value="217">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;10>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="217">
<row stringID="row" value="218">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;11>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="218">
<row stringID="row" value="219">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;12>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="219">
<row stringID="row" value="220">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;13>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="220">
<row stringID="row" value="221">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;14>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="221">
<row stringID="row" value="222">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;15>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="222">
<row stringID="row" value="223">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;16>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="223">
<row stringID="row" value="224">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;17>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="224">
<row stringID="row" value="225">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;18>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="225">
<row stringID="row" value="226">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;19>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="226">
<row stringID="row" value="227">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;20>"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
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<row stringID="row" value="228">
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<row stringID="row" value="228">
<row stringID="row" value="229">
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<row stringID="row" value="231">
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</row>
<row stringID="row" value="231">
<row stringID="row" value="232">
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</row>
<row stringID="row" value="232">
<row stringID="row" value="233">
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="233">
<row stringID="row" value="234">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;27>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="234">
<row stringID="row" value="235">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;28>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="235">
<row stringID="row" value="236">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;29>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="236">
<row stringID="row" value="237">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;30>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="237">
<row stringID="row" value="238">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeA_iob31&lt;31>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="238">
<row stringID="row" value="239">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeAm_ib6&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="239">
<row stringID="row" value="240">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeAm_ib6&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="240">
<row stringID="row" value="241">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeAm_ib6&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="241">
<row stringID="row" value="242">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeAm_ib6&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="242">
<row stringID="row" value="243">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeAm_ib6&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="243">
<row stringID="row" value="244">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeAm_ib6&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="244">
<row stringID="row" value="245">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeAs_in"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="245">
<row stringID="row" value="246">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeBerr_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1903,7 +1907,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="246">
<row stringID="row" value="247">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeDDirVfcToVme_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1911,7 +1915,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="247">
<row stringID="row" value="248">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeDOeN_oen"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -1919,7 +1923,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="248">
<row stringID="row" value="249">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1927,7 +1931,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="249">
<row stringID="row" value="250">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1935,7 +1939,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="250">
<row stringID="row" value="251">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1943,7 +1947,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="251">
<row stringID="row" value="252">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1951,7 +1955,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="252">
<row stringID="row" value="253">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1959,7 +1963,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="253">
<row stringID="row" value="254">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1967,7 +1971,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="254">
<row stringID="row" value="255">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1975,7 +1979,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="255">
<row stringID="row" value="256">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1983,7 +1987,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="256">
<row stringID="row" value="257">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;8>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1991,7 +1995,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="257">
<row stringID="row" value="258">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;9>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -1999,7 +2003,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="258">
<row stringID="row" value="259">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;10>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2007,7 +2011,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="259">
<row stringID="row" value="260">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;11>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2015,7 +2019,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="260">
<row stringID="row" value="261">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;12>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2023,7 +2027,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="261">
<row stringID="row" value="262">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;13>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2031,7 +2035,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="262">
<row stringID="row" value="263">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;14>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2039,7 +2043,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="263">
<row stringID="row" value="264">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;15>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2047,7 +2051,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="264">
<row stringID="row" value="265">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;16>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2055,7 +2059,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="265">
<row stringID="row" value="266">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;17>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2063,7 +2067,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="266">
<row stringID="row" value="267">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;18>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2071,7 +2075,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="267">
<row stringID="row" value="268">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;19>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2079,7 +2083,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="268">
<row stringID="row" value="269">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;20>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2087,7 +2091,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="269">
<row stringID="row" value="270">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;21>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2095,7 +2099,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="270">
<row stringID="row" value="271">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;22>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2103,7 +2107,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="271">
<row stringID="row" value="272">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;23>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2111,7 +2115,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="272">
<row stringID="row" value="273">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;24>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2119,7 +2123,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="273">
<row stringID="row" value="274">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;25>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2127,7 +2131,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="274">
<row stringID="row" value="275">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;26>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2135,7 +2139,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="275">
<row stringID="row" value="276">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;27>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2143,7 +2147,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="276">
<row stringID="row" value="277">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;28>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2151,7 +2155,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="277">
<row stringID="row" value="278">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;29>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2159,7 +2163,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="278">
<row stringID="row" value="279">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;30>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2167,7 +2171,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="279">
<row stringID="row" value="280">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeD_iob32&lt;31>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="BIDIR"/>
......@@ -2175,19 +2179,19 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="280">
<row stringID="row" value="281">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeDs_inb2&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="281">
<row stringID="row" value="282">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeDs_inb2&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="282">
<row stringID="row" value="283">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeDtAckOe_oe"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2195,7 +2199,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="283">
<row stringID="row" value="284">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeDtAck_on"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2203,49 +2207,49 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="284">
<row stringID="row" value="285">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeGaP_in"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="285">
<row stringID="row" value="286">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeGa_ib5n&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="286">
<row stringID="row" value="287">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeGa_ib5n&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="287">
<row stringID="row" value="288">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeGa_ib5n&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="288">
<row stringID="row" value="289">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeGa_ib5n&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="289">
<row stringID="row" value="290">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeGa_ib5n&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="290">
<row stringID="row" value="291">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIackIn_in"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="291">
<row stringID="row" value="292">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIackOut_on"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2253,13 +2257,13 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="292">
<row stringID="row" value="293">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIack_in"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="293">
<row stringID="row" value="294">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIrq_ob7&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2267,7 +2271,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="294">
<row stringID="row" value="295">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIrq_ob7&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2275,7 +2279,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="295">
<row stringID="row" value="296">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIrq_ob7&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2283,7 +2287,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="296">
<row stringID="row" value="297">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIrq_ob7&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2291,7 +2295,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="297">
<row stringID="row" value="298">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIrq_ob7&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2299,7 +2303,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="298">
<row stringID="row" value="299">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIrq_ob7&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2307,7 +2311,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="299">
<row stringID="row" value="300">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeIrq_ob7&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2315,13 +2319,13 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="300">
<row stringID="row" value="301">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeLword_io"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="301">
<row stringID="row" value="302">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0BunchSelectDir_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2329,7 +2333,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="302">
<row stringID="row" value="303">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0BunchSelectOe_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2337,7 +2341,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="303">
<row stringID="row" value="304">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0BuslineDir_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2345,7 +2349,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="304">
<row stringID="row" value="305">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0BuslineOe_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2353,7 +2357,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="305">
<row stringID="row" value="306">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0HwHighByteDir_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2361,7 +2365,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="306">
<row stringID="row" value="307">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0HwHighByteOe_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2369,7 +2373,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="307">
<row stringID="row" value="308">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0HwLowByteDir_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2377,7 +2381,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="308">
<row stringID="row" value="309">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0HwLowByteOe_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2385,13 +2389,13 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="309">
<row stringID="row" value="310">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0LvdsBunchClkIn_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="310">
<row stringID="row" value="311">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0LvdsBunchClkOut_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2399,13 +2403,13 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="311">
<row stringID="row" value="312">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0LvdsTClkIn_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="312">
<row stringID="row" value="313">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeP0LvdsTClkOut_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2413,7 +2417,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="313">
<row stringID="row" value="314">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeRetryOe_oe"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2421,7 +2425,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="314">
<row stringID="row" value="315">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeRetry_on"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2429,31 +2433,31 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="315">
<row stringID="row" value="316">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeSysClk_ik"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="316">
<row stringID="row" value="317">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeSysReset_in"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="317">
<row stringID="row" value="318">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeTck_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="318">
<row stringID="row" value="319">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeTdi_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="319">
<row stringID="row" value="320">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeTdoOe_oe"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2461,7 +2465,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="320">
<row stringID="row" value="321">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeTdo_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2469,37 +2473,37 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="321">
<row stringID="row" value="322">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeTms_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="322">
<row stringID="row" value="323">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeTrst_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="323">
<row stringID="row" value="324">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VmeWrite_in"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="324">
<row stringID="row" value="325">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="WRLoS_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="325">
<row stringID="row" value="326">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="WRModeDef0_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
</row>
<row stringID="row" value="326">
<row stringID="row" value="327">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="WRModeDef1_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2507,7 +2511,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="327">
<row stringID="row" value="328">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="WRRateSelect_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2515,7 +2519,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="328">
<row stringID="row" value="329">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="WRTxDisable_o"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
......@@ -2523,7 +2527,7 @@
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="329">
<row stringID="row" value="330">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="WRTxFault_i"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_ngdbuild.xrpt
View file @ c3d17ad2
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Fri Dec 17 09:59:56 2010">
<application stringID="NgdBuild" timeStamp="Fri Dec 17 11:11:22 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -93,9 +89,9 @@
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="151"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
......@@ -125,9 +121,9 @@
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="307"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="186"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="18"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="151"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="66"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="3"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.csv
View file @ c3d17ad2
#Release 12.3 - par M.70d (nt)
#Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Fri Dec 17 10:02:33 2010
#Fri Dec 17 11:12:54 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program
......@@ -296,7 +296,7 @@ E14,,IOBS,IO_L40N_0,UNUSED,,0,,,,,,,,,
E15,,,GND,,,,,,,,,,,,
E16,VmeP0HwLowByteOe_o,IOB,IO_L49N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E17,,,VCCAUX,,,,,,,,2.5,,,,
E18,,IOBS,IO_L51N_0,UNUSED,,0,,,,,,,,,
E18,Si57xOe_o,IOB,IO_L51N_0,OUTPUT,LVCMOS33,0,12,,,,,LOCATED,NO,NONE,
E19,,,GND,,,,,,,,,,,,
E20,VmeWrite_in,IOB,IO_L57N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE,
E21,,,VCCO_0,,,0,,,,,3.30,,,,
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_pad.txt
View file @ c3d17ad2
Release 12.3 - par M.70d (nt)
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 10:02:34 2010
Fri Dec 17 11:12:54 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......@@ -297,7 +297,7 @@ Pinout by Pin Number:
|E15 | | |GND | | | | | | | | | | | |
|E16 |VmeP0HwLowByteOe_o |IOB |IO_L49N_0 |OUTPUT |LVCMOS33 |0 |12 | | | | |LOCATED |NO |NONE |
|E17 | | |VCCAUX | | | | | | | |2.5 | | | |
|E18 | |IOBS |IO_L51N_0 |UNUSED | |0 | | | | | | | | |
|E18 |Si57xOe_o |IOB |IO_L51N_0 |OUTPUT |LVCMOS33 |0 |12 | | | | |LOCATED |NO |NONE |
|E19 | | |GND | | | | | | | | | | | |
|E20 |VmeWrite_in |IOB |IO_L57N_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE |
|E21 | | |VCCO_0 | | |0 | | | | |3.30 | | | |
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_par.xrpt
View file @ c3d17ad2
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Fri Dec 17 10:01:46 2010">
<application stringID="par" timeStamp="Fri Dec 17 11:12:31 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -63,12 +59,12 @@
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="1 mins 4 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="1 mins 2 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="30 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="29 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="1 mins 8 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="1 mins 7 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="32 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="32 secs "/>
</section>
</task>
<task stringID="PAR_par">
......@@ -87,9 +83,9 @@
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y4"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="217.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.248000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.696000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="229.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.260000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.710000"/>
</row>
<row stringID="row" value="2">
<item label="Clock Net" stringID="CLOCK_NET" value="VmeSysClk_ik_BUFGP"/>
......@@ -97,8 +93,8 @@
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y9"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="6.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.083000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.644000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.009000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.640000"/>
</row>
<row stringID="row" value="3">
<item label="Clock Net" stringID="CLOCK_NET" value="VcTcXo_ik_BUFGP"/>
......@@ -114,17 +110,17 @@
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y14"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="15.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.009000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.515000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="16.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.186000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.693000"/>
</row>
<row stringID="row" value="5">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/Rst_rq"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="213.000000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="223.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="6.628000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="7.868000"/>
</row>
<row stringID="row" value="6">
<item label="Clock Net" stringID="CLOCK_NET" value="i_Core/i_VmeInterface/stb_o"/>
......@@ -132,7 +128,7 @@
<item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="19.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.448000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="4.686000"/>
</row>
</table>
</section>
......@@ -2469,10 +2465,16 @@
</row>
<row stringID="row" value="278">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="E18"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOBS"/>
<item label="Signal&#xA;Name" stringID="Signal_Name" value="Si57xOe_o"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L51N_0"/>
<item stringID="Direction" value="UNUSED"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS33"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="0"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="279">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="E19"/>
......@@ -6279,51 +6281,47 @@
</task>
</application>
<application stringID="Par" timeStamp="Fri Dec 17 10:01:47 2010">
<application stringID="Par" timeStamp="Fri Dec 17 11:12:31 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -6335,10 +6333,10 @@
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="941">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="934">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="154"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="587"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="158"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="571"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="166"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
......@@ -6352,25 +6350,25 @@
<item dataType="int" stringID="PAR_NUM_SRL_O6ONLY" value="3"/>
<item dataType="int" stringID="PAR_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO6" value="9"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="22"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_EXO5" value="23"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="22"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_FLOP" value="23"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="9"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="363">
<item AVAILABLE="23038" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="374">
<item AVAILABLE="6099" dataType="int" stringID="PAR_NUM_SLICEL" value="70"/>
<item AVAILABLE="5420" dataType="int" stringID="PAR_NUM_SLICEM" value="4"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="289"/>
<item AVAILABLE="11519" dataType="int" stringID="PAR_NUM_SLICEX" value="300"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1084">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="369"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="143"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="572"/>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="1101">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="386"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="167"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="548"/>
</item>
</section>
<section stringID="PAR_IOB_REPORTING">
<item AVAILABLE="396" dataType="int" stringID="PAR_AGG_BONDED_IO" value="329"/>
<item AVAILABLE="396" dataType="int" stringID="PAR_AGG_BONDED_IO" value="330"/>
<item AVAILABLE="180" dataType="int" stringID="PAR_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="PAR_NUM_IOB_LATCH" value="0"/>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.html
View file @ c3d17ad2
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (12/17/2010 - 10:03:53)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>SFpga Project Status (12/17/2010 - 11:13:37)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>SystemFpga.xise</TD>
......@@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 12.3</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>320 Warnings (0 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/*.xmsgs?&DataKey=Warning'>319 Warnings (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
......@@ -90,19 +90,19 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>941</TD>
<TD ALIGN=RIGHT>934</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>899</TD>
<TD ALIGN=RIGHT>891</TD>
<TD ALIGN=RIGHT>92,152</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>587</TD>
<TD ALIGN=RIGHT>571</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -114,7 +114,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>158</TD>
<TD ALIGN=RIGHT>166</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -186,13 +186,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>32</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>22</TD>
<TD ALIGN=RIGHT>23</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -210,33 +210,33 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>363</TD>
<TD ALIGN=RIGHT>374</TD>
<TD ALIGN=RIGHT>23,038</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>1,084</TD>
<TD ALIGN=RIGHT>1,101</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>369</TD>
<TD ALIGN=RIGHT>1,084</TD>
<TD ALIGN=RIGHT>34%</TD>
<TD ALIGN=RIGHT>386</TD>
<TD ALIGN=RIGHT>1,101</TD>
<TD ALIGN=RIGHT>35%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>143</TD>
<TD ALIGN=RIGHT>1,084</TD>
<TD ALIGN=RIGHT>13%</TD>
<TD ALIGN=RIGHT>167</TD>
<TD ALIGN=RIGHT>1,101</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>572</TD>
<TD ALIGN=RIGHT>1,084</TD>
<TD ALIGN=RIGHT>52%</TD>
<TD ALIGN=RIGHT>548</TD>
<TD ALIGN=RIGHT>1,101</TD>
<TD ALIGN=RIGHT>49%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
......@@ -252,14 +252,14 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>329</TD>
<TD ALIGN=RIGHT>330</TD>
<TD ALIGN=RIGHT>396</TD>
<TD ALIGN=RIGHT>83%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>327</TD>
<TD ALIGN=RIGHT>329</TD>
<TD ALIGN=RIGHT>328</TD>
<TD ALIGN=RIGHT>330</TD>
<TD ALIGN=RIGHT>99%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
......@@ -426,7 +426,7 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>3.03</TD>
<TD ALIGN=RIGHT>3.02</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
......@@ -463,23 +463,23 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Dec 17 09:50:19 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>126 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Dec 17 09:59:56 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Dec 17 10:01:25 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>84 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Dec 17 10:02:35 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>49 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:11:16 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Warning'>126 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/xst.xmsgs?&DataKey=Info'>12 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:11:23 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>14 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:12:20 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Warning'>83 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (1 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:12:55 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/par.xmsgs?&DataKey=Warning'>49 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Dec 17 10:03:01 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Dec 17 10:03:45 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>47 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:13:07 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/trce.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri 17. Dec 11:13:31 2010</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\_xmsgs/bitgen.xmsgs?&DataKey=Warning'>47 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Dec 16 17:57:34 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed Dec 15 15:16:36 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Dec 17 10:03:46 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri Dec 17 10:03:52 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga_preroute.twr'>Post-Map Static Timing Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu 16. Dec 17:57:34 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\SFpga.ibs'>IBIS Model</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Wed 15. Dec 15:16:36 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 17. Dec 11:13:31 2010</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/VFC_SVN/firmware/XilinxISE/SystemFpga\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Fri 17. Dec 11:13:36 2010</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 12/17/2010 - 10:03:53</center>
<br><center><b>Date Generated:</b> 12/17/2010 - 11:13:37</center>
</BODY></HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/SystemFpga/SFpga_summary.xml
View file @ c3d17ad2
......@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="13">
<DesignSummary rev="15">
<CmdHistory>
</CmdHistory>
</DesignSummary>
trunk/firmware/XilinxISE/SystemFpga/SFpga_usage.xml
View file @ c3d17ad2
......@@ -4,798 +4,798 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="13">
<DesignStatistics TimeStamp="Fri Dec 17 10:03:44 2010"><group name="NetStatistics">
<item name="NumNets_Active" rev="13">
<attrib name="value" value="1862"/></item>
<item name="NumNets_Gnd" rev="13">
<DeviceUsageSummary rev="15">
<DesignStatistics TimeStamp="Fri Dec 17 11:13:31 2010"><group name="NetStatistics">
<item name="NumNets_Active" rev="15">
<attrib name="value" value="1863"/></item>
<item name="NumNets_Gnd" rev="15">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="13">
<item name="NumNets_Vcc" rev="15">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="13">
<attrib name="value" value="20"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="13">
<attrib name="value" value="236"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="13">
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="15">
<attrib name="value" value="30"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="15">
<attrib name="value" value="225"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="15">
<attrib name="value" value="4"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="13">
<attrib name="value" value="15"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="13">
<attrib name="value" value="246"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="13">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="13">
<attrib name="value" value="292"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="13">
<attrib name="value" value="1958"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="13">
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="15">
<attrib name="value" value="17"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="15">
<attrib name="value" value="259"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="15">
<attrib name="value" value="21"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="15">
<attrib name="value" value="310"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="15">
<attrib name="value" value="2002"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="15">
<attrib name="value" value="358"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="13">
<attrib name="value" value="131"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="13">
<item name="NumNodesOfType_Active_GLOBAL" rev="15">
<attrib name="value" value="146"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="15">
<attrib name="value" value="50"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="13">
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="15">
<attrib name="value" value="245"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="13">
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="15">
<attrib name="value" value="245"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="13">
<attrib name="value" value="3719"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="13">
<attrib name="value" value="1558"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="13">
<attrib name="value" value="1411"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="13">
<item name="NumNodesOfType_Active_LUTINPUT" rev="15">
<attrib name="value" value="3702"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="15">
<attrib name="value" value="1554"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="15">
<attrib name="value" value="1413"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="15">
<attrib name="value" value="137"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="13">
<item name="NumNodesOfType_Active_PADOUTPUT" rev="15">
<attrib name="value" value="116"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="13">
<attrib name="value" value="815"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="13">
<attrib name="value" value="4273"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="13">
<attrib name="value" value="5304"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="13">
<attrib name="value" value="280"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="13">
<attrib name="value" value="2257"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="13">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="13">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="13">
<attrib name="value" value="135"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="13">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="13">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="13">
<item name="NumNodesOfType_Active_PINBOUNCE" rev="15">
<attrib name="value" value="814"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="15">
<attrib name="value" value="4282"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="15">
<attrib name="value" value="5514"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="15">
<attrib name="value" value="282"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="15">
<attrib name="value" value="2320"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="15">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="15">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="15">
<attrib name="value" value="136"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="15">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_IOBOUTPUT" rev="15">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="15">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="13">
<attrib name="value" value="334"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="13">
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="13">
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="15">
<attrib name="value" value="340"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="15">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="15">
<attrib name="value" value="13"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="13">
<attrib name="value" value="346"/></item>
<item name="NumNodesOfType_Vcc_REGINPUT" rev="13">
<item name="NumNodesOfType_Vcc_PINFEED" rev="15">
<attrib name="value" value="353"/></item>
<item name="NumNodesOfType_Vcc_REGINPUT" rev="15">
<attrib name="value" value="11"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="15">
<attrib name="value" value="4"/></item>
<item name="IOB-IOBM" rev="15">
<attrib name="value" value="161"/></item>
<item name="IOB-IOBS" rev="15">
<attrib name="value" value="165"/></item>
<item name="SLICEL-SLICEM" rev="15">
<attrib name="value" value="25"/></item>
<item name="SLICEX-SLICEL" rev="15">
<attrib name="value" value="73"/></item>
<item name="SLICEX-SLICEM" rev="15">
<attrib name="value" value="63"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="12">
<attrib name="value" value="329"/></item>
<item name="AGG_IO" rev="12">
<attrib name="value" value="329"/></item>
<item name="AGG_LOCED_IO" rev="12">
<attrib name="value" value="327"/></item>
<item name="AGG_SLICE" rev="12">
<attrib name="value" value="363"/></item>
<item name="NUM_BONDED_IOB" rev="12">
<attrib name="value" value="325"/></item>
<item name="NUM_BONDED_IOBM" rev="12">
<attrib name="value" value="2"/></item>
<item name="NUM_BONDED_IOBS" rev="12">
<attrib name="value" value="2"/></item>
<item name="NUM_BSFULL" rev="12">
<attrib name="value" value="572"/></item>
<item name="NUM_BSLUTONLY" rev="12">
<attrib name="value" value="369"/></item>
<item name="NUM_BSREGONLY" rev="12">
<attrib name="value" value="143"/></item>
<item name="NUM_BSUSED" rev="12">
<attrib name="value" value="1084"/></item>
<item name="NUM_BUFG" rev="12">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O5ANDO6" rev="12">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O6ONLY" rev="12">
<attrib name="value" value="4"/></item>
<item name="NUM_LOCED_IOB" rev="12">
<attrib name="value" value="323"/></item>
<item name="NUM_LOCED_IOBM" rev="12">
<attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOBS" rev="12">
<attrib name="value" value="2"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="12">
<attrib name="value" value="158"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="12">
<item name="AGG_BONDED_IO" rev="14">
<attrib name="value" value="330"/></item>
<item name="AGG_IO" rev="14">
<attrib name="value" value="330"/></item>
<item name="AGG_LOCED_IO" rev="14">
<attrib name="value" value="328"/></item>
<item name="AGG_SLICE" rev="14">
<attrib name="value" value="374"/></item>
<item name="NUM_BONDED_IOB" rev="14">
<attrib name="value" value="326"/></item>
<item name="NUM_BONDED_IOBM" rev="14">
<attrib name="value" value="2"/></item>
<item name="NUM_BONDED_IOBS" rev="14">
<attrib name="value" value="2"/></item>
<item name="NUM_BSFULL" rev="14">
<attrib name="value" value="548"/></item>
<item name="NUM_BSLUTONLY" rev="14">
<attrib name="value" value="386"/></item>
<item name="NUM_BSREGONLY" rev="14">
<attrib name="value" value="167"/></item>
<item name="NUM_BSUSED" rev="14">
<attrib name="value" value="1101"/></item>
<item name="NUM_BUFG" rev="14">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O5ANDO6" rev="14">
<attrib name="value" value="4"/></item>
<item name="NUM_DPRAM_O6ONLY" rev="14">
<attrib name="value" value="4"/></item>
<item name="NUM_LOCED_IOB" rev="14">
<attrib name="value" value="324"/></item>
<item name="NUM_LOCED_IOBM" rev="14">
<attrib name="value" value="2"/></item>
<item name="NUM_LOCED_IOBS" rev="14">
<attrib name="value" value="2"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="14">
<attrib name="value" value="166"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="14">
<attrib name="value" value="154"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="12">
<attrib name="value" value="587"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="12">
<item name="NUM_LOGIC_O6ONLY" rev="14">
<attrib name="value" value="571"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="14">
<attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="12">
<attrib name="value" value="22"/></item>
<item name="NUM_LUT_RT_EXO5" rev="12">
<attrib name="value" value="22"/></item>
<item name="NUM_LUT_RT_EXO6" rev="12">
<item name="NUM_LUT_RT_DRIVES_FLOP" rev="14">
<attrib name="value" value="23"/></item>
<item name="NUM_LUT_RT_EXO5" rev="14">
<attrib name="value" value="23"/></item>
<item name="NUM_LUT_RT_EXO6" rev="14">
<attrib name="value" value="9"/></item>
<item name="NUM_LUT_RT_O5" rev="12">
<attrib name="value" value="7"/></item>
<item name="NUM_LUT_RT_O6" rev="12">
<item name="NUM_LUT_RT_O5" rev="14">
<attrib name="value" value="5"/></item>
<item name="NUM_LUT_RT_O6" rev="14">
<attrib name="value" value="154"/></item>
<item name="NUM_SLICEL" rev="12">
<item name="NUM_SLICEL" rev="14">
<attrib name="value" value="70"/></item>
<item name="NUM_SLICEM" rev="12">
<item name="NUM_SLICEM" rev="14">
<attrib name="value" value="4"/></item>
<item name="NUM_SLICEX" rev="12">
<attrib name="value" value="289"/></item>
<item name="NUM_SLICE_CARRY4" rev="12">
<item name="NUM_SLICEX" rev="14">
<attrib name="value" value="300"/></item>
<item name="NUM_SLICE_CARRY4" rev="14">
<attrib name="value" value="52"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="12">
<item name="NUM_SLICE_CONTROLSET" rev="14">
<attrib name="value" value="32"/></item>
<item name="NUM_SLICE_CYINIT" rev="12">
<attrib name="value" value="1275"/></item>
<item name="NUM_SLICE_F7MUX" rev="12">
<item name="NUM_SLICE_CYINIT" rev="14">
<attrib name="value" value="1274"/></item>
<item name="NUM_SLICE_F7MUX" rev="14">
<attrib name="value" value="18"/></item>
<item name="NUM_SLICE_FF" rev="12">
<item name="NUM_SLICE_FF" rev="14">
<attrib name="value" value="796"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="12">
<attrib name="value" value="117"/></item>
<item name="NUM_SRL_O6ONLY" rev="12">
<item name="NUM_SLICE_UNUSEDCTRL" rev="14">
<attrib name="value" value="115"/></item>
<item name="NUM_SRL_O6ONLY" rev="14">
<attrib name="value" value="3"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="12">
<item name="NUM_UNUSABLE_FF_BELS" rev="14">
<attrib name="value" value="85"/></item>
</group>
<group name="SiteStatistics">
<item name="BUFG-BUFGMUX" rev="13">
<attrib name="value" value="4"/></item>
<item name="IOB-IOBM" rev="13">
<attrib name="value" value="161"/></item>
<item name="IOB-IOBS" rev="13">
<attrib name="value" value="164"/></item>
<item name="SLICEL-SLICEM" rev="13">
<attrib name="value" value="18"/></item>
<item name="SLICEX-SLICEL" rev="13">
<attrib name="value" value="63"/></item>
<item name="SLICEX-SLICEM" rev="13">
<attrib name="value" value="66"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Fri Dec 17 10:03:44 2010"><group name="SiteSummary">
<item name="BUFG" rev="13">
<DeviceUsage TimeStamp="Fri Dec 17 11:13:31 2010"><group name="SiteSummary">
<item name="BUFG" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="BUFG_BUFG" rev="13">
<item name="BUFG_BUFG" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="CARRY4" rev="13">
<item name="CARRY4" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="52"/></item>
<item name="FF_SR" rev="13">
<item name="FF_SR" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="89"/></item>
<item name="HARD0" rev="13">
<item name="HARD0" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="IOB" rev="13">
<attrib name="total" value="1000000"/><attrib name="used" value="325"/></item>
<item name="IOBM" rev="13">
<item name="IOB" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="326"/></item>
<item name="IOBM" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBM_OUTBUF" rev="13">
<item name="IOBM_OUTBUF" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOBS" rev="13">
<item name="IOBS" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="IOB_IMUX" rev="13">
<item name="IOB_IMUX" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="159"/></item>
<item name="IOB_INBUF" rev="13">
<item name="IOB_INBUF" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="159"/></item>
<item name="IOB_OUTBUF" rev="13">
<attrib name="total" value="1000000"/><attrib name="used" value="197"/></item>
<item name="LUT5" rev="13">
<attrib name="total" value="1000000"/><attrib name="used" value="341"/></item>
<item name="LUT6" rev="13">
<attrib name="total" value="1000000"/><attrib name="used" value="908"/></item>
<item name="LUT_OR_MEM5" rev="13">
<item name="IOB_OUTBUF" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="198"/></item>
<item name="LUT5" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="348"/></item>
<item name="LUT6" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="900"/></item>
<item name="LUT_OR_MEM5" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="LUT_OR_MEM6" rev="13">
<item name="LUT_OR_MEM6" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="11"/></item>
<item name="NULLMUX" rev="13">
<item name="NULLMUX" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
<item name="PAD" rev="13">
<attrib name="total" value="1000000"/><attrib name="used" value="329"/></item>
<item name="REG_SR" rev="13">
<item name="PAD" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="330"/></item>
<item name="REG_SR" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="707"/></item>
<item name="SELMUX2_1" rev="13">
<item name="SELMUX2_1" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
<item name="SLICEL" rev="13">
<item name="SLICEL" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="70"/></item>
<item name="SLICEM" rev="13">
<item name="SLICEM" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="4"/></item>
<item name="SLICEX" rev="13">
<attrib name="total" value="1000000"/><attrib name="used" value="289"/></item>
<item name="SLICEX" rev="15">
<attrib name="total" value="1000000"/><attrib name="used" value="300"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Fri Dec 17 10:03:44 2010"><group name="REG_SR">
<item name="CK" rev="13">
<ReportConfigData TimeStamp="Fri Dec 17 11:13:31 2010"><group name="REG_SR">
<item name="CK" rev="15">
<attrib name="CK" value="707"/><attrib name="CK_INV" value="0"/></item>
<item name="LATCH_OR_FF" rev="13">
<item name="LATCH_OR_FF" rev="15">
<attrib name="FF" value="707"/></item>
<item name="SRINIT" rev="13">
<item name="SRINIT" rev="15">
<attrib name="SRINIT0" value="655"/><attrib name="SRINIT1" value="52"/></item>
<item name="SYNC_ATTR" rev="13">
<item name="SYNC_ATTR" rev="15">
<attrib name="ASYNC" value="240"/><attrib name="SYNC" value="467"/></item>
</group>
<group name="LUT_OR_MEM5">
<item name="CLK" rev="13">
<item name="CLK" rev="15">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="13">
<item name="LUT_OR_MEM" rev="15">
<attrib name="RAM" value="4"/></item>
<item name="RAMMODE" rev="13">
<item name="RAMMODE" rev="15">
<attrib name="DPRAM32" value="4"/></item>
</group>
<group name="LUT_OR_MEM6">
<item name="CLK" rev="13">
<item name="CLK" rev="15">
<attrib name="CLK" value="11"/><attrib name="CLK_INV" value="0"/></item>
<item name="LUT_OR_MEM" rev="13">
<item name="LUT_OR_MEM" rev="15">
<attrib name="RAM" value="11"/></item>
<item name="RAMMODE" rev="13">
<item name="RAMMODE" rev="15">
<attrib name="SRL16" value="3"/><attrib name="DPRAM32" value="4"/><attrib name="DPRAM64" value="4"/></item>
</group>
<group name="IOBM_OUTBUF">
<item name="SUSPEND" rev="13">
<item name="SUSPEND" rev="15">
<attrib name="3STATE" value="2"/></item>
</group>
<group name="SLICEL">
<item name="CLK" rev="13">
<attrib name="CLK" value="41"/><attrib name="CLK_INV" value="0"/></item>
<item name="CLK" rev="15">
<attrib name="CLK" value="37"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="SLICEM">
<item name="CLK" rev="13">
<item name="CLK" rev="15">
<attrib name="CLK" value="4"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="13">
<attrib name="12" value="166"/></item>
<item name="SLEW" rev="13">
<attrib name="SLOW" value="166"/></item>
<item name="SUSPEND" rev="13">
<attrib name="3STATE" value="197"/></item>
<item name="DRIVEATTRBOX" rev="15">
<attrib name="12" value="167"/></item>
<item name="SLEW" rev="15">
<attrib name="SLOW" value="167"/></item>
<item name="SUSPEND" rev="15">
<attrib name="3STATE" value="198"/></item>
</group>
<group name="SLICEX">
<item name="CLK" rev="13">
<attrib name="CLK" value="201"/><attrib name="CLK_INV" value="0"/></item>
<item name="CLK" rev="15">
<attrib name="CLK" value="218"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="IOB_INBUF">
<item name="DIFF_TERM" rev="13">
<item name="DIFF_TERM" rev="15">
<attrib name="TRUE" value="1"/></item>
</group>
<group name="FF_SR">
<item name="CK" rev="13">
<item name="CK" rev="15">
<attrib name="CK" value="89"/><attrib name="CK_INV" value="0"/></item>
<item name="SRINIT" rev="13">
<item name="SRINIT" rev="15">
<attrib name="SRINIT0" value="78"/><attrib name="SRINIT1" value="11"/></item>
<item name="SYNC_ATTR" rev="13">
<item name="SYNC_ATTR" rev="15">
<attrib name="ASYNC" value="49"/><attrib name="SYNC" value="40"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Fri Dec 17 10:03:44 2010"><group name="NULLMUX">
<item name="0" rev="13">
<ReportPinData TimeStamp="Fri Dec 17 11:13:31 2010"><group name="NULLMUX">
<item name="0" rev="15">
<attrib name="value" value="3"/></item>
<item name="OUT" rev="13">
<item name="OUT" rev="15">
<attrib name="value" value="3"/></item>
</group>
<group name="REG_SR">
<item name="CE" rev="13">
<item name="CE" rev="15">
<attrib name="value" value="389"/></item>
<item name="CK" rev="13">
<item name="CK" rev="15">
<attrib name="value" value="707"/></item>
<item name="D" rev="13">
<item name="D" rev="15">
<attrib name="value" value="707"/></item>
<item name="Q" rev="13">
<item name="Q" rev="15">
<attrib name="value" value="707"/></item>
<item name="SR" rev="13">
<item name="SR" rev="15">
<attrib name="value" value="468"/></item>
</group>
<group name="LUT_OR_MEM5">
<item name="A1" rev="13">
<item name="A1" rev="15">
<attrib name="value" value="4"/></item>
<item name="A2" rev="13">
<item name="A2" rev="15">
<attrib name="value" value="4"/></item>
<item name="A3" rev="13">
<item name="A3" rev="15">
<attrib name="value" value="4"/></item>
<item name="A4" rev="13">
<item name="A4" rev="15">
<attrib name="value" value="4"/></item>
<item name="A5" rev="13">
<item name="A5" rev="15">
<attrib name="value" value="4"/></item>
<item name="CLK" rev="13">
<item name="CLK" rev="15">
<attrib name="value" value="4"/></item>
<item name="DI1" rev="13">
<item name="DI1" rev="15">
<attrib name="value" value="4"/></item>
<item name="O5" rev="13">
<item name="O5" rev="15">
<attrib name="value" value="4"/></item>
<item name="WA1" rev="13">
<item name="WA1" rev="15">
<attrib name="value" value="4"/></item>
<item name="WA2" rev="13">
<item name="WA2" rev="15">
<attrib name="value" value="4"/></item>
<item name="WA3" rev="13">
<item name="WA3" rev="15">
<attrib name="value" value="4"/></item>
<item name="WA4" rev="13">
<item name="WA4" rev="15">
<attrib name="value" value="4"/></item>
<item name="WA5" rev="13">
<item name="WA5" rev="15">
<attrib name="value" value="4"/></item>
<item name="WE" rev="13">
<item name="WE" rev="15">
<attrib name="value" value="4"/></item>
</group>
<group name="LUT_OR_MEM6">
<item name="A1" rev="13">
<item name="A1" rev="15">
<attrib name="value" value="11"/></item>
<item name="A2" rev="13">
<item name="A2" rev="15">
<attrib name="value" value="11"/></item>
<item name="A3" rev="13">
<item name="A3" rev="15">
<attrib name="value" value="11"/></item>
<item name="A4" rev="13">
<item name="A4" rev="15">
<attrib name="value" value="11"/></item>
<item name="A5" rev="13">
<item name="A5" rev="15">
<attrib name="value" value="11"/></item>
<item name="A6" rev="13">
<item name="A6" rev="15">
<attrib name="value" value="11"/></item>
<item name="CLK" rev="13">
<item name="CLK" rev="15">
<attrib name="value" value="11"/></item>
<item name="DI1" rev="13">
<item name="DI1" rev="15">
<attrib name="value" value="4"/></item>
<item name="DI2" rev="13">
<item name="DI2" rev="15">
<attrib name="value" value="7"/></item>
<item name="O6" rev="13">
<item name="O6" rev="15">
<attrib name="value" value="8"/></item>
<item name="WA1" rev="13">
<item name="WA1" rev="15">
<attrib name="value" value="8"/></item>
<item name="WA2" rev="13">
<item name="WA2" rev="15">
<attrib name="value" value="8"/></item>
<item name="WA3" rev="13">
<item name="WA3" rev="15">
<attrib name="value" value="8"/></item>
<item name="WA4" rev="13">
<item name="WA4" rev="15">
<attrib name="value" value="8"/></item>
<item name="WA5" rev="13">
<item name="WA5" rev="15">
<attrib name="value" value="8"/></item>
<item name="WA6" rev="13">
<item name="WA6" rev="15">
<attrib name="value" value="8"/></item>
<item name="WE" rev="13">
<item name="WE" rev="15">
<attrib name="value" value="11"/></item>
</group>
<group name="IOBM_OUTBUF">
<item name="IN" rev="13">
<item name="IN" rev="15">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="13">
<item name="OUT" rev="15">
<attrib name="value" value="2"/></item>
<item name="OUTN" rev="13">
<item name="OUTN" rev="15">
<attrib name="value" value="2"/></item>
</group>
<group name="SLICEL">
<item name="A" rev="13">
<attrib name="value" value="9"/></item>
<item name="A1" rev="13">
<attrib name="value" value="9"/></item>
<item name="A2" rev="13">
<attrib name="value" value="12"/></item>
<item name="A3" rev="13">
<attrib name="value" value="16"/></item>
<item name="A4" rev="13">
<attrib name="value" value="49"/></item>
<item name="A5" rev="13">
<attrib name="value" value="30"/></item>
<item name="A6" rev="13">
<attrib name="value" value="62"/></item>
<item name="AMUX" rev="13">
<attrib name="value" value="19"/></item>
<item name="AQ" rev="13">
<attrib name="value" value="38"/></item>
<item name="AX" rev="13">
<item name="A" rev="15">
<attrib name="value" value="8"/></item>
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<attrib name="value" value="481"/></item>
<item name="A3" rev="15">
<attrib name="value" value="575"/></item>
<item name="A4" rev="15">
<attrib name="value" value="827"/></item>
<item name="A5" rev="15">
<attrib name="value" value="749"/></item>
<item name="A6" rev="15">
<attrib name="value" value="885"/></item>
<item name="O6" rev="15">
<attrib name="value" value="900"/></item>
</group>
<group name="SELMUX2_1">
<item name="0" rev="13">
<item name="0" rev="15">
<attrib name="value" value="18"/></item>
<item name="1" rev="13">
<item name="1" rev="15">
<attrib name="value" value="18"/></item>
<item name="OUT" rev="13">
<item name="OUT" rev="15">
<attrib name="value" value="18"/></item>
<item name="S0" rev="13">
<item name="S0" rev="15">
<attrib name="value" value="18"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="13">
<item name="I" rev="15">
<attrib name="value" value="159"/></item>
<item name="OUT" rev="13">
<item name="OUT" rev="15">
<attrib name="value" value="159"/></item>
</group>
<group name="IOB">
<item name="DIFFI_IN" rev="13">
<item name="DIFFI_IN" rev="15">
<attrib name="value" value="1"/></item>
<item name="I" rev="13">
<item name="I" rev="15">
<attrib name="value" value="159"/></item>
<item name="O" rev="13">
<attrib name="value" value="197"/></item>
<item name="PAD" rev="13">
<attrib name="value" value="325"/></item>
<item name="PADOUT" rev="13">
<item name="O" rev="15">
<attrib name="value" value="198"/></item>
<item name="PAD" rev="15">
<attrib name="value" value="326"/></item>
<item name="PADOUT" rev="15">
<attrib name="value" value="1"/></item>
<item name="T" rev="13">
<item name="T" rev="15">
<attrib name="value" value="44"/></item>
</group>
<group name="HARD0">
<item name="0" rev="13">
<item name="0" rev="15">
<attrib name="value" value="11"/></item>
</group>
<group name="FF_SR">
<item name="CE" rev="13">
<item name="CE" rev="15">
<attrib name="value" value="52"/></item>
<item name="CK" rev="13">
<item name="CK" rev="15">
<attrib name="value" value="89"/></item>
<item name="D" rev="13">
<item name="D" rev="15">
<attrib name="value" value="89"/></item>
<item name="Q" rev="13">
<item name="Q" rev="15">
<attrib name="value" value="89"/></item>
<item name="SR" rev="13">
<item name="SR" rev="15">
<attrib name="value" value="40"/></item>
</group>
<group name="BUFG">
<item name="I0" rev="13">
<item name="I0" rev="15">
<attrib name="value" value="4"/></item>
<item name="O" rev="13">
<item name="O" rev="15">
<attrib name="value" value="4"/></item>
</group>
</ReportPinData>
......
trunk/firmware/XilinxISE/SystemFpga/SFpga_xst.xrpt
View file @ c3d17ad2
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt" product="ISE" version="12.3">
<document OS="nt64" product="ISE" version="12.3">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Fri Dec 17 09:49:53 2010">
<application stringID="Xst" timeStamp="Fri Dec 17 11:10:57 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt;C:\Xilinx\12.3\ISE_DS\common\bin\nt;C:\Xilinx\12.3\ISE_DS\common\lib\nt;C:\WINNT\system32;C:\WINNT;C:\WINNT\System32\Wbem;C:\Cadence\Psd\tools\bin;c:\cadence\psd\tools\jre\bin;C:\Program Files\Altium Designer Winter 09\System;c:\altera\90\quartus\bin;C:\Program Files\TortoiseSVN\bin;C:\WINNT\system32\WindowsPowerShell\v1.0;C:\Program Files\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files\QuickTime\QTSystem\;C:\Modeltech_6.3d\win32"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\\lib\nt64;C:\Xilinx\12.3\ISE_DS\ISE\\bin\nt64;C:\Xilinx\12.3\ISE_DS\PlanAhead\bin;C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64;C:\Xilinx\12.3\ISE_DS\ISE\lib\nt64;C:\Xilinx\12.3\ISE_DS\EDK\bin\nt64;C:\Xilinx\12.3\ISE_DS\EDK\lib\nt64;C:\Xilinx\12.3\ISE_DS\common\bin\nt64;C:\Xilinx\12.3\ISE_DS\common\lib\nt64;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.PSC1;.PSC1"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="C:\Xilinx\xilinx.lic"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\ISE"/>
</row>
<row stringID="row" value="5">
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\EDK"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\12.3\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows XP Professional"/>
<item stringID="User_EnvOsrelease" value="Service Pack 3 (build 2600)"/>
<item stringID="User_EnvOsname" value="Microsoft "/>
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
</item>
<item stringID="User_EnvHost" value="bqplv2"/>
<item stringID="User_EnvHost" value="PCBE13225"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value=" Intel(R) Pentium(R) D CPU 3.40GHz"/>
<item stringID="speed" value="3389 MHz"/>
<item stringID="arch" value="Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz"/>
<item stringID="speed" value="3158 MHz"/>
</row>
</table>
</section>
......@@ -137,8 +133,8 @@
<item dataType="int" stringID="XST_5BIT_2TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_7BIT_2TO1_MULTIPLEXER" value="1"/>
</item>
<item dataType="int" stringID="XST_TRISTATES" value="66">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="66"/>
<item dataType="int" stringID="XST_TRISTATES" value="65">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="65"/>
</item>
<item dataType="int" stringID="XST_FSMS" value="2"/>
<item dataType="int" stringID="XST_XORS" value="4">
......@@ -233,8 +229,8 @@
<item dataType="int" stringID="XST_IO_BUFFERS" value="305">
<item dataType="int" stringID="XST_IBUF" value="77"/>
<item dataType="int" label="-iobuf" stringID="XST_IOBUF" value="32"/>
<item dataType="int" stringID="XST_OBUF" value="151"/>
<item dataType="int" stringID="XST_OBUFT" value="34"/>
<item dataType="int" stringID="XST_OBUF" value="152"/>
<item dataType="int" stringID="XST_OBUFT" value="33"/>
</item>
</section>
</section>
......
trunk/firmware/XilinxISE/SystemFpga/SystemFpga.gise
View file @ c3d17ad2
......@@ -107,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292575819" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292575791">
<transform xil_pn:end_ts="1292580677" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292580654">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -129,7 +129,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292576396" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292576389">
<transform xil_pn:end_ts="1292580684" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292580677">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -139,7 +139,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292576485" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292576396">
<transform xil_pn:end_ts="1292580741" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292580684">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -155,7 +155,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292576581" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292576485">
<transform xil_pn:end_ts="1292580788" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292580741">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -170,7 +170,7 @@
<outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292576632" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292576581">
<transform xil_pn:end_ts="1292580816" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1292580788">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -183,6 +183,10 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1292580983" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1292580980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292422596" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_createIBISModel_spartan6" xil_pn:prop_ck="-6143094129183081966" xil_pn:start_ts="1292422570">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -193,7 +197,7 @@
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1292576581" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292576556">
<transform xil_pn:end_ts="1292580788" xil_pn:in_ck="6743535591587205937" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1292580776">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SFpga.twr"/>
......
trunk/firmware/XilinxISE/SystemFpga/_ngo/netlist.lst
View file @ c3d17ad2
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292575819
C:\VFC_SVN\firmware\XilinxISE\SystemFpga\SFpga.ngc 1292580676
OK
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/map.xmsgs
View file @ c3d17ad2
......@@ -119,9 +119,6 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Fmc2SDa_io</arg> connected to top level port <arg fmt="%s" index="2">Fmc2SDa_io</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">Si57xOe_o</arg> connected to top level port <arg fmt="%s" index="2">Si57xOe_o</arg> has been removed.
</msg>
<msg type="warning" file="MapLib" num="701" delta="old" >Signal <arg fmt="%s" index="1">AFpgaProgProgram_o</arg> connected to top level port <arg fmt="%s" index="2">AFpgaProgProgram_o</arg> has been removed.
</msg>
......@@ -140,7 +137,7 @@ To see the details of these <arg fmt="%s" index="4">info</arg> messages, please
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Place" num="834" delta="old" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">329</arg> IOs, <arg fmt="%d" index="2">327</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
<msg type="info" file="Place" num="834" delta="new" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">330</arg> IOs, <arg fmt="%d" index="2">328</arg> are locked and <arg fmt="%d" index="3">2</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg>
<msg type="warning" file="Place" num="1109" delta="old" >A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component &lt;<arg fmt="%s" index="1">VmeSysClk_ik</arg>&gt; is placed at site &lt;<arg fmt="%s" index="2">PAD550</arg>&gt;. The corresponding BUFG component &lt;<arg fmt="%s" index="3">VmeSysClk_ik_BUFGP/BUFG</arg>&gt; is placed at site &lt;<arg fmt="%s" index="4">BUFGMUX_X2Y9</arg>&gt;. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN &lt;<arg fmt="%s" index="5">VmeSysClk_ik.PAD</arg>&gt; allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
......
trunk/firmware/XilinxISE/SystemFpga/_xmsgs/pn_parser.xmsgs
View file @ c3d17ad2
......@@ -8,5 +8,8 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1648" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/VFC_SVN/hdl/design/SystemFpga.v\&quot; into library work</arg>
</msg>
</messages>
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport
View file @ c3d17ad2
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2010-12-17T09:49:40</DateModified>
<DateModified>2010-12-17T11:09:45</DateModified>
<ModuleName>SFpga</ModuleName>
<SummaryTimeStamp>2010-12-15T15:17:10</SummaryTimeStamp>
<SavedFilePath>C:/VFC_SVN/firmware/XilinxISE/SystemFpga/iseconfig/SFpga.xreport</SavedFilePath>
......
trunk/firmware/XilinxISE/SystemFpga/iseconfig/SystemFpga.projectmgr
View file @ c3d17ad2
......@@ -57,7 +57,6 @@
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map/Generate Post-Map Static Timing</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
......@@ -65,13 +64,13 @@
<ClosedNode>Implement Design/Translate</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Generate Programming File</SelectedItem>
<SelectedItem>Generate Target PROM/ACE File</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >1</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >14</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000191000000010000000100000000000000000000000064ffffffff000000810000000000000001000001910000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Programming File</CurrentItem>
<CurrentItem>Generate Target PROM/ACE File</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
......
trunk/firmware/XilinxISE/SystemFpga/par_usage_statistics.html
View file @ c3d17ad2
......@@ -2,30 +2,30 @@
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>1486</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4724</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4724</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4258</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>25.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>31.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>43.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>55.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>61.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>62.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>15.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>4740</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>4740</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>4274</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>11.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>15.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>21.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>26.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>29.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>29.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>16.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>10.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>6.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>9.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>4.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>8.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>5.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>5.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.1180</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0984</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
trunk/firmware/XilinxISE/SystemFpga/sfpga.bgn
View file @ c3d17ad2
Release 12.3 - Bitgen M.70d (nt)
Release 12.3 - Bitgen M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx150t.nph' in environment
C:\Xilinx\12.3\ISE_DS\ISE\.
"SFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Opened constraints file SFpga.pcf.
Fri Dec 17 10:03:13 2010
Fri Dec 17 11:13:13 2010
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SFpga.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
......
trunk/firmware/XilinxISE/SystemFpga/sfpga.drc
View file @ c3d17ad2
Release 12.3 Drc M.70d (nt)
Release 12.3 Drc M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Fri Dec 17 10:03:13 2010
Fri Dec 17 11:13:13 2010
drc -z SFpga.ncd SFpga.pcf
......
trunk/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html
View file @ c3d17ad2
......@@ -11,13 +11,13 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>OS Platform:</B></TD>
<TD><xtag-property name="OSPlatform">NT</xtag-property></TD>
<TD><xtag-property name="OSPlatform">NT64</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD><xtag-property name="TargetDevice">xc6slx150t</xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">d36a4175861f4f48ac5a6ada421762f9</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">5</xtag-property></TD>
<TD><xtag-property name="RandomID">effa8437e76f45ca9db699794ac1987e</xtag-property>.<xtag-property name="ProjectID">F6031676C5FE434A8E9F8A1057A8E48F</xtag-property>.<xtag-property name="ProjectIteration">6</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">fgg676</xtag-property></TD>
</TR>
......@@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2010-12-17T10:03:46</xtag-property></TD>
<TD><xtag-property name="Date Generated">2010-12-17T11:13:31</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">ISE</xtag-property></TD>
</TR>
......@@ -39,27 +39,27 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=4><B>User Environment</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows XP Professional</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft </xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 3 (build 2600)</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>major release (build 7600)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value> Intel(R) Pentium(R) D CPU 3.40GHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3389 MHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3158 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft Windows XP Professional</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Name</xtag-env-param-name>"><xtag-env-param-value>Microsoft </xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>OS Release</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>Service Pack 3 (build 2600)</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>OS Release</xtag-env-param-name>"><xtag-env-param-value>major release (build 7600)</xtag-env-param-value></xtag-property></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Name</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value> Intel(R) Pentium(R) D CPU 3.40GHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Name</xtag-env-param-name>"><xtag-env-param-value>Intel(R) Core(TM)2 Duo CPU E8500 @ 3.16GHz</xtag-env-param-value></xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B><xtag-env-param-name>CPU Speed</xtag-env-param-name></B></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3389 MHz</xtag-env-param-value></xtag-property></TD>
<TD><xtag-property name="<xtag-env-param-name>CPU Speed</xtag-env-param-name>"><xtag-env-param-value>3158 MHz</xtag-env-param-value></xtag-property></TD>
</TR>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
......@@ -133,41 +133,41 @@
<TD>
<xtag-group><xtag-group-name name="MiscellaneousStatistics">MiscellaneousStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>AGG_BONDED_IO=329</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=329</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=327</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=363</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=325</xtag-item1></LI>
<LI><xtag-item1>AGG_BONDED_IO=330</xtag-item1></LI>
<LI><xtag-item1>AGG_IO=330</xtag-item1></LI>
<LI><xtag-item1>AGG_LOCED_IO=328</xtag-item1></LI>
<LI><xtag-item1>AGG_SLICE=374</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOB=326</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BONDED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=572</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=369</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=143</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1084</xtag-item1></LI>
<LI><xtag-item1>NUM_BSFULL=548</xtag-item1></LI>
<LI><xtag-item1>NUM_BSLUTONLY=386</xtag-item1></LI>
<LI><xtag-item1>NUM_BSREGONLY=167</xtag-item1></LI>
<LI><xtag-item1>NUM_BSUSED=1101</xtag-item1></LI>
<LI><xtag-item1>NUM_BUFG=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O5ANDO6=4</xtag-item1></LI>
<LI><xtag-item1>NUM_DPRAM_O6ONLY=4</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=323</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOB=324</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBM=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOCED_IOBS=2</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=158</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ANDO6=166</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O5ONLY=154</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=587</xtag-item1></LI>
<LI><xtag-item1>NUM_LOGIC_O6ONLY=571</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_CARRY4=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=22</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=22</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_DRIVES_FLOP=23</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO5=23</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_EXO6=9</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=7</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O5=5</xtag-item1></LI>
<LI><xtag-item1>NUM_LUT_RT_O6=154</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEL=70</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEM=4</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=289</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICEX=300</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CARRY4=52</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CONTROLSET=32</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1275</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_CYINIT=1274</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_F7MUX=18</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_FF=796</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=117</xtag-item1></LI>
<LI><xtag-item1>NUM_SLICE_UNUSEDCTRL=115</xtag-item1></LI>
<LI><xtag-item1>NUM_SRL_O6ONLY=3</xtag-item1></LI>
<LI><xtag-item1>NUM_UNUSABLE_FF_BELS=85</xtag-item1></LI>
</UL>
......@@ -176,42 +176,42 @@
<TD>
<xtag-group><xtag-group-name name="NetStatistics">NetStatistics</xtag-group-name>
<UL>
<LI><xtag-item1>NumNets_Active=1862</xtag-item1></LI>
<LI><xtag-item1>NumNets_Active=1863</xtag-item1></LI>
<LI><xtag-item1>NumNets_Gnd=1</xtag-item1></LI>
<LI><xtag-item1>NumNets_Vcc=1</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=20</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=236</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEACROSS=30</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BOUNCEIN=225</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFGOUT=4</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=15</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=246</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=19</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=292</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=1958</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_BUFHINP2OUT=17</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPIN=259</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CLKPINFEED=21</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_CNTRLPIN=310</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_DOUBLE=2002</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GENERIC=358</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=131</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_GLOBAL=146</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_INPUT=50</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBIN2OUT=245</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_IOBOUTPUT=245</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3719</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1558</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1411</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_LUTINPUT=3702</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTBOUND=1554</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_OUTPUT=1413</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADINPUT=137</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PADOUTPUT=116</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=815</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4273</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5304</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=280</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2257</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINBOUNCE=814</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_PINFEED=4282</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_QUAD=5514</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_REGINPUT=282</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Active_SINGLE=2320</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_CNTRLPIN=2</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=135</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_GENERIC=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_HVCCOUT=136</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBIN2OUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_IOBOUTPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_KVCCOUT=6</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=334</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=12</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_LUTINPUT=340</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PADINPUT=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINBOUNCE=13</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=346</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_PINFEED=353</xtag-item1></LI>
<LI><xtag-item1>NumNodesOfType_Vcc_REGINPUT=11</xtag-item1></LI>
</UL>
</xtag-group>
......@@ -219,10 +219,10 @@
<UL>
<LI><xtag-item1>BUFG-BUFGMUX=4</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBM=161</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=164</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=18</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=63</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=66</xtag-item1></LI>
<LI><xtag-item1>IOB-IOBS=165</xtag-item1></LI>
<LI><xtag-item1>SLICEL-SLICEM=25</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEL=73</xtag-item1></LI>
<LI><xtag-item1>SLICEX-SLICEM=63</xtag-item1></LI>
</UL>
</xtag-group>
</TD>
......@@ -236,24 +236,24 @@
<LI><xtag-item2>CARRY4=52</xtag-item2></LI>
<LI><xtag-item2>FF_SR=89</xtag-item2></LI>
<LI><xtag-item2>HARD0=11</xtag-item2></LI>
<LI><xtag-item2>IOB=325</xtag-item2></LI>
<LI><xtag-item2>IOB=326</xtag-item2></LI>
<LI><xtag-item2>IOBM=2</xtag-item2></LI>
<LI><xtag-item2>IOBM_OUTBUF=2</xtag-item2></LI>
<LI><xtag-item2>IOBS=2</xtag-item2></LI>
<LI><xtag-item2>IOB_IMUX=159</xtag-item2></LI>
<LI><xtag-item2>IOB_INBUF=159</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=197</xtag-item2></LI>
<LI><xtag-item2>LUT5=341</xtag-item2></LI>
<LI><xtag-item2>LUT6=908</xtag-item2></LI>
<LI><xtag-item2>IOB_OUTBUF=198</xtag-item2></LI>
<LI><xtag-item2>LUT5=348</xtag-item2></LI>
<LI><xtag-item2>LUT6=900</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM5=4</xtag-item2></LI>
<LI><xtag-item2>LUT_OR_MEM6=11</xtag-item2></LI>
<LI><xtag-item2>NULLMUX=3</xtag-item2></LI>
<LI><xtag-item2>PAD=329</xtag-item2></LI>
<LI><xtag-item2>PAD=330</xtag-item2></LI>
<LI><xtag-item2>REG_SR=707</xtag-item2></LI>
<LI><xtag-item2>SELMUX2_1=18</xtag-item2></LI>
<LI><xtag-item2>SLICEL=70</xtag-item2></LI>
<LI><xtag-item2>SLICEM=4</xtag-item2></LI>
<LI><xtag-item2>SLICEX=289</xtag-item2></LI>
<LI><xtag-item2>SLICEX=300</xtag-item2></LI>
</UL>
</xtag-group>
</TD>
......@@ -284,9 +284,9 @@
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item3>DRIVEATTRBOX=[12:166]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:166]</xtag-item3></LI>
<LI><xtag-item3>SUSPEND=[3STATE:197]</xtag-item3></LI>
<LI><xtag-item3>DRIVEATTRBOX=[12:167]</xtag-item3></LI>
<LI><xtag-item3>SLEW=[SLOW:167]</xtag-item3></LI>
<LI><xtag-item3>SUSPEND=[3STATE:198]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT_OR_MEM5">LUT_OR_MEM5</xtag-group-name>
......@@ -317,7 +317,7 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:41] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:37] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="SLICEM">SLICEM</xtag-group-name>
......@@ -327,7 +327,7 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item3>CLK=[CLK:201] [CLK_INV:0]</xtag-item3></LI>
<LI><xtag-item3>CLK=[CLK:218] [CLK_INV:0]</xtag-item3></LI>
</UL>
</xtag-group>
</TD>
......@@ -388,8 +388,8 @@
<UL>
<LI><xtag-item1>DIFFI_IN=1</xtag-item1></LI>
<LI><xtag-item1>I=159</xtag-item1></LI>
<LI><xtag-item1>O=197</xtag-item1></LI>
<LI><xtag-item1>PAD=325</xtag-item1></LI>
<LI><xtag-item1>O=198</xtag-item1></LI>
<LI><xtag-item1>PAD=326</xtag-item1></LI>
<LI><xtag-item1>PADOUT=1</xtag-item1></LI>
<LI><xtag-item1>T=44</xtag-item1></LI>
</UL>
......@@ -429,30 +429,30 @@
</xtag-group>
<xtag-group><xtag-group-name name="IOB_OUTBUF">IOB_OUTBUF</xtag-group-name>
<UL>
<LI><xtag-item1>IN=197</xtag-item1></LI>
<LI><xtag-item1>OUT=197</xtag-item1></LI>
<LI><xtag-item1>IN=198</xtag-item1></LI>
<LI><xtag-item1>OUT=198</xtag-item1></LI>
<LI><xtag-item1>TRI=44</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT5">LUT5</xtag-group-name>
<UL>
<LI><xtag-item1>A1=32</xtag-item1></LI>
<LI><xtag-item1>A2=56</xtag-item1></LI>
<LI><xtag-item1>A3=109</xtag-item1></LI>
<LI><xtag-item1>A4=122</xtag-item1></LI>
<LI><xtag-item1>A5=88</xtag-item1></LI>
<LI><xtag-item1>O5=341</xtag-item1></LI>
<LI><xtag-item1>A1=47</xtag-item1></LI>
<LI><xtag-item1>A2=48</xtag-item1></LI>
<LI><xtag-item1>A3=125</xtag-item1></LI>
<LI><xtag-item1>A4=130</xtag-item1></LI>
<LI><xtag-item1>A5=80</xtag-item1></LI>
<LI><xtag-item1>O5=348</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="LUT6">LUT6</xtag-group-name>
<UL>
<LI><xtag-item1>A1=311</xtag-item1></LI>
<LI><xtag-item1>A2=466</xtag-item1></LI>
<LI><xtag-item1>A3=584</xtag-item1></LI>
<LI><xtag-item1>A4=832</xtag-item1></LI>
<LI><xtag-item1>A5=759</xtag-item1></LI>
<LI><xtag-item1>A6=894</xtag-item1></LI>
<LI><xtag-item1>O6=908</xtag-item1></LI>
<LI><xtag-item1>A2=481</xtag-item1></LI>
<LI><xtag-item1>A3=575</xtag-item1></LI>
<LI><xtag-item1>A4=827</xtag-item1></LI>
<LI><xtag-item1>A5=749</xtag-item1></LI>
<LI><xtag-item1>A6=885</xtag-item1></LI>
<LI><xtag-item1>O6=900</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -504,7 +504,7 @@
</xtag-group>
<xtag-group><xtag-group-name name="PAD">PAD</xtag-group-name>
<UL>
<LI><xtag-item1>PAD=329</xtag-item1></LI>
<LI><xtag-item1>PAD=330</xtag-item1></LI>
</UL>
</xtag-group>
<xtag-group><xtag-group-name name="REG_SR">REG_SR</xtag-group-name>
......@@ -526,49 +526,49 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEL">SLICEL</xtag-group-name>
<UL>
<LI><xtag-item1>A=9</xtag-item1></LI>
<LI><xtag-item1>A1=9</xtag-item1></LI>
<LI><xtag-item1>A2=12</xtag-item1></LI>
<LI><xtag-item1>A3=16</xtag-item1></LI>
<LI><xtag-item1>A4=49</xtag-item1></LI>
<LI><xtag-item1>A5=30</xtag-item1></LI>
<LI><xtag-item1>A6=62</xtag-item1></LI>
<LI><xtag-item1>A=8</xtag-item1></LI>
<LI><xtag-item1>A1=11</xtag-item1></LI>
<LI><xtag-item1>A2=11</xtag-item1></LI>
<LI><xtag-item1>A3=14</xtag-item1></LI>
<LI><xtag-item1>A4=48</xtag-item1></LI>
<LI><xtag-item1>A5=29</xtag-item1></LI>
<LI><xtag-item1>A6=61</xtag-item1></LI>
<LI><xtag-item1>AMUX=19</xtag-item1></LI>
<LI><xtag-item1>AQ=38</xtag-item1></LI>
<LI><xtag-item1>AQ=37</xtag-item1></LI>
<LI><xtag-item1>AX=8</xtag-item1></LI>
<LI><xtag-item1>B=11</xtag-item1></LI>
<LI><xtag-item1>B1=9</xtag-item1></LI>
<LI><xtag-item1>B2=11</xtag-item1></LI>
<LI><xtag-item1>B3=13</xtag-item1></LI>
<LI><xtag-item1>B4=50</xtag-item1></LI>
<LI><xtag-item1>B5=30</xtag-item1></LI>
<LI><xtag-item1>B6=60</xtag-item1></LI>
<LI><xtag-item1>BMUX=17</xtag-item1></LI>
<LI><xtag-item1>BQ=37</xtag-item1></LI>
<LI><xtag-item1>BX=6</xtag-item1></LI>
<LI><xtag-item1>B=9</xtag-item1></LI>
<LI><xtag-item1>B1=8</xtag-item1></LI>
<LI><xtag-item1>B2=9</xtag-item1></LI>
<LI><xtag-item1>B3=12</xtag-item1></LI>
<LI><xtag-item1>B4=47</xtag-item1></LI>
<LI><xtag-item1>B5=27</xtag-item1></LI>
<LI><xtag-item1>B6=57</xtag-item1></LI>
<LI><xtag-item1>BMUX=18</xtag-item1></LI>
<LI><xtag-item1>BQ=35</xtag-item1></LI>
<LI><xtag-item1>BX=4</xtag-item1></LI>
<LI><xtag-item1>C1=7</xtag-item1></LI>
<LI><xtag-item1>C2=8</xtag-item1></LI>
<LI><xtag-item1>C3=19</xtag-item1></LI>
<LI><xtag-item1>C4=49</xtag-item1></LI>
<LI><xtag-item1>C5=33</xtag-item1></LI>
<LI><xtag-item1>C6=62</xtag-item1></LI>
<LI><xtag-item1>CE=16</xtag-item1></LI>
<LI><xtag-item1>C5=32</xtag-item1></LI>
<LI><xtag-item1>C6=61</xtag-item1></LI>
<LI><xtag-item1>CE=13</xtag-item1></LI>
<LI><xtag-item1>CIN=40</xtag-item1></LI>
<LI><xtag-item1>CLK=41</xtag-item1></LI>
<LI><xtag-item1>CLK=37</xtag-item1></LI>
<LI><xtag-item1>CMUX=32</xtag-item1></LI>
<LI><xtag-item1>COUT=40</xtag-item1></LI>
<LI><xtag-item1>CQ=35</xtag-item1></LI>
<LI><xtag-item1>CQ=34</xtag-item1></LI>
<LI><xtag-item1>CX=21</xtag-item1></LI>
<LI><xtag-item1>D1=8</xtag-item1></LI>
<LI><xtag-item1>D2=21</xtag-item1></LI>
<LI><xtag-item1>D3=23</xtag-item1></LI>
<LI><xtag-item1>D4=53</xtag-item1></LI>
<LI><xtag-item1>D5=34</xtag-item1></LI>
<LI><xtag-item1>D6=62</xtag-item1></LI>
<LI><xtag-item1>D4=52</xtag-item1></LI>
<LI><xtag-item1>D5=33</xtag-item1></LI>
<LI><xtag-item1>D6=61</xtag-item1></LI>
<LI><xtag-item1>DMUX=15</xtag-item1></LI>
<LI><xtag-item1>DQ=36</xtag-item1></LI>
<LI><xtag-item1>DX=8</xtag-item1></LI>
<LI><xtag-item1>SR=23</xtag-item1></LI>
<LI><xtag-item1>DQ=32</xtag-item1></LI>
<LI><xtag-item1>DX=5</xtag-item1></LI>
<LI><xtag-item1>SR=19</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -622,49 +622,49 @@
</xtag-group>
<xtag-group><xtag-group-name name="SLICEX">SLICEX</xtag-group-name>
<UL>
<LI><xtag-item1>A=122</xtag-item1></LI>
<LI><xtag-item1>A1=99</xtag-item1></LI>
<LI><xtag-item1>A2=153</xtag-item1></LI>
<LI><xtag-item1>A3=191</xtag-item1></LI>
<LI><xtag-item1>A4=206</xtag-item1></LI>
<LI><xtag-item1>A5=208</xtag-item1></LI>
<LI><xtag-item1>A6=209</xtag-item1></LI>
<LI><xtag-item1>AMUX=48</xtag-item1></LI>
<LI><xtag-item1>AQ=159</xtag-item1></LI>
<LI><xtag-item1>AX=62</xtag-item1></LI>
<LI><xtag-item1>B=88</xtag-item1></LI>
<LI><xtag-item1>B1=75</xtag-item1></LI>
<LI><xtag-item1>B2=114</xtag-item1></LI>
<LI><xtag-item1>B3=150</xtag-item1></LI>
<LI><xtag-item1>B4=157</xtag-item1></LI>
<LI><xtag-item1>B5=163</xtag-item1></LI>
<LI><xtag-item1>B6=157</xtag-item1></LI>
<LI><xtag-item1>A=117</xtag-item1></LI>
<LI><xtag-item1>A1=107</xtag-item1></LI>
<LI><xtag-item1>A2=152</xtag-item1></LI>
<LI><xtag-item1>A3=189</xtag-item1></LI>
<LI><xtag-item1>A4=205</xtag-item1></LI>
<LI><xtag-item1>A5=204</xtag-item1></LI>
<LI><xtag-item1>A6=206</xtag-item1></LI>
<LI><xtag-item1>AMUX=51</xtag-item1></LI>
<LI><xtag-item1>AQ=165</xtag-item1></LI>
<LI><xtag-item1>AX=66</xtag-item1></LI>
<LI><xtag-item1>B=84</xtag-item1></LI>
<LI><xtag-item1>B1=70</xtag-item1></LI>
<LI><xtag-item1>B2=117</xtag-item1></LI>
<LI><xtag-item1>B3=144</xtag-item1></LI>
<LI><xtag-item1>B4=153</xtag-item1></LI>
<LI><xtag-item1>B5=158</xtag-item1></LI>
<LI><xtag-item1>B6=155</xtag-item1></LI>
<LI><xtag-item1>BMUX=38</xtag-item1></LI>
<LI><xtag-item1>BQ=133</xtag-item1></LI>
<LI><xtag-item1>BX=62</xtag-item1></LI>
<LI><xtag-item1>C=63</xtag-item1></LI>
<LI><xtag-item1>C1=75</xtag-item1></LI>
<LI><xtag-item1>C2=97</xtag-item1></LI>
<LI><xtag-item1>C3=125</xtag-item1></LI>
<LI><xtag-item1>C4=137</xtag-item1></LI>
<LI><xtag-item1>C5=144</xtag-item1></LI>
<LI><xtag-item1>C6=143</xtag-item1></LI>
<LI><xtag-item1>CE=104</xtag-item1></LI>
<LI><xtag-item1>CLK=201</xtag-item1></LI>
<LI><xtag-item1>CMUX=30</xtag-item1></LI>
<LI><xtag-item1>CQ=139</xtag-item1></LI>
<LI><xtag-item1>CX=57</xtag-item1></LI>
<LI><xtag-item1>D=76</xtag-item1></LI>
<LI><xtag-item1>D1=58</xtag-item1></LI>
<LI><xtag-item1>D2=90</xtag-item1></LI>
<LI><xtag-item1>D3=122</xtag-item1></LI>
<LI><xtag-item1>D4=132</xtag-item1></LI>
<LI><xtag-item1>D5=140</xtag-item1></LI>
<LI><xtag-item1>D6=139</xtag-item1></LI>
<LI><xtag-item1>DMUX=43</xtag-item1></LI>
<LI><xtag-item1>DQ=127</xtag-item1></LI>
<LI><xtag-item1>DX=61</xtag-item1></LI>
<LI><xtag-item1>SR=147</xtag-item1></LI>
<LI><xtag-item1>BQ=136</xtag-item1></LI>
<LI><xtag-item1>BX=64</xtag-item1></LI>
<LI><xtag-item1>C=55</xtag-item1></LI>
<LI><xtag-item1>C1=79</xtag-item1></LI>
<LI><xtag-item1>C2=94</xtag-item1></LI>
<LI><xtag-item1>C3=122</xtag-item1></LI>
<LI><xtag-item1>C4=133</xtag-item1></LI>
<LI><xtag-item1>C5=139</xtag-item1></LI>
<LI><xtag-item1>C6=134</xtag-item1></LI>
<LI><xtag-item1>CE=112</xtag-item1></LI>
<LI><xtag-item1>CLK=218</xtag-item1></LI>
<LI><xtag-item1>CMUX=31</xtag-item1></LI>
<LI><xtag-item1>CQ=141</xtag-item1></LI>
<LI><xtag-item1>CX=59</xtag-item1></LI>
<LI><xtag-item1>D=88</xtag-item1></LI>
<LI><xtag-item1>D1=65</xtag-item1></LI>
<LI><xtag-item1>D2=101</xtag-item1></LI>
<LI><xtag-item1>D3=128</xtag-item1></LI>
<LI><xtag-item1>D4=140</xtag-item1></LI>
<LI><xtag-item1>D5=150</xtag-item1></LI>
<LI><xtag-item1>D6=150</xtag-item1></LI>
<LI><xtag-item1>DMUX=46</xtag-item1></LI>
<LI><xtag-item1>DQ=124</xtag-item1></LI>
<LI><xtag-item1>DX=60</xtag-item1></LI>
<LI><xtag-item1>SR=164</xtag-item1></LI>
</UL>
</TD>
<TD>
......@@ -746,23 +746,19 @@
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
<LI><xtag-cmdline>xst -intstyle ise -ifn &lt;ise_file&gt;</xtag-cmdline></LI>
<LI><xtag-cmdline>ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc &lt;fname&gt;.ucf -p xc6slx150t-fgg676-3 &lt;fname&gt;.ngc &lt;fname&gt;.ngd</xtag-cmdline></LI>
<LI><xtag-cmdline>map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o &lt;fname&gt;.ncd &lt;fname&gt;.ngd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>par -w -intstyle ise -ol high -mt off &lt;fname&gt;.ncd &lt;fname&gt;.ncd &lt;fname&gt;.pcf</xtag-cmdline></LI>
<LI><xtag-cmdline>trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml &lt;fname&gt;.twx &lt;fname&gt;.ncd -o &lt;fname&gt;.twr &lt;fname&gt;.pcf -ucf &lt;fname&gt;.ucf</xtag-cmdline></LI>
<LI><xtag-cmdline>bitgen -intstyle ise -f &lt;fname&gt;.ut &lt;fname&gt;.ncd</xtag-cmdline></LI>
</xtag-section></UL></TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>7</xtag-total-run-started></td>
<td><xtag-total-run-finished>7</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>edif2ngd</xtag-program-name></td>
<td><xtag-total-run-started>5</xtag-total-run-started></td>
<td><xtag-total-run-finished>5</xtag-total-run-finished></td>
<td><xtag-program-name>_impact</xtag-program-name></td>
<td><xtag-total-run-started>2</xtag-total-run-started></td>
<td><xtag-total-run-finished>0</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -770,7 +766,7 @@
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ibiswriter</xtag-program-name></td>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
......@@ -781,18 +777,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>22</xtag-total-run-started></td>
<td><xtag-total-run-finished>12</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
<td><xtag-total-exception>0</xtag-total-exception></td>
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
<tr>
<td><xtag-program-name>ngc2edif</xtag-program-name></td>
<td><xtag-total-run-started>12</xtag-total-run-started></td>
<td><xtag-total-run-finished>12</xtag-total-run-finished></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -801,8 +787,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>26</xtag-total-run-started></td>
<td><xtag-total-run-finished>26</xtag-total-run-finished></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -811,8 +797,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>12</xtag-total-run-started></td>
<td><xtag-total-run-finished>12</xtag-total-run-finished></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -821,8 +807,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>14</xtag-total-run-started></td>
<td><xtag-total-run-finished>14</xtag-total-run-finished></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -831,8 +817,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>32</xtag-total-run-started></td>
<td><xtag-total-run-finished>32</xtag-total-run-finished></td>
<td><xtag-total-run-started>1</xtag-total-run-started></td>
<td><xtag-total-run-finished>1</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
......@@ -840,35 +826,7 @@
<td><xtag-total-core-dump>0</xtag-total-core-dump></td>
</tr>
</xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISEHelpViewerData">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Help Statistics</B></TD></TR>
<TR ALIGN=LEFT><TD COLSPAN=2><xtag-group><B><xtag-group-name name="SearchFoundList">
Search words with results</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>input standard </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>lvds </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>verilog </xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group><TR VALIGN=TOP><TD COLSPAN=2><xtag-group><B><xtag-group-name name="OpenedHelpFiles">
Help files</xtag-group-name></B></TD></TR>
<TR><TD><xtag-search-item>/doc/usenglish/isehelp/cgn_c_df_verilog_flow.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/cgn_c_df_verilog_instantiation_example.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/cgn_p_add_ip_com_flow.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/dsm_c_design_summary_overview.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/gls_r_glossary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_constraints_entry_methods.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/ise_c_pin_assignment_pace.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/ism_r_verlang_expressions.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pn_db_npw_project_summary.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/pp_db_hdl_options_syn.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR><TR><TD><xtag-search-item>/doc/usenglish/isehelp/pp_p_process_io_pin_planning_pre_syn.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
<TD><xtag-search-item>/doc/usenglish/isehelp/sse_p_adding_attr.htm</xtag-search-item> ( <xtag-count-property>1</xtag-count-property> )</TD>
</TR></xtag-group></xtag-section></TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="Project Statistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=2><B>Project Statistics</B></TD></TR>
......@@ -892,7 +850,7 @@ Help files</xtag-group-name></B></TD></TR>
<TD><xtag-design-property-name>PROP_intProjectCreationTimestamp</xtag-design-property-name>=<xtag-design-property-value>2010-12-15T15:02:16</xtag-design-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWbtProjectID</xtag-design-property-name>=<xtag-design-property-value>F6031676C5FE434A8E9F8A1057A8E48F</xtag-design-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>5</xtag-process-property-value></TD>
<TD><xtag-process-property-name>PROP_intWbtProjectIteration</xtag-process-property-name>=<xtag-process-property-value>6</xtag-process-property-value></TD>
</TR><TR><TD><xtag-design-property-name>PROP_intWorkingDirLocWRTProjDir</xtag-design-property-name>=<xtag-design-property-value>Same</xtag-design-property-value></TD>
<TD><xtag-design-property-name>PROP_intWorkingDirUsed</xtag-design-property-name>=<xtag-design-property-value>No</xtag-design-property-value></TD>
......@@ -951,11 +909,11 @@ Help files</xtag-group-name></B></TD></TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_LUT6</xtag-preunisim-param-name>=<xtag-preunisim-param-value>307</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-preunisim-param-name>=<xtag-preunisim-param-value>186</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-preunisim-param-name>=<xtag-preunisim-param-value>18</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>151</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUF</xtag-preunisim-param-name>=<xtag-preunisim-param-value>152</xtag-preunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-preunisim-param-name>=<xtag-preunisim-param-value>3</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-preunisim-param-name>=<xtag-preunisim-param-value>34</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-preunisim-param-name>=<xtag-preunisim-param-value>33</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAM16X1D</xtag-preunisim-param-name>=<xtag-preunisim-param-value>2</xtag-preunisim-param-value></TD>
<TD><xtag-preunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-preunisim-param-name>=<xtag-preunisim-param-value>1</xtag-preunisim-param-value></TD>
</TR>
......@@ -996,11 +954,11 @@ Help files</xtag-group-name></B></TD></TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXCY</xtag-postunisim-param-name>=<xtag-postunisim-param-value>186</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_MUXF7</xtag-postunisim-param-name>=<xtag-postunisim-param-value>18</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>151</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUF</xtag-postunisim-param-name>=<xtag-postunisim-param-value>152</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
</TR>
<TR>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>66</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFT</xtag-postunisim-param-name>=<xtag-postunisim-param-value>65</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_OBUFTDS</xtag-postunisim-param-name>=<xtag-postunisim-param-value>2</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_RAM32M</xtag-postunisim-param-name>=<xtag-postunisim-param-value>1</xtag-postunisim-param-value></TD>
<TD><xtag-postunisim-param-name>NGDBUILD_NUM_SRLC16E</xtag-postunisim-param-name>=<xtag-postunisim-param-value>3</xtag-postunisim-param-value></TD>
......
trunk/firmware/XilinxISE/SystemFpga/webtalk.log
View file @ c3d17ad2
......@@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=F6031676C5FE434A8E9F8A1057A8E48F
ProjectIteration=5
ProjectIteration=6
WebTalk Summary
----------------
......@@ -13,4 +13,4 @@ INFO:WebTalk:2 - WebTalk is enabled.
INFO:WebTalk:8 - WebTalk Install setting is ON.
INFO:WebTalk:6 - WebTalk User setting is ON.
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-17T10:03:52. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
INFO:WebTalk:4 - C:/VFC_SVN/firmware/XilinxISE/SystemFpga/usage_statistics_webtalk.html WebTalk report has been successfully sent to Xilinx on 2010-12-17T11:13:36. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/12.3/ISE_DS/ISE/data/reports/webtalk_introduction.html
trunk/firmware/XilinxISE/SystemFpga/webtalk_pn.xml
View file @ c3d17ad2
......@@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Dec 17 10:03:02 2010">
<application name="pn" timeStamp="Fri Dec 17 11:13:08 2010">
<section name="Project Information" visible="false">
<property name="ProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="project"/>
<property name="ProjectIteration" value="5" type="project"/>
<property name="ProjectIteration" value="6" type="project"/>
<property name="ProjectFile" value="C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SystemFpga.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2010-12-15T15:02:16" type="project"/>
</section>
......@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2010-12-15T15:02:16" type="design"/>
<property name="PROP_intWbtProjectID" value="F6031676C5FE434A8E9F8A1057A8E48F" type="design"/>
<property name="PROP_intWbtProjectIteration" value="5" type="process"/>
<property name="PROP_intWbtProjectIteration" value="6" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
......
trunk/hdl/design/SystemFpga.v
View file @ c3d17ad2
......@@ -336,7 +336,7 @@ assign VmeP0BunchSelectOe_o= 1'b0;
assign Si57xSCl_ok= 1'b0;
assign Si57xSDa_io= 1'bz;
assign Si57xOe_o= 1'bz;
assign Si57xOe_o= 1'b1;
assign DdsF_ob2= 2'b0;
assign DdsProfile_ob3= 3'b0;
......
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