Commit cb70c6e4 authored by Andrea Boccardi's avatar Andrea Boccardi

corrected error in the ucf file

parent dccb0d8b
......@@ -12,13 +12,28 @@ Done.
Annotating constraints to design from ucf file "SFpga.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:137 - Constraint <NET "VcTcXo_ik" TNM_NET = VcTcXo_ik;>
[SFpga.ucf(701)]: No appropriate instances for the TNM constraint are driven
by "VcTcXo_ik".
WARNING:ConstraintSystem:137 - Constraint <NET "VmeSysClk_ik" TNM_NET =
VmeSysClk_ik;> [SFpga.ucf(702)]: No appropriate instances for the TNM
constraint are driven by "VmeSysClk_ik".
WARNING:ConstraintSystem:194 - The TNM 'VcTcXo_ik', does not directly or
indirectly drive any flip-flops, latches and/or RAMs and is not actively used
by any referencing constraint.
WARNING:ConstraintSystem:194 - The TNM 'VmeSysClk_ik', does not directly or
indirectly drive any flip-flops, latches and/or RAMs and is not actively used
by any referencing constraint.
Done...
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'N452' has no driver
WARNING:NgdBuild:452 - logical net 'N454' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TempIdDQ_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver
......@@ -28,7 +43,8 @@ WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgClk_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgCsi_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgRdWr_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgInit_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TempIdDQ_io' has no legal driver
WARNING:NgdBuild:452 - logical net 'N504' has no driver
WARNING:NgdBuild:452 - logical net 'N506' has no driver
Partition Implementation Status
-------------------------------
......@@ -39,9 +55,9 @@ Partition Implementation Status
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 14
Number of warnings: 18
Total memory usage is 155532 kilobytes
Total memory usage is 150888 kilobytes
Writing NGD file "SFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
......
......@@ -110,3 +110,80 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/SystemFpga/SFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc SFpga.ucf -p xc6slx150t-fgg676-3 SFpga.ngc SFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o SFpga_map.ncd SFpga.ngd SFpga.pcf
par -w -intstyle ise -ol high -mt off SFpga_map.ncd SFpga.ncd SFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SFpga.twx SFpga.ncd -o SFpga.twr SFpga.pcf -ucf SFpga.ucf
bitgen -intstyle ise -f SFpga.ut SFpga.ncd
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 17:36:28 2010
Thu Jan 06 13:57:44 2011
# NOTE: This file is designed to be imported into a spreadsheet program
......@@ -543,7 +543,7 @@ R1||IOBS|IO_L44N_GCLK20_M3A6_3|UNUSED||3|||||||||
R2||IOBM|IO_L44P_GCLK21_M3A5_3|UNUSED||3|||||||||
R3|FpLed_onb8<2>|IOB|IO_L52N_M3A9_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R4|FpLed_onb8<1>|IOB|IO_L52P_M3A8_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R5|FpLed_onb8<4>|IOB|IO_L50N_M3BA2_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R5|FpLed_onb8<4>|IOB|IO_L50N_M3BA2_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R6|SysAppClk_ik|IOB|IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
R7|SysAppClk_ok|IOB|IO_L43P_GCLK23_M3RASN_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
R8|ManualAddress_ib5<0>|IOB|IO_L45P_M3A3_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
......@@ -593,7 +593,7 @@ T25|||VCCO_1|||1|||||1.50||||
T26||IOBS|IO_L44N_A2_M1DQ7_1|UNUSED||1|||||||||
U1|Fmc2PrsntM2C_in|IOB|IO_L40N_M3DQ7_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U2|Fmc2PGC2M_in|IOB|IO_L40P_M3DQ6_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U3|FpLed_onb8<5>|IOB|IO_L10N_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U3|FpLed_onb8<5>|IOB|IO_L10N_3|OUTPUT|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U4|FpLed_onb8<6>|IOB|IO_L10P_3|TRISTATE|LVCMOS25*|3|12|||||LOCATED|NO|NONE|
U5|AFpgaProgD_iob8<4>|IOB|IO_L46P_M3CLK_3|INPUT|LVCMOS25*|3||||NONE||LOCATED|NO|NONE|
U6|||VCCAUX||||||||2.5||||
......
verilog work "../../../hdl/design/VmeInterfaceWB.v"
verilog work "../../../hdl/design/VmeToWishBone.v"
verilog work "../../../hdl/design/SpiMasterWB.v"
verilog work "../../../hdl/design/Slv2SerWB.v"
verilog work "../../../hdl/design/Monostable.v"
......
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="5.091" best="4.909" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.482" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 100 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 100 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="7.730" best="2.270" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="7.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VmeSysClk_ik = PERIOD TIMEGRP &quot;VmeSysClk_ik&quot; 40 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="22.874" best="2.126" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.521" units="ns" errors="0" score="0"/><twConstData type="MINPERIOD" slack="22.500" best="2.500" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_VcTcXo_ik = PERIOD TIMEGRP &quot;VcTcXo_ik&quot; 25 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="27.265" best="12.735" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.413" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ikn = PERIOD TIMEGRP &quot;Si57x_ikn&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="0.331" best="8.002" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.374" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="3.723" best="4.610" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.482" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_Si57x_ik = PERIOD TIMEGRP &quot;Si57x_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="5.833" best="2.500" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -699,10 +699,8 @@ NET "Si57x_ik" TNM_NET = "Si57x_ik";
NET "SysAppClk_ik" TNM_NET = SysAppClk_ik;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/20
NET "VcTcXo_ik" TNM_NET = VcTcXo_ik;
TIMESPEC TS_VcTcXo_ik = PERIOD "VcTcXo_ik" 25 MHz HIGH 50%;
NET "VmeSysClk_ik" TNM_NET = VmeSysClk_ik;
TIMESPEC TS_VmeSysClk_ik = PERIOD "VmeSysClk_ik" 40 MHz HIGH 50%;
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 100 MHz HIGH 50%;
TIMESPEC TS_Si57x_ik = PERIOD "Si57x_ik" 120 MHz HIGH 50%;
NET "Si57x_ikn" TNM_NET = Si57x_ikn;
TIMESPEC TS_Si57x_ikn = PERIOD "Si57x_ikn" 100 MHz HIGH 50%;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 100 MHz HIGH 50%;
TIMESPEC TS_Si57x_ikn = PERIOD "Si57x_ikn" 120 MHz HIGH 50%;
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50%;
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 17:36:28 2010
Thu Jan 06 13:57:45 2011
All signals are completely routed.
......@@ -44,12 +44,12 @@ WARNING:ParHelpers:361 - There are 50 loadless signals in this design. This desi
Switch_ib2<0>_IBUF
Switch_ib2<1>_IBUF
TempIdDQ_io_IBUF
VcTcXo_ik_IBUF
VmeAm_ib6<1>_IBUF
VmeAm_ib6<2>_IBUF
VmeDs_inb2<1>_IBUF
VmeDs_inb2<2>_IBUF
VmeP0LvdsBunchClkIn_i_IBUF
VmeP0LvdsTClkIn_i_IBUF
VmeSysClk_ik_IBUF
VmeTck_i_IBUF
VmeTdi_i_IBUF
VmeTms_i_IBUF
......
......@@ -10,23 +10,23 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Mon Dec 20 17:35:13 2010
Mapped Date : Thu Jan 06 13:56:29 2011
Design Summary
--------------
Number of errors: 0
Number of warnings: 86
Number of warnings: 85
Slice Logic Utilization:
Number of Slice Registers: 834 out of 184,304 1%
Number used as Flip Flops: 834
Number of Slice Registers: 784 out of 184,304 1%
Number used as Flip Flops: 784
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 965 out of 92,152 1%
Number used as logic: 934 out of 92,152 1%
Number using O6 output only: 579
Number using O5 output only: 187
Number using O5 and O6: 168
Number of Slice LUTs: 878 out of 92,152 1%
Number used as logic: 851 out of 92,152 1%
Number using O6 output only: 622
Number using O5 output only: 83
Number using O5 and O6: 146
Number used as ROM: 0
Number used as Memory: 14 out of 21,680 1%
Number used as Dual Port RAM: 8
......@@ -35,21 +35,21 @@ Slice Logic Utilization:
Number using O5 and O6: 4
Number used as Single Port RAM: 0
Number used as Shift Register: 6
Number using O6 output only: 6
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 17
Number with same-slice register load: 7
Number with same-slice carry load: 10
Number using O5 and O6: 2
Number used exclusively as route-thrus: 13
Number with same-slice register load: 8
Number with same-slice carry load: 5
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 383 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,137
Number with an unused Flip Flop: 369 out of 1,137 32%
Number with an unused LUT: 172 out of 1,137 15%
Number of fully used LUT-FF pairs: 596 out of 1,137 52%
Number of unique control sets: 34
Number of occupied Slices: 353 out of 23,038 1%
Number of LUT Flip Flop pairs used: 1,041
Number with an unused Flip Flop: 330 out of 1,041 31%
Number with an unused LUT: 163 out of 1,041 15%
Number of fully used LUT-FF pairs: 548 out of 1,041 52%
Number of unique control sets: 26
Number of slice register sites lost
to control set restrictions: 76 out of 184,304 1%
......@@ -70,8 +70,8 @@ Specific Feature Utilization:
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 4 out of 16 25%
Number used as BUFGs: 4
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
......@@ -92,11 +92,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.00
Average Fanout of Non-Clock Nets: 3.41
Peak Memory Usage: 629 MB
Total REAL time to MAP completion: 38 secs
Total CPU time to MAP completion: 36 secs
Peak Memory Usage: 627 MB
Total REAL time to MAP completion: 41 secs
Total CPU time to MAP completion: 41 secs
Table of Contents
-----------------
......@@ -187,25 +187,10 @@ WARNING:MapLib:701 - Signal AFpgaProgProgram_o connected to top level port
AFpgaProgProgram_o has been removed.
WARNING:MapLib:701 - Signal VAdjInhibit_ozn connected to top level port
VAdjInhibit_ozn has been removed.
WARNING:Place:1109 - A clock IOB / BUFGMUX clock component pair have been found
that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
IOB component <VmeSysClk_ik> is placed at site <PAD550>. The corresponding
BUFG component <VmeSysClk_ik_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y10>.
There is only a select set of IOBs that can use the fast path to the Clocker
buffer, and they are not being used. You may want to analyze why this problem
exists and correct it. This is normally an ERROR but the
CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <VmeSysClk_ik.PAD>
allowing your design to continue. This constraint disables all clock placer
rules related to the specified COMP.PIN. The use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended
that this error condition be corrected in the design.
WARNING:PhysDesignRules:372 - Gated clock. Clock net i_Core/WriteCycle is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeDs_inb2<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
i_Core/i_VmeInterface/Stb_oq is sourced by a combinatorial pin. This is not
good design practice. Use the CE pin to control the loading of data into the
flip-flop.
WARNING:PhysDesignRules:367 - The signal <DdsRamSwpOvr_i_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <PcbRev_ib8<0>_IBUF> is incomplete. The
......@@ -252,6 +237,8 @@ WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<1>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeAm_ib6<2>_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VmeSysClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <Sfp2TxFault_i_IBUF> is incomplete. The
......@@ -282,6 +269,8 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsPdClk_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <VcTcXo_ik_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <WRLoS_i_IBUF> is incomplete. The
signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <DdsSyncSmpErr_i_IBUF> is incomplete.
......@@ -306,14 +295,14 @@ WARNING:PhysDesignRules:367 - The signal
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network N452 has no load.
INFO:LIT:243 - Logical network N504 has no load.
INFO:LIT:395 - The above info message is repeated 54 more times for the
following (max. 5 shown):
N454,
N506,
VmeAm_ib6<2>_IBUF,
VmeAm_ib6<1>_IBUF,
VmeDs_inb2<2>_IBUF,
VmeDs_inb2<1>_IBUF
Switch_ib2<1>_IBUF,
Switch_ib2<0>_IBUF
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
......@@ -323,6 +312,8 @@ INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 331 IOs, 329 are locked
......
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Mon Dec 20 17:35:12 2010">
<application stringID="NgdBuild" timeStamp="Thu Jan 06 13:56:28 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -61,75 +61,75 @@
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="14"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="18"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="195"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="102"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="165"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="104"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="342"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="170"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="310"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="76"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="77"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_IOBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="197"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="168"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="116"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="298"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="220"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="86"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="211"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="85"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="123"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="284"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="128"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="154"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="30"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM16X1D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="216"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="121"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="195"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="102"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="165"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="104"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDPE" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="135"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="342"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="170"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="310"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="26"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="33"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDSE" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="157"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="158"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFGDS" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="197"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="168"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="130"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="116"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="148"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="298"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="220"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="28"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="152"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="86"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="211"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="149"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="85"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="123"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="284"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="128"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF7" value="24"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="154"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFDS" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="64"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="62"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUFTDS" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAM32M" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_SRLC16E" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_TS_TIMESPEC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="216"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="121"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
......
#Release 12.3 - par M.70d (nt64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Mon Dec 20 17:36:28 2010
#Thu Jan 06 13:57:44 2011
#
## NOTE: This file is designed to be imported into a spreadsheet program
......@@ -543,7 +543,7 @@ R1,,IOBS,IO_L44N_GCLK20_M3A6_3,UNUSED,,3,,,,,,,,,
R2,,IOBM,IO_L44P_GCLK21_M3A5_3,UNUSED,,3,,,,,,,,,
R3,FpLed_onb8<2>,IOB,IO_L52N_M3A9_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R4,FpLed_onb8<1>,IOB,IO_L52P_M3A8_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R5,FpLed_onb8<4>,IOB,IO_L50N_M3BA2_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R5,FpLed_onb8<4>,IOB,IO_L50N_M3BA2_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R6,SysAppClk_ik,IOB,IO_L43N_GCLK22_IRDY2_M3CASN_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
R7,SysAppClk_ok,IOB,IO_L43P_GCLK23_M3RASN_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
R8,ManualAddress_ib5<0>,IOB,IO_L45P_M3A3_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
......@@ -593,7 +593,7 @@ T25,,,VCCO_1,,,1,,,,,1.50,,,,
T26,,IOBS,IO_L44N_A2_M1DQ7_1,UNUSED,,1,,,,,,,,,
U1,Fmc2PrsntM2C_in,IOB,IO_L40N_M3DQ7_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U2,Fmc2PGC2M_in,IOB,IO_L40P_M3DQ6_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U3,FpLed_onb8<5>,IOB,IO_L10N_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U3,FpLed_onb8<5>,IOB,IO_L10N_3,OUTPUT,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U4,FpLed_onb8<6>,IOB,IO_L10P_3,TRISTATE,LVCMOS25*,3,12,,,,,LOCATED,NO,NONE,
U5,AFpgaProgD_iob8<4>,IOB,IO_L46P_M3CLK_3,INPUT,LVCMOS25*,3,,,,NONE,,LOCATED,NO,NONE,
U6,,,VCCAUX,,,,,,,,2.5,,,,
......
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Mon Dec 20 17:36:28 2010
Thu Jan 06 13:57:44 2011
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......@@ -544,7 +544,7 @@ Pinout by Pin Number:
|R2 | |IOBM |IO_L44P_GCLK21_M3A5_3 |UNUSED | |3 | | | | | | | | |
|R3 |FpLed_onb8<2> |IOB |IO_L52N_M3A9_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R4 |FpLed_onb8<1> |IOB |IO_L52P_M3A8_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R5 |FpLed_onb8<4> |IOB |IO_L50N_M3BA2_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R5 |FpLed_onb8<4> |IOB |IO_L50N_M3BA2_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R6 |SysAppClk_ik |IOB |IO_L43N_GCLK22_IRDY2_M3CASN_3|INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|R7 |SysAppClk_ok |IOB |IO_L43P_GCLK23_M3RASN_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|R8 |ManualAddress_ib5<0> |IOB |IO_L45P_M3A3_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
......@@ -594,7 +594,7 @@ Pinout by Pin Number:
|T26 | |IOBS |IO_L44N_A2_M1DQ7_1 |UNUSED | |1 | | | | | | | | |
|U1 |Fmc2PrsntM2C_in |IOB |IO_L40N_M3DQ7_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|U2 |Fmc2PGC2M_in |IOB |IO_L40P_M3DQ6_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|U3 |FpLed_onb8<5> |IOB |IO_L10N_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|U3 |FpLed_onb8<5> |IOB |IO_L10N_3 |OUTPUT |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|U4 |FpLed_onb8<6> |IOB |IO_L10P_3 |TRISTATE |LVCMOS25* |3 |12 | | | | |LOCATED |NO |NONE |
|U5 |AFpgaProgD_iob8<4> |IOB |IO_L46P_M3CLK_3 |INPUT |LVCMOS25* |3 | | | |NONE | |LOCATED |NO |NONE |
|U6 | | |VCCAUX | | | | | | | |2.5 | | | |
......
......@@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="27">
<DesignSummary rev="51">
<CmdHistory>
</CmdHistory>
</DesignSummary>
......@@ -68,6 +68,7 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="sfpga.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="sfpga.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="sfpga.bit" xil_pn:subbranch="FPGAConfiguration"/>
......@@ -110,7 +111,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292862183" xil_pn:in_ck="2606969364006439169" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1292862165">
<transform xil_pn:end_ts="1294318567" xil_pn:in_ck="-394197636941444327" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2192959706989509064" xil_pn:start_ts="1294318548">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -128,11 +129,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1292862908" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1292862908">
<transform xil_pn:end_ts="1294306442" xil_pn:in_ck="119863998498621" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4066557905353815859" xil_pn:start_ts="1294306442">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1292862913" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1292862908">
<transform xil_pn:end_ts="1294318589" xil_pn:in_ck="6749615496043861780" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="5907793610130957210" xil_pn:start_ts="1294318567">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -142,12 +143,10 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292862953" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1292862913">
<transform xil_pn:end_ts="1294318632" xil_pn:in_ck="6749661907528263733" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1294318589">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SFpga.pcf"/>
<outfile xil_pn:name="SFpga_map.map"/>
<outfile xil_pn:name="SFpga_map.mrp"/>
......@@ -158,7 +157,7 @@
<outfile xil_pn:name="SFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292863002" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1292862953">
<transform xil_pn:end_ts="1294318678" xil_pn:in_ck="-7894903822868506770" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1294318632">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -173,7 +172,7 @@
<outfile xil_pn:name="SFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1292863036" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1292863002">
<transform xil_pn:end_ts="1294318722" xil_pn:in_ck="119863998490996" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="1639941319497468386" xil_pn:start_ts="1294318678">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -189,7 +188,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1292864265" xil_pn:in_ck="166232864437118" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1292864264">