Commit ddc0466d authored by Andrea Boccardi's avatar Andrea Boccardi

nothing, just sync

parent 58639a1a
......@@ -18,12 +18,7 @@ Done...
Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'FpGpIo_iob4<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<2>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgClk_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgCsi_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgRdWr_io' has no legal driver
......@@ -38,12 +33,12 @@ Partition Implementation Status
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 12
Number of warnings: 7
Total memory usage is 149264 kilobytes
Total memory usage is 148820 kilobytes
Writing NGD file "ApplicationFpga.ngd" ...
Total REAL time to NGDBUILD completion: 2 sec
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "ApplicationFpga.bld"...
......@@ -84,3 +84,9 @@ map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
xst -intstyle ise -ifn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.xst" -ofn "C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
map -intstyle ise -p xc6slx150t-fgg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o ApplicationFpga_map.ncd ApplicationFpga.ngd ApplicationFpga.pcf
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd ApplicationFpga.ncd ApplicationFpga.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ApplicationFpga.twx ApplicationFpga.ncd -o ApplicationFpga.twr ApplicationFpga.pcf -ucf ApplicationFpga.ucf
bitgen -intstyle ise -f ApplicationFpga.ut ApplicationFpga.ncd
......@@ -107,7 +107,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1294825814" xil_pn:in_ck="5192584784990505676" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="6138376139572991401" xil_pn:start_ts="1294825805">
<transform xil_pn:end_ts="1296546540" xil_pn:in_ck="5192584784990505676" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="6138376139572991401" xil_pn:start_ts="1296546531">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -129,7 +129,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1294825817" xil_pn:in_ck="-2234839937575114378" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1018860157679998437" xil_pn:start_ts="1294825814">
<transform xil_pn:end_ts="1296546544" xil_pn:in_ck="-2234839937575114378" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1018860157679998437" xil_pn:start_ts="1296546540">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -139,9 +139,11 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1294825843" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1294825817">
<transform xil_pn:end_ts="1296546573" xil_pn:in_ck="-7949697330576238633" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-510487083596868273" xil_pn:start_ts="1296546544">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="ApplicationFpga.pcf"/>
<outfile xil_pn:name="ApplicationFpga_map.map"/>
<outfile xil_pn:name="ApplicationFpga_map.mrp"/>
......@@ -152,7 +154,7 @@
<outfile xil_pn:name="ApplicationFpga_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1294825881" xil_pn:in_ck="4718546783015930448" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1294825843">
<transform xil_pn:end_ts="1296546613" xil_pn:in_ck="4718546783015930448" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3717135755049403020" xil_pn:start_ts="1296546573">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -167,7 +169,7 @@
<outfile xil_pn:name="ApplicationFpga_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1294825923" xil_pn:in_ck="-4700563312770461419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-774614059244361160" xil_pn:start_ts="1294825881">
<transform xil_pn:end_ts="1296546658" xil_pn:in_ck="-4700563312770461419" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-774614059244361160" xil_pn:start_ts="1296546613">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -189,13 +191,9 @@
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1294824431" xil_pn:in_ck="4850548760538546975" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1294824429">
<transform xil_pn:end_ts="1296632982" xil_pn:in_ck="4850548760538546975" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1296632980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="applicationfpga.isc"/>
</transform>
<transform xil_pn:end_ts="1294762411" xil_pn:in_ck="4850548760538546975" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="-7047989797201823252" xil_pn:start_ts="1294762409">
......@@ -204,7 +202,7 @@
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1294825881" xil_pn:in_ck="8541715597190098387" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1294825871">
<transform xil_pn:end_ts="1296546613" xil_pn:in_ck="8541715597190098387" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1296546603">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ApplicationFpga.twr"/>
......
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Wed Jan 12 10:51:09 2011
Tue Feb 01 08:50:01 2011
# NOTE: This file is designed to be imported into a spreadsheet program
......@@ -145,7 +145,7 @@ AD19|||GND||||||||||||
AD20||IPAD|MGTRXN1_267|UNUSED|||||||||||
AD21|||GND||||||||||||
AD22|AFpgaProgM_iob2<1>|IOB|IO_L13P_M1_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
AD23|AFpgaProgD_iob8<0>|IOB|IO_L3P_D0_DIN_MISO_MISO1_2|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
AD23|AFpgaProgD_iob8<0>|IOB|IO_L3P_D0_DIN_MISO_MISO1_2|OUTPUT|LVCMOS25*|2|12|||||LOCATED|NO|NONE|
AD24|Sram1Data_b36<17>|IOB|IO_L48P_HDC_M1DQ8_1|BIDIR|LVCMOS25*|1|12|||NONE||LOCATED|NO|NONE|
AD25|||VCCO_1|||1|||||2.50||||
AD26|Sram1Bws_nb4<0>|IOB|IO_L48N_M1DQ9_1|OUTPUT|LVCMOS25*|1|12|||||LOCATED|NO|NONE|
......
Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Wed Jan 12 10:50:44 2011
PCBE13225:: Tue Feb 01 08:49:34 2011
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd
ApplicationFpga.ncd ApplicationFpga.pcf
......@@ -27,9 +27,9 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 213 out of 92,152 1%
Number used as logic: 160 out of 92,152 1%
Number using O6 output only: 123
Number of Slice LUTs: 210 out of 92,152 1%
Number used as logic: 159 out of 92,152 1%
Number using O6 output only: 122
Number using O5 output only: 14
Number using O5 and O6: 23
Number used as ROM: 0
......@@ -40,17 +40,17 @@ Slice Logic Utilization:
Number using O6 output only: 7
Number using O5 output only: 0
Number using O5 and O6: 16
Number used exclusively as route-thrus: 30
Number with same-slice register load: 29
Number used exclusively as route-thrus: 28
Number with same-slice register load: 27
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 131 out of 23,038 1%
Number of LUT Flip Flop pairs used: 464
Number with an unused Flip Flop: 20 out of 464 4%
Number with an unused LUT: 251 out of 464 54%
Number of fully used LUT-FF pairs: 193 out of 464 41%
Number of occupied Slices: 134 out of 23,038 1%
Number of LUT Flip Flop pairs used: 468
Number with an unused Flip Flop: 22 out of 468 4%
Number with an unused LUT: 258 out of 468 55%
Number of fully used LUT-FF pairs: 188 out of 468 40%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
......@@ -95,47 +95,42 @@ Specific Feature Utilization:
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 9 secs
Finished initial Timing Analysis. REAL time: 9 secs
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<2>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<3>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgCsi_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal FpGpIo_iob4<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgInit_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 1682 unrouted; REAL time: 11 secs
Phase 1 : 1683 unrouted; REAL time: 11 secs
Phase 2 : 1406 unrouted; REAL time: 14 secs
Phase 2 : 1403 unrouted; REAL time: 15 secs
Phase 3 : 375 unrouted; REAL time: 16 secs
Phase 3 : 430 unrouted; REAL time: 18 secs
Phase 4 : 375 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 22 secs
Phase 4 : 430 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 24 secs
Updating file: ApplicationFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 23 secs
Total REAL time to Router completion: 23 secs
Total CPU time to Router completion: 23 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Total REAL time to Router completion: 25 secs
Total CPU time to Router completion: 24 secs
Partition Implementation Status
-------------------------------
......@@ -153,8 +148,8 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|FpGpIo_iob4_4_OBUF_B | | | | | |
| UFG | BUFGMUX_X2Y1| No | 123 | 0.196 | 1.696 |
|SysAppClk_ik_IBUF_BU | | | | | |
| FG | BUFGMUX_X2Y1| No | 124 | 0.196 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -171,8 +166,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 2.883ns| 5.450ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.348ns| | 0| 0
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 1.876ns| 6.457ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.375ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -183,19 +178,19 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 25 secs
Total CPU time to PAR completion: 25 secs
Total REAL time to PAR completion: 27 secs
Total CPU time to PAR completion: 26 secs
Peak Memory Usage: 525 MB
Peak Memory Usage: 526 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 14
Number of warning messages: 9
Number of info messages: 0
Writing design to file ApplicationFpga.ncd
......
//! **************************************************************************
// Written by: Map M.70d on Wed Jan 12 10:50:41 2011
// Written by: Map M.70d on Tue Feb 01 08:49:31 2011
//! **************************************************************************
SCHEMATIC START;
......@@ -436,7 +436,7 @@ TIMEGRP SysAppClk_ik = BEL "Rst_rq" BEL "i_Sram2Controller/Dat_ob32_31" BEL
"i_AddressDecoderWB/StbDebugRegs_o" BEL
"i_AddressDecoderWB/StbSram2Controller_o" BEL
"i_AddressDecoderWB/StbSram1Controller_o" BEL
"i_Ser2MstWB/Adr_ob21_19_1" BEL "FpGpIo_iob4_4_OBUF_BUFG" BEL
"i_Ser2MstWB/Adr_ob21_19_1" BEL "SysAppClk_ik_IBUF_BUFG" BEL
"i_Sram2Controller/Mshreg_DatI_db32_0_94" BEL
"i_Sram2Controller/DatI_db32_0_94" BEL
"i_Sram2Controller/Mshreg_ReadCycle_d_2" BEL
......@@ -528,7 +528,7 @@ TIMEGRP SysAppClk_ik = BEL "Rst_rq" BEL "i_Sram2Controller/Dat_ob32_31" BEL
"i_Ser2MstWB/Rst_xb3_2_shift25" BEL "i_Ser2MstWB/Rst_xb3_2_shift26"
BEL "i_Ser2MstWB/Rst_xb3_2_shift27" BEL
"i_Ser2MstWB/Rst_xb3_2_shift28" BEL "i_Ser2MstWB/AckI_d31_30" BEL
"FpGpIo_iob4<4>" BEL "SysAppClk_ok" BEL "Sram1Clk_k" BEL "Sram2Clk_k";
"SysAppClk_ok" BEL "Sram1Clk_k" BEL "Sram2Clk_k";
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppClk_ik" 120 MHz HIGH 50%;
SCHEMATIC END;
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="2.883" best="5.450" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.348" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_SysAppClk_ik = PERIOD TIMEGRP &quot;SysAppClk_ik&quot; 120 MHz HIGH 50%</twConstName><twConstData type="SETUP" slack="1.876" best="6.457" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.375" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="2">0</twUnmetConstCnt></twSumRpt></twBody></twReport>
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Wed Jan 12 10:51:09 2011
Tue Feb 01 08:50:01 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 12 loadless signals in this design. This design will cause Bitgen to issue DRC
WARNING:ParHelpers:361 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
AFpgaProgClk_io_IBUF
AFpgaProgCsi_io_IBUF
AFpgaProgD_iob8<0>_IBUF
AFpgaProgD_iob8<1>_IBUF
AFpgaProgD_iob8<2>_IBUF
AFpgaProgD_iob8<3>_IBUF
AFpgaProgD_iob8<6>_IBUF
AFpgaProgInit_io_IBUF
AFpgaProgM_iob2<0>_IBUF
AFpgaProgM_iob2<1>_IBUF
AFpgaProgRdWr_io_IBUF
FpGpIo_iob4<1>_IBUF
......@@ -11,7 +11,7 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Wed Jan 12 10:50:18 2011
Mapped Date : Tue Feb 01 08:49:05 2011
Mapping design into LUTs...
Running directed packing...
......@@ -20,54 +20,54 @@ Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 10 secs
Total REAL time at the beginning of Placer: 12 secs
Total CPU time at the beginning of Placer: 10 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:5f7405cc) REAL time: 14 secs
Phase 1.1 Initial Placement Analysis (Checksum:5f73fddf) REAL time: 16 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:5f7405cc) REAL time: 14 secs
Phase 2.7 Design Feasibility Check (Checksum:5f73fddf) REAL time: 16 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:5f7405cc) REAL time: 14 secs
Phase 3.31 Local Placement Optimization (Checksum:5f73fddf) REAL time: 16 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:af4a5b5c) REAL time: 18 secs
(Checksum:af4a536f) REAL time: 21 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:af4a5b5c) REAL time: 18 secs
Phase 5.36 Local Placement Optimization (Checksum:af4a536f) REAL time: 21 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:af4a5b5c) REAL time: 18 secs
Phase 6.30 Global Clock Region Assignment (Checksum:af4a536f) REAL time: 21 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:af4a5b5c) REAL time: 19 secs
Phase 7.3 Local Placement Optimization (Checksum:af4a536f) REAL time: 21 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:af4a5b5c) REAL time: 19 secs
Phase 8.5 Local Placement Optimization (Checksum:af4a536f) REAL time: 21 secs
Phase 9.8 Global Placement
.....
.......................
..........
Phase 9.8 Global Placement (Checksum:bbda77c7) REAL time: 20 secs
.......
................
.......
Phase 9.8 Global Placement (Checksum:8c1b842) REAL time: 22 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:bbda77c7) REAL time: 20 secs
Phase 10.5 Local Placement Optimization (Checksum:8c1b842) REAL time: 23 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:c7a717ae) REAL time: 21 secs
Phase 11.18 Placement Optimization (Checksum:cf3bcc6e) REAL time: 23 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:c7a717ae) REAL time: 21 secs
Phase 12.5 Local Placement Optimization (Checksum:cf3bcc6e) REAL time: 23 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:fdaf00cd) REAL time: 21 secs
Phase 13.34 Placement Validation (Checksum:a98cb8bf) REAL time: 23 secs
Total REAL time to Placer completion: 23 secs
Total REAL time to Placer completion: 25 secs
Total CPU time to Placer completion: 23 secs
Running post-placement packing...
Writing output files...
......@@ -75,20 +75,10 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <FpGpIo_iob4<1>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
......@@ -101,16 +91,16 @@ Design Summary
Design Summary:
Number of errors: 0
Number of warnings: 12
Number of warnings: 7
Slice Logic Utilization:
Number of Slice Registers: 496 out of 184,304 1%
Number used as Flip Flops: 496
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 213 out of 92,152 1%
Number used as logic: 160 out of 92,152 1%
Number using O6 output only: 123
Number of Slice LUTs: 210 out of 92,152 1%
Number used as logic: 159 out of 92,152 1%
Number using O6 output only: 122
Number using O5 output only: 14
Number using O5 and O6: 23
Number used as ROM: 0
......@@ -121,17 +111,17 @@ Slice Logic Utilization:
Number using O6 output only: 7
Number using O5 output only: 0
Number using O5 and O6: 16
Number used exclusively as route-thrus: 30
Number with same-slice register load: 29
Number used exclusively as route-thrus: 28
Number with same-slice register load: 27
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 131 out of 23,038 1%
Number of LUT Flip Flop pairs used: 464
Number with an unused Flip Flop: 20 out of 464 4%
Number with an unused LUT: 251 out of 464 54%
Number of fully used LUT-FF pairs: 193 out of 464 41%
Number of occupied Slices: 134 out of 23,038 1%
Number of LUT Flip Flop pairs used: 468
Number with an unused Flip Flop: 22 out of 468 4%
Number with an unused LUT: 258 out of 468 55%
Number of fully used LUT-FF pairs: 188 out of 468 40%
Number of unique control sets: 12
Number of slice register sites lost
to control set restrictions: 17 out of 184,304 1%
......@@ -173,11 +163,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.35
Average Fanout of Non-Clock Nets: 2.36
Peak Memory Usage: 584 MB
Total REAL time to MAP completion: 24 secs
Total CPU time to MAP completion: 23 secs
Peak Memory Usage: 585 MB
Total REAL time to MAP completion: 26 secs
Total CPU time to MAP completion: 24 secs
Mapping completed.
See MAP report file "ApplicationFpga_map.mrp" for details.
......@@ -11,21 +11,21 @@ Target Device : xc6slx150t
Target Package : fgg676
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.52 $
Mapped Date : Wed Jan 12 10:50:18 2011
Mapped Date : Tue Feb 01 08:49:05 2011
Design Summary
--------------
Number of errors: 0
Number of warnings: 12
Number of warnings: 7
Slice Logic Utilization:
Number of Slice Registers: 496 out of 184,304 1%
Number used as Flip Flops: 496
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 213 out of 92,152 1%
Number used as logic: 160 out of 92,152 1%
Number using O6 output only: 123
Number of Slice LUTs: 210 out of 92,152 1%
Number used as logic: 159 out of 92,152 1%
Number using O6 output only: 122
Number using O5 output only: 14
Number using O5 and O6: 23
Number used as ROM: 0
......@@ -36,17 +36,17 @@ Slice Logic Utilization:
Number using O6 output only: 7
Number using O5 output only: 0
Number using O5 and O6: 16
Number used exclusively as route-thrus: 30
Number with same-slice register load: 29
Number used exclusively as route-thrus: 28
Number with same-slice register load: 27
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 131 out of 23,038 1%
Number of LUT Flip Flop pairs used: 464
Number with an unused Flip Flop: 20 out of 464 4%
Number with an unused LUT: 251 out of 464 54%
Number of fully used LUT-FF pairs: 193 out of 464 41%
Number of occupied Slices: 134 out of 23,038 1%
Number of LUT Flip Flop pairs used: 468
Number with an unused Flip Flop: 22 out of 468 4%
Number with an unused LUT: 258 out of 468 55%
Number of fully used LUT-FF pairs: 188 out of 468 40%
Number of unique control sets: 12
Number of slice register sites lost
to control set restrictions: 17 out of 184,304 1%
......@@ -88,11 +88,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.35
Average Fanout of Non-Clock Nets: 2.36
Peak Memory Usage: 584 MB
Total REAL time to MAP completion: 24 secs
Total CPU time to MAP completion: 23 secs
Peak Memory Usage: 585 MB
Total REAL time to MAP completion: 26 secs
Total CPU time to MAP completion: 24 secs
Table of Contents
-----------------
......@@ -119,20 +119,10 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgClk_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgRdWr_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<0>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<1>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<2>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<3>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgD_iob8<6>_IBUF> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgCsi_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <FpGpIo_iob4<1>_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgInit_io_IBUF> is incomplete.
The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<0>_IBUF> is
......@@ -143,13 +133,13 @@ WARNING:PhysDesignRules:367 - The signal <AFpgaProgM_iob2<1>_IBUF> is
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network AFpgaProgM_iob2<1>_IBUF has no load.
INFO:LIT:395 - The above info message is repeated 11 more times for the
following (max. 5 shown):
INFO:LIT:395 - The above info message is repeated 6 more times for the following
(max. 5 shown):
AFpgaProgM_iob2<0>_IBUF,
FpGpIo_iob4<1>_IBUF,
AFpgaProgD_iob8<6>_IBUF,
AFpgaProgD_iob8<3>_IBUF,
AFpgaProgD_iob8<2>_IBUF
AFpgaProgClk_io_IBUF,
AFpgaProgCsi_io_IBUF,
AFpgaProgRdWr_io_IBUF
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
......@@ -187,7 +177,7 @@ Section 6 - IOB Properties
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| AFpgaProgClk_io | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgCsi_io | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| AFpgaProgD_iob8<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| AFpgaProgD_iob8<3> | IOB | INPUT | LVCMOS25 | | | | | | |
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Wed Jan 12 10:50:42 2011">
<application stringID="Map" timeStamp="Tue Feb 01 08:49:32 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -70,9 +70,9 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="184">
<item AVAILABLE="92152" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="183">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="14"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="123"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="122"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="23"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
......@@ -115,10 +115,10 @@
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="12"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="598072"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="24 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="23 secs "/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="7"/>