Commit e10d9b2b authored by Andrea Boccardi's avatar Andrea Boccardi

updated the paths for the simulation

parent 8d2947ac
mv simplesim.o simplesim.o.bkp
iverilog -stb_VFC -fmodulist -osimplesim.o
./simplesim.o >& /dev/null &
(cd ../sw/src; python vmet.py)
(cd ../software/src; python vmet.py)
#gtkwave simout.vcd >& /dev/null &
# Components' models
../verilog/components/ivt3205c25mhz.v
../verilog/components/sn74vmeh22501.v
../hdl/components/ivt3205c25mhz.v
../hdl/components/sn74vmeh22501.v
# Components with missing models
../verilog/components/blackboxes/si57x.v
../hdl/components/blackboxes/si57x.v
# System FPGA's modules
../verilog/design/SystemFpga.v
../verilog/design/CsGenerator.v
../verilog/design/Generic4Regs.v
../verilog/design/Monostable.v
../verilog/design/VmeDoutArbiter.v
../verilog/design/Debouncer.v
../verilog/design/InterruptManager.v
../verilog/design/VmeInterface.v
../hdl/design/SystemFpga.v
../hdl/design/CsGenerator.v
../hdl/design/Generic4Regs.v
../hdl/design/Monostable.v
../hdl/design/VmeDoutArbiter.v
../hdl/design/Debouncer.v
../hdl/design/InterruptManager.v
../hdl/design/VmeInterface.v
# Board schematic
../verilog/schematic/VFCBoard.v
../hdl/schematic/VFCBoard.v
# Simulation modules
../verilog/testbench/VmeMaster.v
../verilog/testbench/tb_VFC.v
../hdl/testbench/VmeMaster.v
../hdl/testbench/tb_VFC.v
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