updated the paths for the simulation

e10d9b2b · Andrea Boccardi · 8d2947ac · e10d9b2b · e10d9b2b · e10d9b2b
Commit e10d9b2b authored Nov 11, 2010 by Andrea Boccardi
Expand all Hide whitespace changes
Inline Side-by-side

Showing with 2328 additions and 2328 deletions

makesim trunk/simulation/makesim +1 -1

modulist trunk/simulation/modulist +14 -14

simplesim.o.bkp trunk/simulation/simplesim.o.bkp +2313 -2313

No files found.
--- a/trunk/simulation/makesim
+++ b/trunk/simulation/makesim
 mv simplesim.o simplesim.o.bkp
 iverilog -stb_VFC -fmodulist -osimplesim.o
 ./simplesim.o >& /dev/null &
-(cd ../sw/src; python vmet.py)
+(cd ../software/src; python vmet.py)
 #gtkwave simout.vcd >& /dev/null &
--- a/trunk/simulation/modulist
+++ b/trunk/simulation/modulist
 # Components' models
-../verilog/components/ivt3205c25mhz.v
+../hdl/components/ivt3205c25mhz.v
-../verilog/components/sn74vmeh22501.v
+../hdl/components/sn74vmeh22501.v
 # Components with missing models
-../verilog/components/blackboxes/si57x.v
+../hdl/components/blackboxes/si57x.v
 # System FPGA's modules
-../verilog/design/SystemFpga.v
+../hdl/design/SystemFpga.v
-../verilog/design/CsGenerator.v
+../hdl/design/CsGenerator.v
-../verilog/design/Generic4Regs.v
+../hdl/design/Generic4Regs.v
-../verilog/design/Monostable.v
+../hdl/design/Monostable.v
-../verilog/design/VmeDoutArbiter.v
+../hdl/design/VmeDoutArbiter.v
-../verilog/design/Debouncer.v
+../hdl/design/Debouncer.v
-../verilog/design/InterruptManager.v
+../hdl/design/InterruptManager.v
-../verilog/design/VmeInterface.v
+../hdl/design/VmeInterface.v
 # Board schematic
-../verilog/schematic/VFCBoard.v
+../hdl/schematic/VFCBoard.v
 # Simulation modules
-../verilog/testbench/VmeMaster.v
+../hdl/testbench/VmeMaster.v
-../verilog/testbench/tb_VFC.v
+../hdl/testbench/tb_VFC.v
--- a/trunk/simulation/simplesim.o.bkp
+++ b/trunk/simulation/simplesim.o.bkp