Commit e3bedab5 authored by Andrea Boccardi's avatar Andrea Boccardi

nothing major

parent 8cac29ef
module CsGenerator(
input [23:2] VmeAddr_ib22,
output CsIntManager_oa,
output CsDebugRegs_oa);
assign CsIntManager_oa = VmeAddr_ib22[23:4] == 20'h0; // FROM 00_0000 TO 00_000C (addr[23:0]) <- 4 regs (16B)
assign CsDebugRegs_oa = VmeAddr_ib22[23:4] == 20'h1; // FROM 00_0010 TO 00_001C (addr[23:0]) <- 4 regs (16B)
endmodule
module Generic4Regs (
input Clk_ik,
input Clrn_inra,
input Cs_i,
input WrReg_i,
input [3:2] Address_ib2,
input [31:0] DataIn_ib32,
input RdReg_i,
output DataOutDav_o,
output reg [31:0] DataOut_ob32,
output reg [31:0] Reg0Value_ob32,
output reg [31:0] Reg1Value_ob32,
output reg [31:0] Reg2Value_ob32,
output reg [31:0] Reg3Value_ob32);
always @(posedge Clk_ik or negedge Clrn_inra)
if (~Clrn_inra) Reg0Value_ob32 <= #1 32'h0;
else if (Cs_i && WrReg_i && Address_ib2==2'b00) Reg0Value_ob32 <= #1 DataIn_ib32;
always @(posedge Clk_ik or negedge Clrn_inra)
if (~Clrn_inra) Reg1Value_ob32 <= #1 32'h0;
else if (Cs_i && WrReg_i && Address_ib2==2'b01) Reg1Value_ob32 <= #1 DataIn_ib32;
always @(posedge Clk_ik or negedge Clrn_inra)
if (~Clrn_inra) Reg2Value_ob32 <= #1 32'h0;
else if (Cs_i && WrReg_i && Address_ib2==2'b10) Reg2Value_ob32 <= #1 DataIn_ib32;
always @(posedge Clk_ik or negedge Clrn_inra)
if (~Clrn_inra) Reg3Value_ob32 <= #1 32'h0;
else if (Cs_i && WrReg_i && Address_ib2==2'b11) Reg3Value_ob32 <= #1 DataIn_ib32;
assign DataOutDav_o = RdReg_i;
always @* case (Address_ib2)
2'b00: DataOut_ob32 = Reg0Value_ob32;
2'b01: DataOut_ob32 = Reg1Value_ob32;
2'b10: DataOut_ob32 = Reg2Value_ob32;
2'b11: DataOut_ob32 = Reg3Value_ob32;
default: DataOut_ob32 = Reg0Value_ob32;
endcase
endmodule
module Generic4RegsWB (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output Ack_oa,
output reg [31:0] Reg0Value_ob32,
output reg [31:0] Reg1Value_ob32,
output reg [31:0] Reg2Value_ob32,
output reg [31:0] Reg3Value_ob32);
always @(posedge Clk_ik)
if (Rst_irq) Reg0Value_ob32 <= #1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b00) Reg0Value_ob32 <= #1 Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg1Value_ob32 <= #1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b01) Reg1Value_ob32 <= #1 Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg2Value_ob32 <= #1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b10) Reg2Value_ob32 <= #1 Dat_ib32;
always @(posedge Clk_ik)
if (Rst_irq) Reg3Value_ob32 <= #1 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==(2'b11)) Reg3Value_ob32 <= #1 Dat_ib32;
assign Ack_oa = Stb_i&&Cyc_i;
always @* case (Adr_ib2)
2'b00: Dat_oab32 = Reg0Value_ob32;
2'b01: Dat_oab32 = Reg1Value_ob32;
2'b10: Dat_oab32 = Reg2Value_ob32;
2'b11: Dat_oab32 = Reg3Value_ob32;
default: Dat_oab32 = Reg0Value_ob32;
endcase
endmodule
`timescale 1 ns/ 1 ns
module InterruptManager (
input clk, clrn,
input int_enable,
input vme_cs,
input vme_wr,
input vme_rd,
input [3:2] vme_addr,
input [31:0] vme_data,
output reg vme_dout_dav,
output reg [31:0] vme_dout,
input [7:0] interrupt_in,
output reg osc_clk,
input int_acknowledged,
input clear_all,
output assert_interrupt);
parameter dly = 1;
parameter int_reg_addr = 2'b00;
parameter mask_reg_addr = 2'b01;
parameter fpga_status_reg_addr = 2'b10;
parameter new_int_mode_addr = 2'b11;
reg [7:0] mask_reg, int_masked_old; //if a 1 is in position i than the i_th interrupt is masked
wire [7:0] int_masked, interrupt;
reg [2:0] int_pointer_r, int_pointer_w;
wire clear_int;
reg [7:0] int_fifo [7:0];
reg fifo_full, fifo_empty;
wire asynch_clk_change;
reg hs_int_mode;
wire int_in_fifo;
reg rora_roak;
reg ready4int;
reg [3:0] int_counter;
assign clear_int = vme_cs && vme_rd && vme_addr==int_reg_addr;
always @(posedge clk or negedge clrn) begin
if (~clrn) begin
{hs_int_mode, ready4int, rora_roak, mask_reg} <= # dly 11'h2ff;
end else if (vme_cs && vme_wr && vme_addr==mask_reg_addr) begin
{hs_int_mode, ready4int, rora_roak, mask_reg} <= # dly vme_data[10:0];
end else if (hs_int_mode && ((rora_roak && vme_cs && vme_rd && vme_addr==int_reg_addr) || (~rora_roak && int_acknowledged))) begin
ready4int <= # dly 1'b0;
end
end
assign asynch_clk_change = clrn && ~interrupt_in[6];
always @(posedge clk or negedge asynch_clk_change) begin
if (~asynch_clk_change) begin
osc_clk <= # dly 1'b1;
end else if (vme_cs && vme_wr && vme_addr==mask_reg_addr) begin
osc_clk <= # dly vme_data[31];
end
end
assign int_masked = interrupt_in & ~mask_reg;
always @(posedge clk or negedge clrn) begin
if (~clrn) begin
int_masked_old <= # dly 8'hff;
end else if (~int_enable) begin
int_masked_old <= # dly 8'hff;
end else begin
int_masked_old <= # dly int_masked;
end
end
assign interrupt = int_masked & ~int_masked_old;
assign new_interrupt = |interrupt;
always @(posedge clk or negedge clrn) begin
if (~clrn) begin
int_counter <= # dly 4'h0;
end else if (~int_enable || clear_all) begin
int_counter <= # dly 4'h0;
end else begin
if (new_interrupt && ~fifo_full && ~int_acknowledged && ~&int_counter) begin
int_counter <= # dly int_counter + 1'b1;
end else if (int_acknowledged && ~(new_interrupt && ~fifo_full) && |int_counter) begin
int_counter <= # dly int_counter - 1'b1;
end
end
end
always @(posedge clk or negedge clrn) begin
if (~clrn) begin
int_pointer_r <= # dly 3'h0;
int_pointer_w <= # dly 3'h0;
end else if (~int_enable || clear_all) begin
int_pointer_r <= # dly 3'h0;
int_pointer_w <= # dly 3'h0;
end else begin
if (new_interrupt && ~fifo_full) begin
int_pointer_w <= # dly int_pointer_w + 1'b1;
end
if (clear_int && ~fifo_empty) begin
int_pointer_r <= # dly int_pointer_r + 1'b1;
end
end
end
always @(posedge clk or negedge clrn) begin
if (~clrn) begin
fifo_full <= # dly 1'b0;
fifo_empty <= # dly 1'b1;
end else if (~int_enable || clear_all) begin
fifo_full <= # dly 1'b0;
fifo_empty <= # dly 1'b1;
end else begin
if ((int_pointer_w+1'b1)==int_pointer_r && new_interrupt && ~clear_int) begin
fifo_full <= # dly 1'b1;
end else if (int_pointer_w!=int_pointer_r) begin
fifo_full <= # dly 1'b0;
end
if ((int_pointer_r+1'b1)==int_pointer_w && clear_int && ~new_interrupt) begin
fifo_empty <= # dly 1'b1;
end else if (int_pointer_w!=int_pointer_r) begin
fifo_empty <= # dly 1'b0;
end
end
end
assign int_in_fifo = ~fifo_empty;
always @(posedge clk) begin
if (new_interrupt && ~fifo_full) begin
int_fifo[int_pointer_w] <= # dly interrupt;
end
end
assign assert_interrupt = int_enable && ready4int && ((|int_counter && ~rora_roak) || (int_in_fifo && rora_roak));
wire [7:0] fpga_version;
wire [7:0] fpga_revision;
wire [15:0] date;
assign fpga_version = 8'h00;
assign fpga_revision = 8'h01;
assign date = {8'd6, 4'd10,4'd10};
always @(posedge clk) begin
vme_dout_dav <= # dly vme_rd;
if (vme_rd) begin
case(vme_addr)
int_reg_addr : vme_dout <= # dly fifo_empty ? 32'h0000_0000 : {24'h0, int_fifo[int_pointer_r]};
mask_reg_addr : vme_dout <= # dly {osc_clk, int_enable, 2'h0, 1'b0, int_pointer_r, 1'b0, int_pointer_w, int_counter, 5'h0, hs_int_mode, ready4int, rora_roak, mask_reg};
fpga_status_reg_addr: vme_dout <= # dly {date, fpga_version, fpga_revision};
default: vme_dout <= # dly 32'hdead_beef;
endcase
end
end
endmodule
`timescale 1ns/1ns
module MAX5483Manager (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
input [31:0] Dat_ib32,
output reg [31:0] Dat_oab32,
output Ack_oa,
output reg SPIUD_o,
output CS_oqn,
output reg SclkInc_oqk,
output reg Din_oq);
reg [31:0] MAX5483Reg_qb32;
reg [31:0] ClockDivider;
reg [31:0] SetBusyTime; //1200000 steps @ 100MHz = 12ms as requested in datasheet
reg FlagMAX5483SPI_q; //1 clok flag for SPI cycle
reg FlagMAX5483UD_q; //1 clock flag for UD cycle
reg [31:0] CounterClockStep_q; //Counter used for Clk divider setting -> gets out SlowClck_e
reg [31:0] Counter24Clock; //For SPI full cycle
reg [31:0] CounterXClock; //For UD -> x number of step defined by MAX5483Reg[17:8]
reg SlowClk_e; //is out of clock divider setting
reg CSspi_oqn, CSud_oqn; //CS for SPI and UD cycle
reg CSudD0_oqn, CSudD1_oqn, CSudD2_oqn; //CS with delays
reg DinSPI_oq, DinUD_oq; //Data when SPI and UD mode
reg [9:0] CounterUDStepClock; //will keep CSud down for x steps
reg MAX5483Busy_s;
reg [23:0] CounterBusy_q;
parameter dly = 1;
//#############################################
//Register ClockDivider == clock divider
//#############################################
always @(posedge Clk_ik or posedge Rst_irq)
if (Rst_irq) ClockDivider <= #dly 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b01) ClockDivider <= #dly Dat_ib32;
//#############################################
//Register SetBusyTime == 12ms fonction of the clk
//#############################################
always @(posedge Clk_ik or posedge Rst_irq)
if (Rst_irq) SetBusyTime <= #dly 32'h0;
else if (Cyc_i && We_i && Stb_i && Adr_ib2==2'b10) SetBusyTime <= #dly Dat_ib32;
//############################################
//Reg MAX5483
//############################################
always @(posedge Clk_ik or posedge Rst_irq) begin
if (Rst_irq) MAX5483Reg_qb32 <= #dly 32'h0;
else if (Cyc_i && We_i && Stb_i && (Adr_ib2==2'b00) && Dat_ib32[24]) begin
MAX5483Reg_qb32 <= #dly Dat_ib32;
FlagMAX5483SPI_q <= #dly 1'b1;
end
else if (Cyc_i && We_i && Stb_i && (Adr_ib2==2'b00) && (Dat_ib32[24]==1'b0)) begin
MAX5483Reg_qb32 <= #dly Dat_ib32;
FlagMAX5483UD_q <= #dly 1'b1;
end
else begin
FlagMAX5483SPI_q <= #dly 1'b0;
FlagMAX5483UD_q <= #dly 1'b0;
end
end
//#############################################
//MAX5483 control pins settings SPI
//#############################################
always @(posedge Clk_ik) begin
if (MAX5483Reg_qb32[24]) SPIUD_o <= #dly 1'b1;
else SPIUD_o <= #dly 1'b0;
end
//always @(posedge Clk_ik) SclkInc_oqk <= #dly SlowClk_e;
//#############################################
//Assign Acknowledge
//#############################################
assign Ack_oa = Stb_i && Cyc_i;
//#############################################
//Read registers
//#############################################
always @* case (Adr_ib2)
2'b00: Dat_oab32 = MAX5483Reg_qb32;
2'b01: Dat_oab32 = ClockDivider;
2'b10: Dat_oab32 = SetBusyTime;
2'b11: begin Dat_oab32[0] = MAX5483Busy_s;
Dat_oab32[31:1] = 31'b0;
end
default: Dat_oab32 = 32'hDEADBEEF;
endcase
//#############################################
//Enable 'Slow' Clock generated from ClockDivider number
//#############################################
always @(posedge Clk_ik or posedge Rst_irq) begin
if ((CounterClockStep_q == ClockDivider - 1'b1) || Rst_irq) begin
SlowClk_e <= #dly 1'b1;
CounterClockStep_q <= #dly 1'b0;
end
else if (~CSspi_oqn || ~CSudD0_oqn) begin
CounterClockStep_q <= #dly CounterClockStep_q + 1'b1;
SlowClk_e <= #dly 1'b0;
end
end
//#############################################
//24 clocks cycle manager for SPI mode
//#############################################
always @(posedge Clk_ik or posedge Rst_irq) begin
if (Counter24Clock == 5'd25*ClockDivider || Rst_irq) Counter24Clock <= #dly 32'b0;
else if (|Counter24Clock || FlagMAX5483SPI_q) Counter24Clock <= #dly Counter24Clock + 1'b1;
end
always @(posedge Clk_ik or posedge Rst_irq)
if (Rst_irq) CSspi_oqn <= #dly 1'b1;
else if (MAX5483Reg_qb32[24]) CSspi_oqn <= #dly ~|Counter24Clock;
//#############################################
//X clocks cycle manager for UD mode
//#############################################
always @(posedge Clk_ik or posedge Rst_irq) begin
if (CounterXClock == (CounterUDStepClock)*ClockDivider || Rst_irq) CounterXClock <= #dly 32'b0;
else if (|CounterXClock || FlagMAX5483UD_q) CounterXClock <= #dly CounterXClock + 1'b1;
end
always @(posedge Clk_ik or posedge Rst_irq)
if (Rst_irq) CSudD0_oqn <= #dly 1'b1;
else if (MAX5483Reg_qb32[24] == 1'b0) CSudD0_oqn <= #dly ~|CounterXClock;
//#############################################
//Parallel to serial
//#############################################
reg [23:0] ParallelData;
always @(posedge Clk_ik or posedge Rst_irq) begin
if (Rst_irq) begin
ParallelData <= #dly 24'b0;
DinSPI_oq <= #dly 1'b0;
end
else if (FlagMAX5483SPI_q) ParallelData <= #dly MAX5483Reg_qb32[23:0];
else if (SlowClk_e && ~CSspi_oqn)begin
ParallelData <= #dly {ParallelData[22:0], 1'b0};
DinSPI_oq <= #dly ParallelData[23];
end
end
//#############################################
//Register MAX5483Busy_s == flag saying in use = wiper store cycle time (12ms)
//#############################################
always @(posedge Clk_ik or posedge Rst_irq)
if (CounterBusy_q == SetBusyTime || Rst_irq) CounterBusy_q <= #dly 24'b0;
else if ((MAX5483Reg_qb32[2] == 1'b1 && MAX5483Reg_qb32[3] == 1'b0) && FlagMAX5483SPI_q || |CounterBusy_q) CounterBusy_q <= #dly CounterBusy_q + 1'b1;
always @(posedge Clk_ik) MAX5483Busy_s <= #dly |CounterBusy_q;
//#############################################
//MAX5483 control pins settings
//#############################################
always @(posedge Clk_ik) begin
CounterUDStepClock <= #dly MAX5483Reg_qb32[17:8];
if (MAX5483Reg_qb32[25] == 1'b1) DinUD_oq <= #dly 1'b1; //Count up in UD mode
else if (MAX5483Reg_qb32[25] == 1'b0) DinUD_oq <= #dly 1'b0; //Count down in UD mode
end
always @(posedge Clk_ik) SclkInc_oqk <= #dly SlowClk_e;
always @(posedge Clk_ik) CSudD1_oqn <= #dly CSudD0_oqn;
always @(posedge Clk_ik) CSudD2_oqn <= #dly CSudD1_oqn;
always @* if (MAX5483Reg_qb32[26]) CSud_oqn <= ~(~CSudD0_oqn || ~CSudD2_oqn); //Store in NV in UD mode
else if (~MAX5483Reg_qb32[26]) CSud_oqn <= #dly CSudD0_oqn; //Don't store in NV in UD mode
always @(posedge Clk_ik)
if (~CSspi_oqn) Din_oq <= #dly DinSPI_oq;
else if (~CSud_oqn) Din_oq <= #dly DinUD_oq;
assign CS_oqn = ~(~CSspi_oqn || ~CSud_oqn);
endmodule
\ No newline at end of file
......@@ -36,7 +36,10 @@ module SystemFpga (
input VmeTms_i,
// CLOCKS
input VcTcXo_ik,
input Si57x_ik,
(* IOSTANDARD="LVDS" *)input Si57x_ik,
output Si57xSCl_ok,
inout Si57xSDa_io,
output Si57xOe_o,
// PUSH BUTTON
inout PushButton_ion,
// SWITCHES
......@@ -47,7 +50,6 @@ module SystemFpga (
output FpGpIo1OutputMode_o,
output FpGpIo2OutputMode_o,
output FpGpIo34OutputMode_o,
// Application FPGA Programming Pins
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgClk_io,
......@@ -55,37 +57,30 @@ module SystemFpga (
inout AFpgaProgCsi_io,
inout AFpgaProgRdWr_io,
inout AFpgaProgInit_io,
// Application FPGA Clk
output SysAppClk_o,
output SysAppClk_ok,
// Application FPGA Slow Communication
inout [2:1] SysAppSlow_iob2,
// Flash PROMs Interfaces
output FlashSFpgaD_o,
output FlashSFpgaClk_ok,
output FlashSFpgaCs_on,
input FlashSFpgaQ_i,
output FlashAFpgaD_o,
output FlashAFpgaClk_ok,
output FlashAFpgaCs_on,
input FlashAFpgaQ_i,
// Voltage Monitoring ADC interface
output VAdcSClk_ok,
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_on,
// VAdj Control
output VAdjCs_on,
output VAdjSClk_ok,
output VAdjDin_o,
output VAdjInhibit_ozn,
output VAdjSpi_o,
// PLLs control
input PllFmc1Ld_i,
input PllFmc1Status_i,
......@@ -100,7 +95,6 @@ module SystemFpga (
input PllFmc1Sdo_i,
output PllFmc1Cs_on,
input PllFmc12SFpgaP_ik,
input PllFmc2Ld_i,
input PllFmc2Status_i,
input PllFmc2RefMon_i,
......@@ -113,13 +107,12 @@ module SystemFpga (
inout PllFmc2SDio_io,
input PllFmc2Sdo_i,
output PllFmc2Cs_on,
input PllFmc22SFpgaP_ik,
input PllFmc22SFpgaP_ik,
input PllSysLd_i,
input PllSysStatus_i,
input PllSysRefMon_i,
output PllSysRefSel_o,
output PllSysRef12_ok,
output PllSysRef12_ok,
output PllSysPd_on,
output PllSysSynch_on,
output PllSysReset_orn,
......@@ -128,7 +121,6 @@ module SystemFpga (
input PllSysSdo_i,
output PllSysCs_on,
input PllSys2SFpgaP_ik,
input PllDdsLd_i,
input PllDdsStatus_i,
input PllDdsRefMon_i,
......@@ -142,15 +134,108 @@ module SystemFpga (
input PllDdsSdo_i,
output PllDdsCs_on,
input PllDds2SFpgaP_ik,
// PLL DAC
output PllDacSClk_ok,
output PllDacSynch_on,
output PllDacDin_o,
input PllDacDout_i,
output PllDacClrn_orn,
output PllDacLDac_on
output PllDacLDac_on,
// DDS
output [1:0] DdsF_ob2,
output [2:0] DdsProfile_ob3,
output [15:0] DdsD_ob16,
input DdsSyncSmpErr_i,
output DdsTxEnable_o,
output DdsMasterRst_or,
output DdsPowerDown_o,
input DdsPllLock_i,
inout DdsIOUpdate_io,
output DdsOsk_o,
output DdsDrHold_o,
output DdsSClk_o,
input DdsSDo_i,
output DdsSDio_io,
input DdsRamSwpOvr_i,
output DdsIoReset_or,
output DdsDrCtl_o,
input DdsDrOver_i,
input DdsSyncClk_ik,
input DdsPdClk_ik,
input DdsSyncOut_ik,
output DdsSyncIn_ok,
// VME P0
output VmeP0BuslineDir_o,
output VmeP0BuslineOe_o,
output VmeP0HwLowByteDir_o,
output VmeP0HwLowByteOe_o,
output VmeP0HwHighByteDir_o,
output VmeP0HwHighByteOe_o,
output VmeP0BunchSelectDir_o,
output VmeP0BunchSelectOe_o,
input VmeP0LvdsBunchClkIn_i,
output VmeP0LvdsBunchClkOut_o,
input VmeP0LvdsTClkIn_i,
output VmeP0LvdsTClkOut_o,
// DDR
output [13:0] DdrA_ob14,
output [2:0] DdrBA_ob3,
inout [15:0] DdrDQ_iob16,
output DdrReset_or,
output DdrCkE_o,
output DdrWe_o,
output DdrCk_ok,
output DdrODT_o,
output DdrRAS_o,
output DdrCAS_o,
output DdrUDM_o,
output DdrLDM_o,
inout DdrLDQS_io,
inout DdrUDQS_io,
// Miscellaneaus
input [7:0] PcbRev_ib8,
// SFP Controls
input WRModeDef0_i,
output WRModeDef1_i,
inout WRModeDef2_io,
output WRRateSelect_o,
output WRTxDisable_o,
input WRTxFault_i,
input WRLoS_i,
input Sfp2ModeDef0_i,
output Sfp2ModeDef1_i,
inout Sfp2ModeDef2_io,
output Sfp2RateSelect,
input Sfp2LoS_i,
output Sfp2TxDisable_o,
input Sfp2TxFault_i,
// FMC controls
output Fmc1PGC2M_in,
input Fmc1PrsntM2C_in,
output Fmc2PGC2M_in,
input Fmc2PrsntM2C_in,
inout Fmc1SDa_io,
output Fmc1SCl_ok,
inout Fmc2SDa_io,
output Fmc2SCl_ok,
// GBit signals
output WRGBitOut_o,
input WRGbitIn_i,
input WRRefClk_ik,
output Sfp2GBitOut_o,
input Sfp2GbitIn_i,
output SataTx_o,
input SataRx_i,
output Gbit1Sys2App_o,
input Gbit1App2Sys_i,
output Gbit2Sys2App_o,
input Gbit2App2Sys_i,
input Gbit12RefClk_ik,
output Gbit3Sys2App_o,
input Gbit3App2Sys_i,
output Gbit4Sys2App_o,
input Gbit4App2Sys_i,
input Gbit34RefClk_ik
);
`define dly 1
......@@ -160,6 +245,105 @@ wire [31:0] DatGenericOutputRegsrO_b32;
wire StbGenericOutputRegs, AckGenericOutputRegs;
wire VmeAccessForLed;
wire RstForLed;
wire DeboucedPushButton_q;
wire SpiIdle, SpiWaitingData;
wire IntAcknowledged;
wire AssertInterrupt;
wire VmeDtAck_n, VmeDOe;
wire [7:1] VmeIrq_b7n;
wire StbMaster, AckMaster, Cyc, We;
wire [21:0] Adr_b22;
wire [31:0] DatMasterI_b32, DatMasterO_b32;
wire [31:0] DatIntManagerO_b32;
wire StbIntManager, AckIntMAnager;
wire [31:0] PllStatusBits_b32, GenericInputReg1, GenericInputReg2, GenericInputReg3;
wire [31:0] DatGenericInputRegsrO_b32;
wire StbGenericInputRegs, AckGenericInputRegs;
wire [31:0] DatSlv2SerWBO_b32;
wire StbSlv2SerWB, AckSlv2SerWB;
wire [31:0] SpiSS_nb32, SpiMiSo_b32;
wire SpiMoSi, SpiSClk_k;
wire StbSpiMaster, AckSpiMaster;
wire [31:0] DatSpiMaster_b32;
wire Si57xDivided, VcTcXoDivided, VmeSysClkDivided;
wire Clk_k;
wire a_VmeSysReset_nq;
wire [7:0] IntSource_b8;
wire [2:0] InterrupLevel;
wire [7:0] IntVector_b8;
reg [21:0] Si57xDivider_c = 'd0;
reg [21:0] VcTcXoDivider_c = 'd0;
reg [21:0] VmeSysClkDivider_c = 'd0;
reg a_FpLed7;
reg Rst_rq;
reg [1:0] VmeSysReset_dx;
//####################################
// Interface Output Pins to be assigned
//####################################
assign WRModeDef1_i= 1'b0;
assign WRModeDef2_io= 1'bz;
assign WRRateSelect_o= 1'b0;
assign WRTxDisable_o= 1'b0;
assign Sfp2ModeDef1_i= 1'b0;
assign Sfp2ModeDef2_io= 1'bz;
assign Sfp2RateSelect= 1'b0;
assign Sfp2TxDisable_o= 1'b0;
assign Fmc1PGC2M_in= 1'b0;
assign Fmc2PGC2M_in= 1'b0;
assign Fmc1SDa_io= 1'bz;
assign Fmc1SCl_ok= 1'b0;
assign Fmc2SDa_io= 1'bz;
assign Fmc2SCl_ok= 1'b0;
assign VmeP0LvdsBunchClkOut_o= 1'b0;
assign VmeP0LvdsTClkOut_o= 1'b0;
assign DdrA_ob14= 14'b0;
assign DdrBA_ob3= 3'b0;
assign DdrDQ_iob16= 16'hZZZZ;
assign DdrReset_or= 1'b0;
assign DdrCkE_o= 1'b0;
assign DdrWe_o= 1'b0;
assign DdrCk_ok= 1'b0;
assign DdrODT_o= 1'b0;
assign DdrRAS_o= 1'b0;
assign DdrCAS_o= 1'b0;
assign DdrUDM_o= 1'b0;
assign DdrLDM_o= 1'b0;
assign DdrLDQS_io= 1'bz;
assign DdrUDQS_io= 1'bz;
assign VmeP0BuslineDir_o= 1'b0;
assign VmeP0BuslineOe_o= 1'b0;
assign VmeP0HwLowByteDir_o= 1'b0;
assign VmeP0HwLowByteOe_o= 1'b0;
assign VmeP0HwHighByteDir_o= 1'b0;
assign VmeP0HwHighByteOe_o= 1'b0;
assign VmeP0BunchSelectDir_o= 1'b0;
assign VmeP0BunchSelectOe_o= 1'b0;
assign Si57xSCl_ok= 1'b0;
assign Si57xSDa_io= 1'bz;
assign Si57xOe_o= 1'b0;
assign DdsF_ob2= 2'b0;
assign DdsProfile_ob3= 3'b0;
assign DdsD_ob16= 16'b0;
assign DdsTxEnable_o= 1'b0;
assign DdsMasterRst_or= 1'b0;
assign DdsPowerDown_o= 1'b0;
assign DdsIOUpdate_io= 1'bz;
assign DdsOsk_o= 1'b0;
assign DdsDrHold_o= 1'b0;
assign DdsSClk_o= 1'b0;
assign DdsSDio_io= 1'b0;
assign DdsIoReset_or= 1'b0;
assign DdsDrCtl_o= 1'b0;
assign DdsSyncIn_ok= 1'b0;
//####################################
// FP Leds
......@@ -180,20 +364,15 @@ assign FpLed_onb8[1] = (~&VmeIrq_ob7) ? 1'b0 : 1'bz;
assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz;
assign FpLed_onb8[3] = RstForLed ? 1'b0 : 1'bz;
reg [21:0] Si57xDivider_c = 'd0;
wire Si57xDivided = Si57xDivider_c[21];
assign Si57xDivided = Si57xDivider_c[21];
always @(posedge Si57x_ik) Si57xDivider_c <= #`dly Si57xDivider_c + 1'b1;
reg [21:0] VcTcXoDivider_c = 'd0;
wire VcTcXoDivided = VcTcXoDivider_c[21];
assign VcTcXoDivided = VcTcXoDivider_c[21];
always @(posedge VcTcXo_ik) VcTcXoDivider_c <= #`dly VcTcXoDivider_c + 1'b1;
reg [21:0] VmeSysClkDivider_c = 'd0;
wire VmeSysClkDivided = VmeSysClkDivider_c[21];
assign VmeSysClkDivided = VmeSysClkDivider_c[21];
always @(posedge VmeSysClk_ik) VmeSysClkDivider_c <= #`dly VmeSysClkDivider_c + 1'b1;
reg a_FpLed7;
always @* case(Switch_ib2)
2'b00: a_FpLed7 = Si57xDivided;
2'b01: a_FpLed7 = VcTcXoDivided;
......@@ -218,19 +397,15 @@ assign FpGpIo34OutputMode_o = 1'b1;
// Clock
//####################################
wire Clk_k= Si57x_ik;
assign Clk_k= Si57x_ik;
//#####################################
// Reset Signal Generation
//#####################################
reg Rst_rq;
reg [1:0] VmeSysReset_dx;
always @(posedge Clk_k) VmeSysReset_dx <= #`dly {VmeSysReset_dx[0], VmeSysReset_in};
wire a_VmeSysReset_nq = VmeSysReset_dx[1];
assign a_VmeSysReset_nq = VmeSysReset_dx[1];
wire DeboucedPushButton_q;
Debouncer #(.g_CounterWidth(16), .g_SynchDepth(3)) i_Debouncer (
.Clk_ik(Clk_k),
.BouncingSignal_ia(PushButton_ion),
......@@ -242,12 +417,6 @@ always @(posedge Clk_k) Rst_rq <= #`dly ~DeboucedPushButton_q || ~a_VmeSysReset_
// VME Interface
//#####################################
wire SpiIdle, SpiWaitingData;
wire IntAcknowledged;
wire AssertInterrupt;
wire VmeDtAck_n, VmeDOe;
wire [7:1] VmeIrq_b7n;
assign VmeDtAck_on = 1'b0;
assign VmeDtAckOe_oe = ~VmeDtAck_n;
assign VmeDOeN_oen = ~VmeDOe;
......@@ -259,18 +428,13 @@ assign VmeBerr_o = 1'b0;
assign VmeIrq_ob7 = ~VmeIrq_b7n;
assign VmeTdoOe_oe = 1'b0;
wire [2:0] InterrupLevel = InterruptConfigReg_b32[30:28];
wire [7:0] IntVector_b8 = InterruptConfigReg_b32[7:0];
wire [7:0] IntSource_b8;
assign InterrupLevel = InterruptConfigReg_b32[30:28];
assign IntVector_b8 = InterruptConfigReg_b32[7:0];
assign IntSource_b8[7:2] = GenericOutputReg1[7:2];
assign IntSource_b8[1] = SpiIdle;
assign IntSource_b8[0] = SpiWaitingData;
wire StbMaster, AckMaster, Cyc, We;
wire [21:0] Adr_b22;
wire [31:0] DatMasterI_b32, DatMasterO_b32;
VmeInterfaceWB i_VmeInterface(
.rst_i(Rst_rq),
.clk_i(Clk_k),
......@@ -305,9 +469,6 @@ VmeInterfaceWB i_VmeInterface(
.assert_interrupt(AssertInterrupt),
.clear_int(IntAcknowledged));
wire [31:0] DatIntManagerO_b32;
wire StbIntManager, AckIntMAnager;
InterruptManagerWB i_InterruptManager(
.Clk_ik(Clk_k),
.Rst_irq(Rst_rq),
......@@ -375,11 +536,6 @@ Generic4OutputRegs #(.Reg2Default(32'h8888)) i_Generic4OutputRegs(
// GenericInput Registers
//#####################################
wire [31:0] PllStatusBits_b32, GenericInputReg1, GenericInputReg2, GenericInputReg3;
wire [31:0] DatGenericInputRegsrO_b32;
wire StbGenericInputRegs, AckGenericInputRegs;
Generic4InputRegs i_Generic4InputRegs(
.Rst_irq(Rst_rq),
.Cyc_i(Cyc),
......@@ -396,9 +552,6 @@ Generic4InputRegs i_Generic4InputRegs(
// WB Serial Interface To The A-FPGA
//#####################################
wire [31:0] DatSlv2SerWBO_b32;
wire StbSlv2SerWB, AckSlv2SerWB;
Slv2SerWB i_Slv2SerWB(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
......@@ -421,12 +574,6 @@ Slv2SerWB i_Slv2SerWB(
// SPI master
//#####################################
wire [31:0] SpiSS_nb32, SpiMiSo_b32;
wire SpiMoSi, SpiSClk_k;
wire StbSpiMaster, AckSpiMaster;
wire [31:0] DatSpiMaster_b32;
assign SpiMiSo_b32[31] = SpiMoSi;
assign SpiMiSo_b32[8] = FlashSFpgaQ_i; //Think about removing it and placing it in a special place (CSR space)
......@@ -548,4 +695,4 @@ assign PllDacClrn_orn = 1'b1;
assign PllDacLDac_on = 1'b0; //always updating the dac after a new value is loaded
endmodule
\ No newline at end of file
endmodule
module VmeDoutArbiter (
input CsIntManager_i,
input IntManagerDav_i,
input [31:0] IntManagerData_ib32,
input CsDebugRegs_i,
input DebugRegsDav_i,
input [31:0] DebugRegsData_ib32,
output reg VmeDav_o,
output reg [31:0] VmeData_ob32);
always @(*) begin
VmeData_ob32 = 32'hdead_beef;
VmeDav_o = 1'b0;
if (CsIntManager_i) begin
VmeData_ob32 = IntManagerData_ib32;
VmeDav_o = IntManagerDav_i;
end else if (CsDebugRegs_i) begin
VmeData_ob32 = DebugRegsData_ib32;
VmeDav_o = DebugRegsDav_i;
end
end
endmodule
`timescale 1ns/1ns
module VmeInterface(
input clk, clrn,
input UseGa_i,
input [4:0] ManualAddress_i,
input [4:0] vme_ga,
input vme_gap,
input vme_as,
input vme_ds1,
input vme_ds2,
input [5:0] vme_am,
input vme_wr,
output reg vme_dtack,
input vme_lword,
input [31:1] vme_addr,
inout [31:0] vme_data,
output reg VmeDOe_o,
output reg VmeDDirFpgaToVme_o,
input vme_iackinn,
input vme_iackn,
output reg vme_iack_outn,
output reg [7:1] vme_irqn,
input [2:0] intlev_reg,
input [7:0] IrqVector_i,
output reg wr_reg,
output reg rd_reg,
output reg [31:2] vme_addr_out,
output reg [31:0] vme_data_out,
input dav,
input [31:0] data_in,
input assert_interrupt,
output reg clear_int);
parameter dly = 1;
reg oe_vme_data;
reg [1:0] ds1_shr, ds2_shr;
reg [1:0] as_shr;
wire as_int, pre_as_int, ds_int;
wire [4:0] base_addr;
wire gap_error;
wire selected;
reg dav_reg;
reg [31:0] data_in_reg;
wire valid_am;
reg pre_wr_reg;
reg [2:0] state;
parameter s_idle = 3'h0;
parameter s_read = 3'h1;
parameter s_write = 3'h2;
parameter s_ack_int = 3'h3;
assign gap_error = ^{vme_ga, ~vme_gap};
assign base_addr = (gap_error | ~UseGa_i) ? ManualAddress_i : ~vme_ga;
assign valid_am = (vme_am==6'h0F) || (vme_am==6'h0D) || (vme_am==6'h0B) || (vme_am==6'h09);
assign selected = vme_iackn && ~as_int && ~ds_int && ~vme_lword && valid_am && (vme_addr_out[31:24]=={3'b0, base_addr});
//******************************
//ADD OF A DEFAULT REPLAY IN CASE OF MISSING ANSWER FROM THE EXTERNAL MODULES
//******************************
reg [4:0] rd_to_counter;
always @(posedge clk or negedge clrn) begin
if (~clrn) begin
rd_to_counter <= # dly 5'h0;
end else begin
if (dav) begin
rd_to_counter <= # dly 5'h0;
end else if (rd_reg) begin
rd_to_counter <= # dly 5'h1;
end else if (|rd_to_counter) begin
rd_to_counter <= # dly rd_to_counter + 1'b1;
end
end
end
always @(posedge clk) dav_reg <= # dly dav || &rd_to_counter;
always @(posedge clk) if (dav) data_in_reg <= # dly &rd_to_counter ? 32'hdead_beef : data_in;
//******************************
reg SendIrqVector;
assign vme_data = oe_vme_data ? (SendIrqVector ? {24'h0, IrqVector_i} : data_in_reg) : 32'hz;
assign pre_as_int = as_shr[0];
assign as_int = as_shr[1];
assign ds_int = ds1_shr[1] && ds2_shr[1];
always @(posedge clk) begin
as_shr <= # dly {as_shr[0], vme_as};
ds1_shr <= # dly {ds1_shr[0], vme_ds1};
ds2_shr <= # dly {ds2_shr[0], vme_ds2};
end
always @(posedge clk or negedge clrn) begin
if (~clrn) begin
vme_irqn <= # dly 7'h7f;
end else begin
vme_irqn <= # dly 7'h7f;
if (assert_interrupt) begin
vme_irqn[intlev_reg] <= # dly 1'b0;
end
end
end
always @(posedge clk or negedge clrn) begin
if (~clrn) begin
state <= # dly s_idle;
oe_vme_data <= # dly 1'b0;
vme_dtack <= # dly 1'b1;
wr_reg <= # dly 1'b0;
rd_reg <= # dly 1'b0;
vme_addr_out <= # dly 30'h0;
vme_data_out <= # dly 32'h0;
pre_wr_reg <= # dly 1'b0;
vme_iack_outn <= # dly 1'b1;
clear_int <= # dly 1'b0;
VmeDOe_o <= # dly 1'b0;
VmeDDirFpgaToVme_o <= # dly 1'b1;
SendIrqVector <= # dly 1'b0;
end else case (state)
s_idle: begin
pre_wr_reg <= # dly 1'b0;
state <= # dly s_idle;
oe_vme_data <= # dly 1'b0;
VmeDOe_o <= # dly 1'b0;
VmeDDirFpgaToVme_o <= # dly 1'b1;
vme_dtack <= # dly 1'b1;
wr_reg <= # dly 1'b0;
rd_reg <= # dly 1'b0;
vme_iack_outn <= # dly 1'b1;
clear_int <= # dly 1'b0;
SendIrqVector <= # dly 1'b0;
if (as_int && ~pre_as_int) begin
vme_addr_out <= # dly vme_addr[31:2];
end
if (selected) begin
VmeDOe_o <= # dly 1'b1;
if (vme_wr) begin
state <= # dly s_read;
rd_reg <= # dly 1'b1;
end else begin
state <= # dly s_write;
VmeDDirFpgaToVme_o <= # dly 1'b0;
end
end else if (~vme_iackinn) begin
if (~as_int && vme_addr[3:1]==intlev_reg && ~&vme_irqn && ~ds1_shr[1]) begin
state <= # dly s_ack_int;
clear_int <= # dly 1'b1;
SendIrqVector <= # dly 1'b1;
oe_vme_data <= # dly 1'b1;
VmeDOe_o <= # dly 1'b1;
end else if (~as_int) begin
vme_iack_outn <= # dly 1'b0;
end
end
end
s_read: begin
oe_vme_data <= # dly 1'b1;
rd_reg <= # dly 1'b0;
if (dav_reg) begin
vme_dtack <= # dly 1'b0;
end
if (~selected) begin
state <= # dly s_idle;
VmeDOe_o <= # dly 1'b0;
oe_vme_data <= # dly 1'b0;
vme_addr_out <= # dly vme_addr_out + 1'b1;
end
end
s_write: begin
wr_reg <= # dly pre_wr_reg;
if (vme_dtack && ~pre_wr_reg) begin
pre_wr_reg <= # dly 1'b1;
end else begin
pre_wr_reg <= # dly 1'b0;
end
if (pre_wr_reg) begin
vme_data_out <= # dly vme_data;
vme_dtack <= # dly 1'b0;
end
if (~selected) begin
state <= # dly s_idle;
VmeDOe_o <= # dly 1'b0;
VmeDDirFpgaToVme_o <= # dly 1'b1;
vme_addr_out <= # dly vme_addr_out + 1'b1;
end
end
s_ack_int: begin
clear_int <= # dly 1'b0;
SendIrqVector <= # dly 1'b1;
if (ds1_shr[1] && vme_iackinn) begin
state <= # dly s_idle;
vme_dtack <= # dly 1'b1;
VmeDOe_o <= # dly 1'b0;
end else begin
vme_dtack <= # dly clear_int; //need to delay 1 clock cycle
end
end
default: begin
state <= # dly s_idle;
end
endcase
end
endmodule
`timescale 1ns/1ns
module VfcSFpga (
input UseGa_i,
input [4:0] ManualAddress_ib5,
input [4:0] VmeGa_ib5n,
input VmeGaP_in,
output [7:1] VmeIrq_ob7,
inout [31:0] VmeD_iob32,
output VmeDtAckOe_oe,
output VmeDtAck_on,
inout [31:1] VmeA_iob31,
inout VmeLword_io,
input [5:0] VmeAm_ib6,
input VmeAs_in,
input VmeSysClk_ik,
input VmeWrite_in,
output VmeDOeN_oen,
output VmeDDirVfcToVme_o,
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
input [2:1] VmeDs_inb2,
output VmeAOeN_oen,
output VmeADirVfcToVme_o,
output VmeRetryOe_oe,
output VmeRetry_on,
output VmeBerr_o,
input VmeSysReset_in,
input VmeTck_i,
input VmeTrst_i,
output VmeTdoOe_oe,
output VmeTdo_o,
input VmeTdi_i,
input VmeTms_i,
input VcTcXo_ik,
input Si57x_ik,
input Si57x_ikn,
output Si57xSCl_ok,
inout Si57xSDa_io,
output Si57xOe_o,
inout PushButton_ion,
input [1:0] Switch_ib2,
output [7:0] FpLed_onb8,
output FpGpIo1OutputMode_o,
output FpGpIo2OutputMode_o,
output FpGpIo34OutputMode_o,
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgClk_io,
inout [1:0] AFpgaProgM_iob2,
inout AFpgaProgCsi_io,
inout AFpgaProgRdWr_io,
inout AFpgaProgInit_io,
output SysAppClk_ok,
output SysAppClk_okn,
inout [2:1] SysAppSlow_iob2,
output FlashSFpgaD_o,
output FlashSFpgaClk_ok,
output FlashSFpgaCs_on,
input FlashSFpgaQ_i,
output FlashAFpgaD_o,
output FlashAFpgaClk_ok,
output FlashAFpgaCs_on,
input FlashAFpgaQ_i,
output VAdcSClk_ok,
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_on,
output VAdjCs_on,
output VAdjSClk_ok,
output VAdjDin_o,
output VAdjInhibit_ozn,
output VAdjSpi_o,
input PllFmc1Ld_i,
input PllFmc1Status_i,
input PllFmc1RefMon_i,
output PllFmc1RefSel_o,
output PllFmc1Ref1_ok,
output PllFmc1Pd_on,
output PllFmc1Synch_on,
output PllFmc1Reset_orn,
output PllFmc1SClk_ok,
inout PllFmc1SDio_io,
input PllFmc1Sdo_i,
output PllFmc1Cs_on,
input PllFmc12SFpgaP_ik,
input PllFmc12SFpgaP_ikn,
input PllFmc2Ld_i,
input PllFmc2Status_i,
input PllFmc2RefMon_i,
output PllFmc2RefSel_o,
output PllFmc2Ref1_ok,
output PllFmc2Pd_on,
output PllFmc2Synch_on,
output PllFmc2Reset_orn,
output PllFmc2SClk_ok,
inout PllFmc2SDio_io,
input PllFmc2Sdo_i,
output PllFmc2Cs_on,
input PllFmc22SFpgaP_ik,
input PllFmc22SFpgaP_ikn,
input PllSysLd_i,
input PllSysStatus_i,
input PllSysRefMon_i,
output PllSysRefSel_o,
output PllSysRef12_ok,
output PllSysRef12_okn,
output PllSysPd_on,
output PllSysSynch_on,
output PllSysReset_orn,
output PllSysSClk_ok,
inout PllSysSDio_io,
input PllSysSdo_i,
output PllSysCs_on,
input PllSys2SFpgaP_ik,
input PllSys2SFpgaP_ikn,
input PllDdsLd_i,
input PllDdsStatus_i,
input PllDdsRefMon_i,
output PllDdsRefSel_o,
output PllDdsPd_on,
output PllDdsSynch_on,
output PllDdsReset_orn,
output PllDdsClk_ok,
output PllDdsSClk_ok,
inout PllDdsSDio_io,
input PllDdsSdo_i,
output PllDdsCs_on,
input PllDds2SFpgaP_ik,
input PllDds2SFpgaP_ikn,
output PllDacSClk_ok,
output PllDacSynch_on,
output PllDacDin_o,
input PllDacDout_i,
output PllDacClrn_orn,
output PllDacLDac_on,
output [1:0] DdsF_ob2,
output [2:0] DdsProfile_ob3,
output [15:0] DdsD_ob16,
input DdsSyncSmpErr_i,
output DdsTxEnable_o,
output DdsMasterRst_or,
output DdsPowerDown_o,
input DdsPllLock_i,
inout DdsIOUpdate_io,
output DdsOsk_o,
output DdsDrHold_o,
output DdsSClk_o,
input DdsSDo_i,
output DdsSDio_io,
input DdsRamSwpOvr_i,
output DdsIoReset_or,
output DdsDrCtl_o,
input DdsDrOver_i,
input DdsSyncClk_ik,
input DdsPdClk_ik,
input DdsSyncOut_ik,
input DdsSyncOut_ikn,
output DdsSyncIn_ok,
output DdsSyncIn_okn,
output VmeP0BuslineDir_o,
output VmeP0BuslineOe_o,
output VmeP0HwLowByteDir_o,
output VmeP0HwLowByteOe_o,
output VmeP0HwHighByteDir_o,
output VmeP0HwHighByteOe_o,
output VmeP0BunchSelectDir_o,
output VmeP0BunchSelectOe_o,
input VmeP0LvdsBunchClkIn_i,
output VmeP0LvdsBunchClkOut_o,
input VmeP0LvdsTClkIn_i,
output VmeP0LvdsTClkOut_o,
output [13:0] DdrA_ob14,
output [2:0] DdrBA_ob3,
inout [15:0] DdrDQ_iob16,
output DdrReset_or,
output DdrCkE_o,
output DdrWe_o,
output DdrCk_ok,
output DdrODT_o,
output DdrRAS_o,
output DdrCAS_o,
output DdrUDM_o,
output DdrLDM_o,
inout DdrLDQS_io,
inout DdrUDQS_io,
input [7:0] PcbRev_ib8,
input WRModeDef0_i,
output WRModeDef1_i,
inout WRModeDef2_io,
output WRRateSelect_o,
output WRTxDisable_o,
input WRTxFault_i,
input WRLoS_i,
input Sfp2ModeDef0_i,
output Sfp2ModeDef1_i,
inout Sfp2ModeDef2_io,
output Sfp2RateSelect,
input Sfp2LoS_i,
output Sfp2TxDisable_o,
input Sfp2TxFault_i,
output Fmc1PGC2M_in,
input Fmc1PrsntM2C_in,
output Fmc2PGC2M_in,
input Fmc2PrsntM2C_in,
inout Fmc1SDa_io,
output Fmc1SCl_ok,
inout Fmc2SDa_io,
output Fmc2SCl_ok,
output WRGBitOut_o,
input WRGbitIn_i,
input WRRefClk_ik,
output Sfp2GBitOut_o,
input Sfp2GbitIn_i,
output SataTx_o,
input SataRx_i,
output Gbit1Sys2App_o,
input Gbit1App2Sys_i,
output Gbit2Sys2App_o,
input Gbit2App2Sys_i,
input Gbit12RefClk_ik,
output Gbit3Sys2App_o,
input Gbit3App2Sys_i,
output Gbit4Sys2App_o,
input Gbit4App2Sys_i,
input Gbit34RefClk_ik
);
module SystemFpga (
// VME BUS SIGNALS
input UseGa_i,
input [4:0] ManualAddress_ib5,
input [4:0] VmeGa_ib5n,
input VmeGaP_in,
output [7:1] VmeIrq_ob7, // Active high because of the connection on the board
inout [31:0] VmeD_iob32,
output VmeDtAckOe_oe,
output VmeDtAck_on,
inout [31:1] VmeA_iob31,
inout VmeLword_io,
input [5:0] VmeAm_ib6,
input VmeAs_in,
input VmeSysClk_ik,
input VmeWrite_in,
output VmeDOeN_oen,
output VmeDDirVfcToVme_o,
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
input [2:1] VmeDs_inb2,
output VmeAOeN_oen,
output VmeADirVfcToVme_o,
output VmeRetryOe_oe,
output VmeRetry_on,
output VmeBerr_o, // Active high because of the connection on the board
input VmeSysReset_in,
input VmeTck_i,
input VmeTrst_i,
output VmeTdoOe_oe,
output VmeTdo_o,
input VmeTdi_i,
input VmeTms_i,
// CLOCKS
input VcTcXo_ik,
input Si57x_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
output Si57xSCl_ok,
inout Si57xSDa_io,
output Si57xOe_o,
// PUSH BUTTON
inout PushButton_ion,
// SWITCHES
input [1:0] Switch_ib2,
// Front Panel GPIO
output [7:0] FpLed_onb8,
// Front Panel GPIO
output FpGpIo1OutputMode_o,
output FpGpIo2OutputMode_o,
output FpGpIo34OutputMode_o,
// Application FPGA Programming Pins
inout [7:0] AFpgaProgD_iob8,
inout AFpgaProgClk_io,
inout [1:0] AFpgaProgM_iob2,
inout AFpgaProgCsi_io,
inout AFpgaProgRdWr_io,
inout AFpgaProgInit_io,
// Application FPGA Clk
output SysAppClk_ok/* synthesis xc_padtype = "OBUFG_LVDS" */,
// Application FPGA Slow Communication
inout [2:1] SysAppSlow_iob2,
// Flash PROMs Interfaces
output FlashSFpgaD_o,
output FlashSFpgaClk_ok,
output FlashSFpgaCs_on,
input FlashSFpgaQ_i,
output FlashAFpgaD_o,
output FlashAFpgaClk_ok,
output FlashAFpgaCs_on,
input FlashAFpgaQ_i,
// Voltage Monitoring ADC interface
output VAdcSClk_ok,
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_on,
// VAdj Control
output VAdjCs_on,
output VAdjSClk_ok,
output VAdjDin_o,
output VAdjInhibit_ozn,
output VAdjSpi_o,
// PLLs control
input PllFmc1Ld_i,
input PllFmc1Status_i,
input PllFmc1RefMon_i,
output PllFmc1RefSel_o,
output PllFmc1Ref1_ok,
output PllFmc1Pd_on,
output PllFmc1Synch_on,
output PllFmc1Reset_orn,
output PllFmc1SClk_ok,
inout PllFmc1SDio_io,
input PllFmc1Sdo_i,
output PllFmc1Cs_on,
input PllFmc12SFpgaP_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
input PllFmc2Ld_i,
input PllFmc2Status_i,
input PllFmc2RefMon_i,
output PllFmc2RefSel_o,
output PllFmc2Ref1_ok,
output PllFmc2Pd_on,
output PllFmc2Synch_on,
output PllFmc2Reset_orn,
output PllFmc2SClk_ok,
inout PllFmc2SDio_io,
input PllFmc2Sdo_i,
output PllFmc2Cs_on,
input PllFmc22SFpgaP_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
input PllSysLd_i,
input PllSysStatus_i,
input PllSysRefMon_i,
output PllSysRefSel_o,
output PllSysRef12_ok/* synthesis xc_padtype = "OBUFG_LVDS" */,
output PllSysPd_on,
output PllSysSynch_on,
output PllSysReset_orn,
output PllSysSClk_ok,
inout PllSysSDio_io,
input PllSysSdo_i,
output PllSysCs_on,
input PllSys2SFpgaP_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
input PllDdsLd_i,
input PllDdsStatus_i,
input PllDdsRefMon_i,
output PllDdsRefSel_o,
output PllDdsPd_on,
output PllDdsSynch_on,
output PllDdsReset_orn,
output PllDdsClk_ok,
output PllDdsSClk_ok,
inout PllDdsSDio_io,
input PllDdsSdo_i,
output PllDdsCs_on,
input PllDds2SFpgaP_ik/* synthesis xc_padtype = "OBUFG_LVDS" */,
// PLL DAC
output PllDacSClk_ok,
output PllDacSynch_on,
output PllDacDin_o,
input PllDacDout_i,
output PllDacClrn_orn,
output PllDacLDac_on,
// DDS
output [1:0] DdsF_ob2,
output [2:0] DdsProfile_ob3,
output [15:0] DdsD_ob16,
input DdsSyncSmpErr_i,
output DdsTxEnable_o,
output DdsMasterRst_or,
output DdsPowerDown_o,
input DdsPllLock_i,
inout DdsIOUpdate_io,
output DdsOsk_o,
output DdsDrHold_o,
output DdsSClk_o,
input DdsSDo_i,
output DdsSDio_io,
input DdsRamSwpOvr_i,
output DdsIoReset_or,
output DdsDrCtl_o,
input DdsDrOver_i,
input DdsSyncClk_ik,
input DdsPdClk_ik,
input DdsSyncOut_ik/* synthesis xc_padtype = "IBUFG_LVDS" */,
output DdsSyncIn_ok/* synthesis xc_padtype = "OBUFG_LVDS" */,
// VME P0
output VmeP0BuslineDir_o,
output VmeP0BuslineOe_o,
output VmeP0HwLowByteDir_o,
output VmeP0HwLowByteOe_o,
output VmeP0HwHighByteDir_o,
output VmeP0HwHighByteOe_o,
output VmeP0BunchSelectDir_o,
output VmeP0BunchSelectOe_o,
input VmeP0LvdsBunchClkIn_i,
output VmeP0LvdsBunchClkOut_o,
input VmeP0LvdsTClkIn_i,
output VmeP0LvdsTClkOut_o,
// DDR
output [13:0] DdrA_ob14,
output [2:0] DdrBA_ob3,
inout [15:0] DdrDQ_iob16,
output DdrReset_or,
output DdrCkE_o,
output DdrWe_o,
output DdrCk_ok,
output DdrODT_o,
output DdrRAS_o,
output DdrCAS_o,
output DdrUDM_o,
output DdrLDM_o,
inout DdrLDQS_io,
inout DdrUDQS_io,
// Miscellaneaus
input [7:0] PcbRev_ib8,
// SFP Controls
input WRModeDef0_i,
output WRModeDef1_i,
inout WRModeDef2_io,
output WRRateSelect_o,
output WRTxDisable_o,
input WRTxFault_i,
input WRLoS_i,
input Sfp2ModeDef0_i,
output Sfp2ModeDef1_i,
inout Sfp2ModeDef2_io,
output Sfp2RateSelect,
input Sfp2LoS_i,
output Sfp2TxDisable_o,
input Sfp2TxFault_i,
// FMC controls
output Fmc1PGC2M_in,
input Fmc1PrsntM2C_in,
output Fmc2PGC2M_in,
input Fmc2PrsntM2C_in,
inout Fmc1SDa_io,
output Fmc1SCl_ok,
inout Fmc2SDa_io,
output Fmc2SCl_ok,
// GBit signals
output WRGBitOut_o,
input WRGbitIn_i,
input WRRefClk_ik,
output Sfp2GBitOut_o,
input Sfp2GbitIn_i,
output SataTx_o,
input SataRx_i,
output Gbit1Sys2App_o,
input Gbit1App2Sys_i,
output Gbit2Sys2App_o,
input Gbit2App2Sys_i,
input Gbit12RefClk_ik,
output Gbit3Sys2App_o,
input Gbit3App2Sys_i,
output Gbit4Sys2App_o,
input Gbit4App2Sys_i,
input Gbit34RefClk_ik
);
endmodule
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