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VME FMC Carrier VFC
Commit e723ed57 authored by Andrea Boccardi's avatar Andrea Boccardi
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debug features for SRAM2 in the application FPGA

parent ddc0466d
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Showing with 43 additions and 6 deletions
trunk/hdl/design/AddrDecoderWBApp.v
View file @ e723ed57
......@@ -9,6 +9,10 @@ module AddressDecoderWBApp(
input AckDebugRegs_i,
output reg StbDebugRegs_o,
input [31:0] DatDebugInRegs_ib32,
input AckDebugInRegs_i,
output reg StbDebugInRegs_o,
input [31:0] DatSram1Controller_ib32,
input AckSram1Controller_i,
output reg StbSram1Controller_o,
......@@ -18,14 +22,18 @@ module AddressDecoderWBApp(
output reg StbSram2Controller_o);
always @(posedge Clk_ik) begin
Ack_o <= AckDebugRegs_i || AckSram1Controller_i || AckSram2Controller_i;
Ack_o <= AckDebugInRegs_i || AckDebugRegs_i || AckSram1Controller_i || AckSram2Controller_i;
Dat_ob32 <= 32'h0;
StbDebugRegs_o <= 1'b0;
StbDebugInRegs_o <= 1'b0;
StbSram1Controller_o <= 1'b0;
StbSram2Controller_o <= 1'b0;
if (Adr_ib21[20:2]=='h0) begin // FROM 00_0000 TO 00_0003 (WB) == FROM 80_0000 TO 80_000C (VME) <- 4 regs (16B)
StbDebugRegs_o <= Stb_i;
Dat_ob32 <= DatDebugRegs_ib32;
end else if (Adr_ib21[20:2]=='h1) begin // FROM 00_0004 TO 00_0007 (WB) == FROM 80_0010 TO 80_001C (VME) <- 4 regs (16B)
StbDebugInRegs_o <= Stb_i;
Dat_ob32 <= DatDebugInRegs_ib32;
end else if (Adr_ib21[20:19]==2'h1) begin // FROM 08_0000 TO 0F_FFFF == FROM A0_0000 TO BF_FFFC (VME)
StbSram1Controller_o <= Stb_i;
Dat_ob32 <= DatSram1Controller_ib32;
......
trunk/hdl/design/ApplicationFpga.v
View file @ e723ed57
......@@ -40,6 +40,8 @@ wire [31:0] DatMasterO_b32, DatMasterI_b32;
wire [31:0] DebugReg0, DebugReg1, DebugReg2, DebugReg3;
wire [31:0] DatDebugRegsrO_b32;
wire StbDebugRegs, AckDebugRegs;
wire [31:0] DatDebugInRegsrO_b32;
wire StbDebugInRegs, AckDebugInRegs;
wire StbSram1Controller, AckSram1Controller;
wire [31:0] DatSram1ControllerO_b32;
wire StbSram2Controller, AckSram2Controller;
......@@ -106,7 +108,11 @@ AddressDecoderWBApp i_AddressDecoderWB(
.DatDebugRegs_ib32(DatDebugRegsrO_b32),
.AckDebugRegs_i(AckDebugRegs),
.StbDebugRegs_o(StbDebugRegs),
.DatDebugInRegs_ib32(DatDebugInRegsrO_b32),
.AckDebugInRegs_i(AckDebugInRegs),
.StbDebugInRegs_o(StbDebugInRegs),
.DatSram1Controller_ib32(DatSram1ControllerO_b32),
.AckSram1Controller_i(AckSram1Controller),
.StbSram1Controller_o(StbSram1Controller),
......@@ -119,8 +125,8 @@ AddressDecoderWBApp i_AddressDecoderWB(
// Debug Registers
//#####################################
Generic4OutputRegs #(.Reg0Default(32'ha), .Reg1Default(32'hb), .Reg2Default(32'hc), .Reg3Default(32'hd))
i_DebugRegs(
Generic4OutputRegs #(.Reg0Default(32'h0), .Reg1Default(32'h0), .Reg2Default(32'h0), .Reg3Default(32'h0))
i_DebugOutRegs(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
......@@ -159,6 +165,7 @@ WbToCy7c1470 i_Sram1Controller(
.SramBws_onb4(Sram1Bws_nb4));
/*
wire [20:0] AdrSram2Controller = {2'b0, Adr_b21[18:0]};
WbToCy7c1470 i_Sram2Controller(
......@@ -166,7 +173,7 @@ WbToCy7c1470 i_Sram2Controller(
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.Stb_i(StbSram2Controller),
.We_i(We),
.We_i(We),
.Adr_ib21(AdrSram2Controller),
.Dat_ib32(DatMasterO_b32),
.Dat_ob32(DatSram2ControllerO_b32),
......@@ -176,6 +183,28 @@ WbToCy7c1470 i_Sram2Controller(
.SramClk_ok(Sram2Clk_k),
.SramWe_on(Sram2We_n),
.SramOe_on(Sram2Oe_n),
.SramBws_onb4(Sram2Bws_nb4));
.SramBws_onb4(Sram2Bws_nb4));
*/
assign AckSram2Controller = 1'b0;
assign Sram2Data_b36 = DebugReg1[31] ? {4'b0, DebugReg0} : 36'hz;
assign Sram2Address_b21 = DebugReg1[20:0];
assign Sram2Clk_k = Clk_k;
assign Sram2We_n = ~DebugReg1[31];
assign Sram2Oe_n = DebugReg1[31];
assign Sram2Bws_nb4 = 4'h0;
Generic4InputRegs DebugInRegs (
.Rst_irq(Rst_rq),
.Cyc_i(Cyc),
.Stb_i(StbDebugInRegs),
.Adr_ib2(Adr_b21[1:0]),
.Dat_oab32(DatDebugInRegsrO_b32),
.Ack_oa(AckDebugInRegs),
.Reg0Value_ib32(DebugReg0),
.Reg1Value_ib32(Sram2Data_b36[31:0]),
.Reg2Value_ib32(DebugReg1),
.Reg3Value_ib32({32'hbabebabe}));
endmodule
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