Commit f8166f52 authored by Andrea Boccardi's avatar Andrea Boccardi

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VmeInterface
contains: VME connectors (P0, P1, P2), VME buffers, VME GA bypass
connected to: SystemFpga, PowerSupplies
EthernetInterface
contains: SFP socket, PHY, PLL
connected to : SystemFpga, ClockGeneration, PowerSupplies
DdrMemory
contains: the DDR module
connected to: SystemFpga, PowerSupplies
EepromMemory
contains: the EEPROM module
connected to: SystemFpga, PowerSupplies
SystemFpga
contains: FPGA, EEPROM
conected to: VmeInterface, EthernetInterface, DdrMemory, EepromMemory,
ApplicationFpga, ClockGeneration, Fmc1, Fmc2, PowerSupplies
ApplicationFpga
contains: FPGA
connected to: SystemFpga, Fmc1, Fmc2, ZbtMemory, ClockGeneration,
PowerSupplies
ZbtMemory
contains: ZBT memories
connected to: ApplicationFpga, PowerSupplies
ClockGeneration:
contains: PLL chips, quartz cristal, clock buffers
connected to: SystemFpga, EthernetInterface, ApplicationFpga, Fmc1,
Fmc2, PowerSupplies
Fmc1/2
contains: FMC conector
connected to: ApplicationFpga,SystemFpga, ClockGeneration, PowerSuppliesPowerSupplies
contains: DC/DC switcting converters, filtering components, bypass logic
Connected to: ALL the modules
Release 12.3 ngdbuild M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\12.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc ApplicationFpga.ucf -p
xc6slx150t-fgg676-3 ApplicationFpga.ngc ApplicationFpga.ngd
Reading NGO file
"C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "ApplicationFpga.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgM_iob2<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgD_iob8<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgClk_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgCsi_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgRdWr_io' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'AFpgaProgInit_io' has no legal driver
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 7
Total memory usage is 148820 kilobytes
Writing NGD file "ApplicationFpga.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec
Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "ApplicationFpga.bld"...
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Release 12.3 par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
PCBE13225:: Tue Feb 01 08:49:34 2011
par -w -intstyle ise -ol high -mt off ApplicationFpga_map.ncd
ApplicationFpga.ncd ApplicationFpga.pcf
Constraints file: ApplicationFpga.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment C:\Xilinx\12.3\ISE_DS\ISE\.
"ApplicationFpga" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.12c 2010-09-15".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 496 out of 184,304 1%
Number used as Flip Flops: 496
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 210 out of 92,152 1%
Number used as logic: 159 out of 92,152 1%
Number using O6 output only: 122
Number using O5 output only: 14
Number using O5 and O6: 23
Number used as ROM: 0
Number used as Memory: 23 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 23
Number using O6 output only: 7
Number using O5 output only: 0
Number using O5 and O6: 16
Number used exclusively as route-thrus: 28
Number with same-slice register load: 27
Number with same-slice carry load: 1
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 134 out of 23,038 1%
Number of LUT Flip Flop pairs used: 468
Number with an unused Flip Flop: 22 out of 468 4%
Number with an unused LUT: 258 out of 468 55%
Number of fully used LUT-FF pairs: 188 out of 468 40%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 151 out of 396 38%
Number of LOCed IOBs: 151 out of 151 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 268 0%
Number of RAMB8BWERs: 0 out of 536 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 0 out of 586 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 0 out of 586 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 10 secs
Finished initial Timing Analysis. REAL time: 10 secs
WARNING:Par:288 - The signal AFpgaProgClk_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgRdWr_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgD_iob8<6>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgCsi_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgInit_io_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal AFpgaProgM_iob2<1>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 1683 unrouted; REAL time: 11 secs
Phase 2 : 1403 unrouted; REAL time: 15 secs
Phase 3 : 430 unrouted; REAL time: 18 secs
Phase 4 : 430 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 24 secs
Updating file: ApplicationFpga.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs
Total REAL time to Router completion: 25 secs
Total CPU time to Router completion: 24 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|SysAppClk_ik_IBUF_BU | | | | | |
| FG | BUFGMUX_X2Y1| No | 124 | 0.196 | 1.696 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_SysAppClk_ik = PERIOD TIMEGRP "SysAppC | SETUP | 1.876ns| 6.457ns| 0| 0
lk_ik" 120 MHz HIGH 50% | HOLD | 0.375ns| | 0| 0
----------------------------------------------------------------------------------------------------------
All constraints were met.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 27 secs
Total CPU time to PAR completion: 26 secs
Peak Memory Usage: 526 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 9
Number of info messages: 0
Writing design to file ApplicationFpga.ncd
PAR done!
verilog work "../../../hdl/design/WbToCy7c1470.v"
verilog work "../../../hdl/design/Ser2MstWB.v"
verilog work "../../../hdl/design/Generic4OutputRegs.v"
verilog work "../../../hdl/design/Debouncer.v"
verilog work "../../../hdl/design/AddrDecoderWBApp.v"
verilog work "../../../hdl/design/ApplicationFpga.v"
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2010/12/20
NET "SysAppClk_ik" TNM_NET = "SysAppClk_ik";
TIMESPEC TS_SysAppClk_ik = PERIOD "SysAppClk_ik" 120 MHz HIGH 50 %;
NET "AFpgaProgClk_io" LOC = AE24;
NET "AFpgaProgCsi_io" LOC = AF23;
NET "AFpgaProgD_iob8[0]" LOC = AD23;
NET "AFpgaProgD_iob8[1]" LOC = V18;
NET "AFpgaProgD_iob8[2]" LOC = W19;
NET "AFpgaProgD_iob8[3]" LOC = AD6;
NET "AFpgaProgD_iob8[4]" LOC = AF6;
NET "AFpgaProgD_iob8[5]" LOC = W8;
NET "AFpgaProgD_iob8[6]" LOC = W7;
NET "AFpgaProgD_iob8[7]" LOC = AA10;
NET "AFpgaProgInit_io" LOC = AE3;
NET "AFpgaProgM_iob2[0]" LOC = AF24;
NET "AFpgaProgM_iob2[1]" LOC = AD22;
NET "AFpgaProgRdWr_io" LOC = AB11;
NET "FpGpIo_iob4[1]" LOC = G3;
NET "FpGpIo_iob4[2]" LOC = G4;
NET "FpGpIo_iob4[3]" LOC = F1;
NET "FpGpIo_iob4[4]" LOC = F3;
NET "PushButton_ion" LOC = H20;
NET "SysAppClk_ik" LOC = U23;
NET "SysAppClk_ok" LOC = U24;
NET "SysAppSlow_iob2[1]" LOC = AF22;
NET "SysAppSlow_iob2[2]" LOC = AF3;
# PlanAhead Generated physical constraints
NET "Sram1Address_b21[0]" LOC = P17;
NET "Sram1Address_b21[1]" LOC = P19;
NET "Sram1Address_b21[2]" LOC = R18;
NET "Sram1Address_b21[3]" LOC = V20;
NET "Sram1Address_b21[4]" LOC = V21;
NET "Sram1Address_b21[5]" LOC = T19;
NET "Sram1Address_b21[6]" LOC = U20;
NET "Sram1Address_b21[7]" LOC = U21;
NET "Sram1Address_b21[8]" LOC = R19;
NET "Sram1Address_b21[9]" LOC = N3;
NET "Sram1Address_b21[10]" LOC = L3;
NET "Sram1Address_b21[11]" LOC = M4;
NET "Sram1Address_b21[12]" LOC = L4;
NET "Sram1Address_b21[13]" LOC = K1;
NET "Sram1Address_b21[14]" LOC = N2;
NET "Sram1Address_b21[15]" LOC = L2;
NET "Sram1Address_b21[16]" LOC = M3;
NET "Sram1Address_b21[17]" LOC = H1;
NET "Sram1Address_b21[18]" LOC = J1;
NET "Sram1Address_b21[19]" LOC = K3;
NET "Sram1Address_b21[20]" LOC = J3;
NET "Sram1Bws_nb4[0]" LOC = AD26;
NET "Sram1Bws_nb4[1]" LOC = AC25;
NET "Sram1Bws_nb4[2]" LOC = AE26;
NET "Sram1Bws_nb4[3]" LOC = AE25;
NET "Sram1Clk_k" LOC = U19;
NET "Sram1Data_b36[0]" LOC = T24;
NET "Sram1Data_b36[1]" LOC = U22;
NET "Sram1Data_b36[2]" LOC = T20;
NET "Sram1Data_b36[3]" LOC = T22;
NET "Sram1Data_b36[4]" LOC = R21;
NET "Sram1Data_b36[5]" LOC = R23;
NET "Sram1Data_b36[6]" LOC = R20;
NET "Sram1Data_b36[7]" LOC = P21;
NET "Sram1Data_b36[8]" LOC = AA26;
NET "Sram1Data_b36[9]" LOC = Y26;
NET "Sram1Data_b36[10]" LOC = V26;
NET "Sram1Data_b36[11]" LOC = U25;
NET "Sram1Data_b36[12]" LOC = U26;
NET "Sram1Data_b36[13]" LOC = T26;
NET "Sram1Data_b36[14]" LOC = W25;
NET "Sram1Data_b36[15]" LOC = W26;
NET "Sram1Data_b36[16]" LOC = AC23;
NET "Sram1Data_b36[17]" LOC = AD24;
NET "Sram1Data_b36[18]" LOC = AC24;
NET "Sram1Data_b36[19]" LOC = AB24;
NET "Sram1Data_b36[20]" LOC = AA24;
NET "Sram1Data_b36[21]" LOC = Y24;
NET "Sram1Data_b36[22]" LOC = W24;
NET "Sram1Data_b36[23]" LOC = V23;
NET "Sram1Data_b36[24]" LOC = V24;
NET "Sram1Data_b36[25]" LOC = D1;
NET "Sram1Data_b36[26]" LOC = D3;
NET "Sram1Data_b36[27]" LOC = T23;
NET "Sram1Data_b36[28]" LOC = R24;
NET "Sram1Data_b36[29]" LOC = E3;
NET "Sram1Data_b36[30]" LOC = E4;
NET "Sram1Data_b36[31]" LOC = P22;
NET "Sram1Data_b36[32]" LOC = P26;
NET "Sram1Data_b36[33]" LOC = AA25;
NET "Sram1Data_b36[34]" LOC = AA23;
NET "Sram1Data_b36[35]" LOC = P24;
NET "Sram1Oe_n" LOC = AB26;
NET "Sram1We_n" LOC = AC26;
NET "Sram2Address_b21[0]" LOC = N6;
NET "Sram2Address_b21[1]" LOC = N7;
NET "Sram2Address_b21[2]" LOC = V6;
NET "Sram2Address_b21[3]" LOC = U8;
NET "Sram2Address_b21[4]" LOC = R10;
NET "Sram2Address_b21[5]" LOC = V7;
NET "Sram2Address_b21[6]" LOC = T9;
NET "Sram2Address_b21[7]" LOC = U9;
NET "Sram2Address_b21[8]" LOC = C1;
NET "Sram2Address_b21[9]" LOC = N4;
NET "Sram2Address_b21[10]" LOC = M9;
NET "Sram2Address_b21[11]" LOC = N9;
NET "Sram2Address_b21[12]" LOC = P8;
NET "Sram2Address_b21[13]" LOC = R8;
NET "Sram2Address_b21[14]" LOC = B1;
NET "Sram2Address_b21[15]" LOC = N5;
NET "Sram2Address_b21[16]" LOC = M10;
NET "Sram2Address_b21[17]" LOC = N8;
NET "Sram2Address_b21[18]" LOC = P10;
NET "Sram2Address_b21[19]" LOC = R9;
NET "Sram2Address_b21[20]" LOC = R6;
NET "Sram2Bws_nb4[0]" LOC = AC2;
NET "Sram2Bws_nb4[1]" LOC = AD1;
NET "Sram2Bws_nb4[2]" LOC = AC1;
NET "Sram2Bws_nb4[3]" LOC = AB1;
NET "Sram2Clk_k" LOC = Y6;
NET "Sram2Data_b36[0]" LOC = P3;
NET "Sram2Data_b36[1]" LOC = Y3;
NET "Sram2Data_b36[2]" LOC = P1;
NET "Sram2Data_b36[3]" LOC = W5;
NET "Sram2Data_b36[4]" LOC = U3;
NET "Sram2Data_b36[5]" LOC = U4;
NET "Sram2Data_b36[6]" LOC = B2;
NET "Sram2Data_b36[7]" LOC = T4;
NET "Sram2Data_b36[8]" LOC = AC3;
NET "Sram2Data_b36[9]" LOC = AB5;
NET "Sram2Data_b36[10]" LOC = AA4;
NET "Sram2Data_b36[11]" LOC = AB3;
NET "Sram2Data_b36[12]" LOC = Y5;
NET "Sram2Data_b36[13]" LOC = AA3;
NET "Sram2Data_b36[14]" LOC = AB4;
NET "Sram2Data_b36[15]" LOC = AD3;
NET "Sram2Data_b36[16]" LOC = Y1;
NET "Sram2Data_b36[17]" LOC = AA1;
NET "Sram2Data_b36[18]" LOC = W1;
NET "Sram2Data_b36[19]" LOC = W2;
NET "Sram2Data_b36[20]" LOC = U2;
NET "Sram2Data_b36[21]" LOC = V1;
NET "Sram2Data_b36[22]" LOC = E1;
NET "Sram2Data_b36[23]" LOC = U1;
NET "Sram2Data_b36[24]" LOC = U5;
NET "Sram2Data_b36[25]" LOC = V3;
NET "Sram2Data_b36[26]" LOC = T6;
NET "Sram2Data_b36[27]" LOC = T8;
NET "Sram2Data_b36[28]" LOC = R4;
NET "Sram2Data_b36[29]" LOC = R5;
NET "Sram2Data_b36[30]" LOC = P5;
NET "Sram2Data_b36[31]" LOC = P6;
NET "Sram2Data_b36[32]" LOC = R3;
NET "Sram2Data_b36[33]" LOC = AC4;
NET "Sram2Data_b36[34]" LOC = AA2;
NET "Sram2Data_b36[35]" LOC = E2;
NET "Sram2Oe_n" LOC = AE2;
NET "Sram2We_n" LOC = AE1;
Release 12.3 - par M.70d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Tue Feb 01 08:50:01 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
AFpgaProgClk_io_IBUF
AFpgaProgCsi_io_IBUF
AFpgaProgD_iob8<6>_IBUF
AFpgaProgInit_io_IBUF
AFpgaProgM_iob2<0>_IBUF
AFpgaProgM_iob2<1>_IBUF
AFpgaProgRdWr_io_IBUF
-w
-g DebugBitstream:No
-g Binary:yes
-b
-g IEEE1532:Yes
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:26
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF