VME FMC Carrier VFC issueshttps://ohwr.org/project/fmc-vme-carrier/issues2019-02-12T08:43:41Zhttps://ohwr.org/project/fmc-vme-carrier/issues/36TTLBunchClk and TTLTClk signals on the P0 are forced as input for the carrier.2019-02-12T08:43:41ZAndrea BoccardiTTLBunchClk and TTLTClk signals on the P0 are forced as input for the carrier.The direction of those 2 signals was set by default to input for the
carrier with a pull down.
Was foreseen to be able to change it from the System FPGA, but the
connection is missing for both.https://ohwr.org/project/fmc-vme-carrier/issues/35Name inversion between the control signals of the P0 HWHIGHBYTE and HWLOWBYTE2019-02-12T08:43:40ZAndrea BoccardiName inversion between the control signals of the P0 HWHIGHBYTE and HWLOWBYTEThe names on the schematic has been crossed: VMEP0\_HWHIGHBYTE\_OE and
VMEP0\_HWHIGHBYTE\_DIR should be named respectively VMEP0\_HWLOWBYTE\_OE
and VMEP0\_HWLOWBYTE\_DIR and vice versa.https://ohwr.org/project/fmc-vme-carrier/issues/34Missing connection to control the output enable of the VMEP0_LVDSTCLK and VME...2019-02-12T08:43:40ZAndrea BoccardiMissing connection to control the output enable of the VMEP0_LVDSTCLK and VMEP0_LVDSBUNCHCLKThe output enable pins on IC23 are left floating.
This will require a wire connection to ground or to the pin 7 of the SW1
if we want to keep the controllabilityhttps://ohwr.org/project/fmc-vme-carrier/issues/33Inverted polarity of DDS_OUT LVDS signal2019-02-12T08:43:39ZAndrea BoccardiInverted polarity of DDS_OUT LVDS signalThis will cause a 180 degree shift in the generated signalhttps://ohwr.org/project/fmc-vme-carrier/issues/32Design out RAKON IVT3205CR 25.0 MHz as too difficult to obtain.2019-02-12T08:43:39ZErik van der BijDesign out RAKON IVT3205CR 25.0 MHz as too difficult to obtain.Find replacement for Rakon oscillator and update design.Andrea BoccardiAndrea Boccardihttps://ohwr.org/project/fmc-vme-carrier/issues/31NUMONYX M25P128-VMF6G difficult to find2019-02-12T08:43:38ZErik van der BijNUMONYX M25P128-VMF6G difficult to findSee https://www.ohwr.org/work_packages/119
Update schematics and design files.Andrea BoccardiAndrea Boccardihttps://ohwr.org/project/fmc-vme-carrier/issues/30Do not mount PT6914 and PT6915 negative supplies2019-02-12T08:43:37ZErik van der BijDo not mount PT6914 and PT6915 negative suppliesThese components are hard to obtain (delivery time over 18 weeks) and
costly. Currently no applications are known that use the negative
supplies that would be put on the FMC connector. It would be violating
the FMC spec anyway.
These components are not ordered for the first large scale production.Andrea BoccardiAndrea Boccardihttps://ohwr.org/project/fmc-vme-carrier/issues/29V1: PCB layout problem resulting in solder between pins2019-02-12T08:43:36ZErik van der BijV1: PCB layout problem resulting in solder between pinsOn several IC's, like IC5, IC7, IC9, some pins are connected to the mass
fill. Despite that there should be a solder mask present, on the
prototypes one finds neighbouring pins that both are connected to this
fill have solder between them.
Correct this layout for V2 of the boards.Andrea BoccardiAndrea Boccardihttps://ohwr.org/project/fmc-vme-carrier/issues/28Add configuration jumpers to SFPGA's HSWAPEN2019-02-12T08:43:36ZPablo AlvarezAdd configuration jumpers to SFPGA's HSWAPENHSWAPEN is tied to ground, forcing the system FPGA IOs to pull-up while
being configured via JTAG. At this moment the IRQ and BERR lines are
asserted provoking a reboot on the CPU (MEN-A20). This behaviour could
be fixed by connecting HSWAPEN to VCC and connecting the corresponding
default pull-ups and pull-downs on the SFPGA IOs.https://ohwr.org/project/fmc-vme-carrier/issues/27A 100nF on the Vref of the AD5666 would improve the reference stability2019-02-12T08:43:35ZAndrea BoccardiA 100nF on the Vref of the AD5666 would improve the reference stabilityhttps://ohwr.org/project/fmc-vme-carrier/issues/261-wire chip package should be changed2019-02-12T08:43:35ZAndrea Boccardi1-wire chip package should be changedReplace the DS18B20U+ with a DS18B20V+https://ohwr.org/project/fmc-vme-carrier/issues/25Difficulties in soldering the FMC connectors2019-02-12T08:43:34ZAndrea BoccardiDifficulties in soldering the FMC connectorsThe assembly workshop at CERN is having serious issues soldering the FMC
connector.
Many pins in the inner rows are not connected. The problem seems
localized mainly on rows b, c,d, ehttps://ohwr.org/project/fmc-vme-carrier/issues/24place pull ups and down on the pin modes of the S-FPGA2019-02-12T08:43:34ZAndrea Boccardiplace pull ups and down on the pin modes of the S-FPGAThe mode pins could be set as user io in case of errors in the UCF file.
It is safer to have them as pull up(down)https://ohwr.org/project/fmc-vme-carrier/issues/23AC couple the SFP2019-02-12T08:43:33ZAndrea BoccardiAC couple the SFPPlace AC coupling on the SFPs' high speed signalshttps://ohwr.org/project/fmc-vme-carrier/issues/22Place the VME-ADDR buffers by default in BUS to Carrier direction2019-02-12T08:43:33ZAndrea BoccardiPlace the VME-ADDR buffers by default in BUS to Carrier directionPlace the VME-ADDR buffers by default in BUS to Carrier direction. At
the moment they are by default simply in hi-zhttps://ohwr.org/project/fmc-vme-carrier/issues/21Replace the on off indication (serigraphy) on the manual address switch with ...2019-02-12T08:43:32ZAndrea BoccardiReplace the on off indication (serigraphy) on the manual address switch with 1 and 0Replace the on off indication (serigraphy) on the manual address switch
with 1 and 0.
The on off indication is misleading as inverted with respect to the
switch own indication.https://ohwr.org/project/fmc-vme-carrier/issues/20Foresee the possibility to have the BST signals (2 bytes) and clocks either f...2019-02-12T08:43:32ZAndrea BoccardiForesee the possibility to have the BST signals (2 bytes) and clocks either from the P0 or from the S-FPGA (jumpers?)Foresee the possibility to have the BST signals (2 bytes) and clocks
either from the P0 or from the S-FPGA (jumpers?)https://ohwr.org/project/fmc-vme-carrier/issues/19Add a CDR chip optionally connected (AC coupling switch) to one of the 2 SFP2019-02-12T08:43:31ZAndrea BoccardiAdd a CDR chip optionally connected (AC coupling switch) to one of the 2 SFPAdd a CDR chip (AN2812) optionally connected (AC coupling switch) to one
of the 2 SFPhttps://ohwr.org/project/fmc-vme-carrier/issues/18Missing RZQ calibration resistor for DDR termination2019-02-12T08:43:31ZProjectsMissing RZQ calibration resistor for DDR terminationA 100ohm resistor to GND must be added on one of the following pins:
N17, U21, T19, T20, AA23, AA24, U19, U20, V20https://ohwr.org/project/fmc-vme-carrier/issues/17Connect ddr3 address pin 142019-02-12T08:43:30ZProjectsConnect ddr3 address pin 14For compatibility with higher memory capacity, connect S-FPGA pin L24
(A14) to DDR3 pin T7 with a 51ohm pull-up to VTTDDR.
See SPEC board schematics.