VME FMC Carrier VFC issueshttps://ohwr.org/project/fmc-vme-carrier/issues2019-02-12T08:43:23Zhttps://ohwr.org/project/fmc-vme-carrier/issues/1V2-0: Front-panel BOM wrong2019-02-12T08:43:23ZErik van der BijV2-0: Front-panel BOM wrong- Review arrangement-mat BOM. Refer to SVEC design.
See issue https://www.ohwr.org/work_packages/660 of the SVEC.
Also one can find in the BOM of the VFC a microswitch that is not used.
Need the following items:
- ELMA 66-514-26 - EMC Front Panels - Aluminium With EMC Gasket acc.
IEEE - Thickness 2.5m
- (actually the EMC Gasket is *not* included, despite the
description).
- ELMA 81-062-06 - EMC Gasket
- ELMA 81-095 - Top Black Handle with ESD Pin and Red button (includes
fixing screws to PCB)
- ELMA 81-096 - Bottom Black Handle with ESD Pin and Red Button
(includes fixing screws to PCB)
- ELMA 61-295 - Round head screw, cross recessed M2.5 x 12.7 - (two
needed)Andrea BoccardiAndrea Boccardihttps://ohwr.org/project/fmc-vme-carrier/issues/2Design files in Repository old2019-02-12T08:43:23ZErik van der BijDesign files in Repository oldThe design files in the Repository describe V1-0. In EDMS the files are
of EDA-02030-V2-0. This has actually caused problems to a user.
- Update files in the repositoryAndrea BoccardiAndrea Boccardihttps://ohwr.org/project/fmc-vme-carrier/issues/3VMEPX_DS lines swaped on vme connector2019-02-12T08:43:24ZPablo AlvarezVMEPX_DS lines swaped on vme connectorVMEPX\_DS1 and VMEPX\_DS2 should be swapped to follow VME standard
notation. Additionally in the VME standard are named DS0 and DS1
respectively.https://ohwr.org/project/fmc-vme-carrier/issues/4DDS not debugged2019-02-12T08:43:24ZErik van der BijDDS not debuggedThe DDS has not been debugged yet. R/W to registers are working, but the
functionality has not been tested yet.https://ohwr.org/project/fmc-vme-carrier/issues/5DDR3 access problems2019-02-12T08:43:25ZErik van der BijDDR3 access problemsAccessing the DDR3 with the same core as used on the SPEC card doesn't
work. After several correct write and read cycles, the DDR3 returns all
F as data, likely caused by an unexpected recalibration cycle initiated
for unknown reasons.
Causes can be various (missing calibration resistor, unequal length A/D
lines, reflections, problems with Vref after starting up).
Needs debugging before design of V2.https://ohwr.org/project/fmc-vme-carrier/issues/6VME 2eSST cycles not proven to work2019-02-12T08:43:25ZErik van der BijVME 2eSST cycles not proven to workThe board has never used 2eSST and block transfer cycles.
Debugging of it has been interrupted after the Sprint debugging period.
May decide to leave as signal R/W have shown to be working.https://ohwr.org/project/fmc-vme-carrier/issues/7Solve JTAG problems2019-02-12T08:43:25ZProjectsSolve JTAG problemsMake shorter chains.
Consider using a buffer to slow down the edges.
Xilinx platform cable USB II has fast buffer causing reflection on the
lines.https://ohwr.org/project/fmc-vme-carrier/issues/8Unreliable PTH04T230W soldering2019-02-12T08:43:26ZProjectsUnreliable PTH04T230W solderingConsider using the thu-hole version or changing the type.https://ohwr.org/project/fmc-vme-carrier/issues/9Follow PCB layout guidelines for DDR3 routing.2019-02-12T08:43:26ZProjectsFollow PCB layout guidelines for DDR3 routing.See http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
from page 41.
Trace length might be matched.https://ohwr.org/project/fmc-vme-carrier/issues/10Review inter-FPGA GTP clocking2019-02-12T08:43:27ZProjectsReview inter-FPGA GTP clockinghttps://ohwr.org/project/fmc-vme-carrier/issues/11Programming the system FPGA crashes/reboots the MEN-A202019-02-12T08:43:27ZProjectsProgramming the system FPGA crashes/reboots the MEN-A20If the system FPGA is programmed while the vmebus driver is loaded, the
MEN-A20 crashes/reboots.
This might be due to some glitches on VME bus lines during FPGA
configuration.
Further investigation is needed.https://ohwr.org/project/fmc-vme-carrier/issues/12Oscillators for WR2019-02-12T08:43:28ZTomasz WlostowskiOscillators for WRUse the same oscillator layout as in the SPEC v2. Connect the 25 MHz
oscillator directly to the REF input of IC18.https://ohwr.org/project/fmc-vme-carrier/issues/13PLL oscillators2019-02-12T08:43:28ZTomasz WlostowskiPLL oscillatorsThere is no PLL in the design which would have an independent oscillator
connected to the reference input. Instead all of them are using FPGA
outputs as reference clocks. This is not a good practice.https://ohwr.org/project/fmc-vme-carrier/issues/14[CRITICAL] Tx/Rx pairs swapped in SFP1 and SFP22019-02-12T08:43:29ZTomasz Wlostowski[CRITICAL] Tx/Rx pairs swapped in SFP1 and SFP2GTP I/Os for SFP1, SFP2 in the system FPGA are reversed.https://ohwr.org/project/fmc-vme-carrier/issues/15P2 user defined connections2019-02-12T08:43:29ZAndrea BoccardiP2 user defined connectionsIn the chosen FPGAs only IO of banks 0 and 2 can be configured as LVDS
outputs. Those banks are used for the 2 FMCs, the pins connected to the
P2 user defined lines cannot be used as LVDS outputs.
NOTE: the pins can be used as LVDS inputs.https://ohwr.org/project/fmc-vme-carrier/issues/16eSATA connector2019-02-12T08:43:30ZAndrea BoccardieSATA connectorThe eSATA front panel connector cannot be mounted or the carrier will
need to use 2 slots.
The connector was foreseen to be used in case of stand alone application
in a 'pizza-box' container. Indeed no space for it was foreseen on the
produced front panels.https://ohwr.org/project/fmc-vme-carrier/issues/17Connect ddr3 address pin 142019-02-12T08:43:30ZProjectsConnect ddr3 address pin 14For compatibility with higher memory capacity, connect S-FPGA pin L24
(A14) to DDR3 pin T7 with a 51ohm pull-up to VTTDDR.
See SPEC board schematics.https://ohwr.org/project/fmc-vme-carrier/issues/18Missing RZQ calibration resistor for DDR termination2019-02-12T08:43:31ZProjectsMissing RZQ calibration resistor for DDR terminationA 100ohm resistor to GND must be added on one of the following pins:
N17, U21, T19, T20, AA23, AA24, U19, U20, V20https://ohwr.org/project/fmc-vme-carrier/issues/19Add a CDR chip optionally connected (AC coupling switch) to one of the 2 SFP2019-02-12T08:43:31ZAndrea BoccardiAdd a CDR chip optionally connected (AC coupling switch) to one of the 2 SFPAdd a CDR chip (AN2812) optionally connected (AC coupling switch) to one
of the 2 SFPhttps://ohwr.org/project/fmc-vme-carrier/issues/20Foresee the possibility to have the BST signals (2 bytes) and clocks either f...2019-02-12T08:43:32ZAndrea BoccardiForesee the possibility to have the BST signals (2 bytes) and clocks either from the P0 or from the S-FPGA (jumpers?)Foresee the possibility to have the BST signals (2 bytes) and clocks
either from the P0 or from the S-FPGA (jumpers?)