Foresee the possibility to have the BST signals (2 bytes) and clocks either from the P0 or from the S-FPGA (jumpers?)
Foresee the possibility to have the BST signals (2 bytes) and clocks either from the P0 or from the S-FPGA (jumpers?)
Foresee the possibility to have the BST signals (2 bytes) and clocks either from the P0 or from the S-FPGA (jumpers?)