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Andrea Boccardi authored
Some Verilog file had to be modified, simulation to be checked
23b1b4b5
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bitgen.xmsgs | ||
ibiswriter.xmsgs | ||
map.xmsgs | ||
ngdbuild.xmsgs | ||
par.xmsgs | ||
pn_parser.xmsgs | ||
trce.xmsgs | ||
xst.xmsgs |
Some Verilog file had to be modified, simulation to be checked
Name |
Last commit
|
Last update |
---|---|---|
.. | ||
bitgen.xmsgs | Loading commit data... | |
ibiswriter.xmsgs | Loading commit data... | |
map.xmsgs | Loading commit data... | |
ngdbuild.xmsgs | Loading commit data... | |
par.xmsgs | Loading commit data... | |
pn_parser.xmsgs | Loading commit data... | |
trce.xmsgs | Loading commit data... | |
xst.xmsgs | Loading commit data... |