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VME FMC Carrier VFC
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VME FMC Carrier VFC
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Mar 15, 2019
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VME FMC carrier
2 Spartan6 FPGA
One dedicated to system tasks (S-FPGA)
One fully available for the user applications (A-FPGA)
2 LPC (Low Pin Count) FMC slots
40 user defined single ended (20 LVDS) connections from the A-FPGA to P2 available for rear plug-in units (transition modules)
flexible clocking resources
1 Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO)
1 any rate I2C programmable crystal oscillator
1 Direct Digital Synthesizer (DDS)
3 Phase Locked Loop (PLL) chips for clock cleaning and redistribution to the FPGAs and the pluggable modules
Large amount of on board memory
2 completely independent 72Mbit ZBT SRAMS
A 2Gbit DDR3
2 SPI 128Mbit flash proms for multiboot S-FPGA powerup configuration, storage of the A-FPGA firmware or of critical data
Front panel connectivity
2 Small Formfactor Pluggable (SFP)
4 lemos configurable in all possible input/output combinations
1 e-SATA (only in non-VME applications)
12 layer printed circuit board
Official design data
LHC equipment name: CVORK
Controls Configuration Database entry
Controls EDMS page
bill of material:
Manufacturing test suite
List of (potential) users of the VFC
PCB layout started
Vadj fixed to 2.5V for FMC slot 2 to solve problems with bank power supplies.
All active components ordered.
Layout files received and being reviewed.
PCB layout review held.
PCB layout good for production.
Simulation started. Many troubles getting connectivity files out of schematics. Redo by hand.
PCB being produced at CERN. Expect assembled boards by mid October.
Two PCB's being assembled. A third one will come later.
Problem with solder mask for 0402 capacitors under BGA detected. PCB specification will be changed.
1st prototype received, waiting for the front panel.
1st prototype powered: 3 DC/DC are not working.
2nd and 3rd prototype received: one powered and no issues on the PS this time
Test code loaded in the System FPGA and PROM programmed. JTAG and PROM loading are working. VME access OK.
Ten additional boards produced. Two reworked and work, but have JTAG issues. Eight still need rework.
Modifications to layout required. Can start in two to three weeks time.
to debug the hardware design. 4 engineers intensively working on it, following the
to debug hardware design. Uncovered 18 Issues. DDR3 memory and DDS not debugged yet.
New version of schematics ready.
Schematics design review held
. The design office will layout from 24 August on.
Schematics still being updated. The design office will layout from 19 September on.
V2 layout ready. Needs schematics and PCB review.
V2 schematics and PCB review held.
Will produce 20 PCBs. First only 10 will be assembled.
Expect assembled boards by mid-December.
Andrea Boccardi, Erik van der Bij - 16 November 2011
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