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Meeting20100211

Last edited by Andrea Boccardi Mar 09, 2010
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Meeting20100211techspec(schematic)review

During the review the following points have been risen:

  • The choice of the lemo as front panel connector should be reviewed
  • The FMC standard ask for a 10kΩ to 3.3V on the power good line <- DONE
  • The use of the Si571 as clock source should be investigated
  • It might exist single chip solutions from TI for the Vadj
  • The inhibit line of the Vadj DC-DC should be used and connected the S-FPGA <- DONE
  • The communication between the 2 FPGAs could be implemented in PCIe standard. This might have implications on the choice of the GTPs to be used
  • The FMC PLLs should deliver one output also to the S-FPGA for WR applications <- DONE
  • It might be nice to have a 2nd oscillator
  • There should be the possibility to isolate the mezzanines also from the P2
  • Buffers should be used on the FP GPIOs
  • The necessity of buffers on the P0 data lines should be verified
  • Doubts have been risen about the LDO regulator: are 300mV from in to out really enough? <- DONE (max drop is 150mV up to 3A and 125 degrees)
  • There should be the possibility to put the SRAMs in the JTAG chain with the FPGAs
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