FPGA Configuration Space Specification
This project is an effort to introduce a configuration space specification for internal FPGA buses (interconnects, crossbars). Our initial target is Wishbone, but the specification is generic. The output of this project is called SDB (self describing bus) even if the project (thus the repository) is called fpga-config-space.
SDB allows to enumerate the cores that are live in the current fpga binary, either from the host computer or from the internal soft-core CPU in the FPGA itself.
The current specification is already in use in some of our designs. And we have some sdb implementation guidelines
Specification
Version 1.0 of SDB the specification is available in PDF
format, together with the header
file.
It has been built from the repository of this project, so you can get
the git tree instead and run Latex on it.
Interrupt support
We chose, for the time being, to not describe interrupts. After some
drafts for one such description, Wesley Terpstra
explained why legacy interrupts should be avoided in a SoC design and
MSI-like interrupts don't need an external description.
His complete reasoning is here: Interrupts
Code
The implementation as VHDL is part of the respective projects (currently, Etherbone and White Rabbit Core).
Code for the Linux kernel (both as a bus driver and a file system
driver) is being written. Available code
is part of this repository, but it's still work in progress.
Status
Date | Event |
09-05-2011 | Start of project |
09-05-2011 | Added draft of specification (available in Repository section) |
10-05-2011 | Added code for wishbone simulator (source code available in Repository or Files section) |
21-06-2012 | After long discussions, the specification is published |