FPGA Device Identification
Project description
Rules for low-level software to check an FPGA for sanity, to ease debugging and to provide support for low-level software auto-configuration for byte-order and optional components. See FPGAInterfaceDesign.pdf for details.
Project information
Known Identifiers
Vendor ID | Device ID | Description |
---|---|---|
h000010DC | h53504543 | SPEC |
h000010DC | h53564543 | SVEC |
h000010DC | h54535431 | SVEC VME Testing |
h000010DC | h574f0001 | SPEC + Fine-Delay 1ns 4ch |
h000010DC | h574f0002 | SVEC + Double Fine-Delay 1ns 4ch |
h000010DC | h574E0001 | SPEC + TDC 1ns 5ch |
h000010DC | h574E0002 | SVEC + Double TDC 1ns 5ch |
h000010DC | h41444301 | SPEC + ADC 100M 14b 4ch |
h000010DC | h41444302 | SVEC + Double ADC 100M 14b 4ch |
h000010DC | h57544E01 | SPEC + WRTD + ADC 100M 14b 4ch |
h000010DC | h57544E02 | SVEC + WRTD + TDC 1ns 5ch + Fine-Delay 1ns 4ch |
h000010DC | h57544E03 | SVEC + Double TDC 1ns 5ch |
h000010DC | h57544E04 | SVEC + Double Fine-Delay 1ns 4ch |
h000010DC | h57544E05 | SVEC + Double ADC 100M 14b 4ch |
h000010DC | h5452544C | Mockturle demo |
Note For WRTD applications, we reserve the 24 most significant bits in the device ID: h57544Exx
Note For testing applications, we reserve the 24 most significant bits in the device ID: h545354xx
Contacts
- Federico Vaga - CERN
Status
Date | Event |
---|---|
24-10-2019 | First version of Device structure document. |
24 April 2020