VHDL Style Guide
Project description
The aim of this set of rules is to help the low-level software to perform a sanity check on an FPGA device, to ease debugging and to provide support for low-level software auto-configuration for byte-order and optional components.
Template below - Please correct and have an image or clear example (Device Metadata table?) below to give a quick impression
A text document contains a list of rules, like:
==== [PortsName] [M] Ports name
Ports name must be in lower case (as ruled by Identifiers), but must also have
a suffix:
* '_i' for normal input.
* '_o' for normal output.
* '_b' for bidirectional port.
The suffix must be the last one.
Reason: Helps to specify the purpose of a port, makes the dataflow more
obvious.
A tool has been developed to automatically enforce the rules. For this file:
library ieee;
use ieee.std_logic_1164.all;
entity example is
port (clk_i : in std_logic;
incorrect : out std_logic);
end example;
The tool will generate this message for the above rule:
./ex1.vhdl:6:9: [PortsName] out port 'incorrect' must end with '_o'
Project information
- VHDL Style Guide (pdf generated from the master) or text description (the master)
Contacts
- Federico Vaga - CERN
Status
Date | Event |
---|---|
24-10-2019 | First version of Device structure document. |
24 October 2019