--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- General Cores Library
-- https://www.ohwr.org/projects/general-cores
--------------------------------------------------------------------------------
--
-- unit name:   wb_slave_vic
--
-- description: Wishbone slave core for Vectored Interrupt Controller (VIC)
-- block layout (wbgen2)
--
--------------------------------------------------------------------------------
-- Copyright CERN 2013-2018
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------

-- -*- Mode: LUA; tab-width: 2 -*-

peripheral {
	 name = "Vectored Interrupt Controller (VIC)";
	 description = "Module implementing a 2 to 32-input prioritized interrupt controller with internal interrupt vector storage support.";
	 prefix = "VIC";
	 hdl_entity = "wb_slave_vic";

	 reg {
			name = "VIC Control Register";
			prefix = "CTL";

			field {
				 name = "VIC Enable";
				 description = "- 1: enables VIC operation\n- 0: disables VIC operation";
				 prefix = "ENABLE";
				 type = BIT;
				 access_dev = READ_ONLY;
				 access_bus = READ_WRITE;
			};

			field {
				 name = "VIC output polarity";
				 description = "- 1: IRQ output is active high\n- 0: IRQ output is active low";
				 prefix = "POL";
				 type = BIT;
				 access_dev = READ_ONLY;
				 access_bus = READ_WRITE;
			};

      field {
				 name = "Emulate Edge sensitive output";
				 description = "- 1: Forces a low pulse of <code>EMU_LEN</code> clock cycles at each write to <code>EOIR</code>. Useful for edge-only IRQ controllers such as Gennum.\n- 0: Normal IRQ master line behavior";
				 prefix = "EMU_EDGE";
				 type = BIT;
				 access_dev = READ_ONLY;
				 access_bus = READ_WRITE;
			};

      field {
         name = "Emulated Edge pulse timer";
		 description = "Length of the delay (in <code>clk_sys_i</code> cycles) between write to <code>EOIR</code> and re-assertion of <code>irq_master_o</code>.";
         prefix = "EMU_LEN";
         type = SLV;
         size = 16;
				 access_dev = READ_ONLY;
				 access_bus = READ_WRITE;
      };
	 };

	 reg {
			name = "Raw Interrupt Status Register";
			prefix = "RISR";
			
			field {
				 name = "Raw interrupt status";
				 description = "Each bit reflects the current state of corresponding IRQ input line.\n- read 1: interrupt line is currently active\n- read 0: interrupt line is inactive";
				 type = SLV;
				 size = 32;
				 access_dev = WRITE_ONLY;
				 access_bus = READ_ONLY;
			};
	 };

	 reg {
			name = "Interrupt Enable Register";
			prefix = "IER";
			
			field {
				 name = "Enable IRQ";
				 description = "- write 1: enables interrupt associated with written bit\n- write 0: no effect";
				 type = PASS_THROUGH;
				 size = 32;
			};
	 };

	 reg {
			name = "Interrupt Disable Register";
			prefix = "IDR";
			
			field {
				 name = "Disable IRQ";
				 description = "- write 1: enables interrupt associated with written bit\n- write 0: no effect";
				 type = PASS_THROUGH;
				 size = 32;
			};
	 };

	 reg {
			name = "Interrupt Mask Register";
			prefix = "IMR";
			
			field {
				 name = "IRQ disabled/enabled";
				 description = "- read 1: interrupt associated with read bit is enabled\n- read 0: interrupt is disabled";
				 type = SLV;
				 size = 32;
				 access_bus = READ_ONLY;
				 access_dev = WRITE_ONLY;
			};
	 };

	 reg {
			name = "Vector Address Register";
			prefix = "VAR";
			
			field {
				 name = "Vector Address";
				 description = "Address of pending interrupt vector, read from Interrupt Vector Table";
				 type = SLV;
				 size = 32;
				 access_bus = READ_ONLY;
				 access_dev = WRITE_ONLY;
			};
	 };

	 reg {
			name = "Software Interrupt Register";
			description = "Writing 1 to one of bits of this register causes a software emulation of the respective interrupt.";
			prefix = "SWIR";
			field {
				 name = "SWI interrupt mask";
				 type = PASS_THROUGH;
				 size = 32;
			};
	 };

	 reg {
			name = "End Of Interrupt Acknowledge Register";
			prefix = "EOIR";
			
			field {
				 name = "End of Interrupt";
				 description = "Any write operation acknowledges the pending interrupt. Then, VIC advances to another pending interrupt(s) or releases the master interrupt output.";
				 type = PASS_THROUGH;
				 size = 32;
			};
	 };

	 ram {
			name = "Interrupt Vector Table";
			description = "Vector Address Table. Word at offset N stores the vector address of IRQ N. When interrupt is requested, VIC reads it's vector address from this memory and stores it in VAR register. The contents of this table can be pre-initialized during synthesis through <code>g_init_vectors</code> generic parameter. This is used to auto-enumerate interrupts in SDB-based designs.";
			prefix = "IVT_RAM";
			
			size = 32;
			width = 32;
			
			access_bus = READ_WRITE;
			access_dev = READ_ONLY;
	 };
};
