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Dimitris Lampridis authored
The previous implementation was introducing latches to the GN4124 core under Xilinx ISE. Tested and verified to work with the following SPEC-based reference designs: - WR - MT - WRTD
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doc | ||
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platform | ||
sim | ||
syn/gsi_pexaria2a/wishbone_demo | ||
testbench | ||
tools | ||
top/gsi_pexaria2a/wishbone_demo | ||
.gitignore | ||
Manifest.py | ||
README.md |