Release 12.2 par M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

ABPC10853::  Fri Dec 10 09:45:57 2010

par -w -intstyle ise -ol high -mt off pfc_wrapper_map.ncd pfc_wrapper.ncd
pfc_wrapper.pcf 


Constraints file: pfc_wrapper.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment /opt/Xilinx/12.2/ISE_DS/ISE/.
   "pfc_wrapper" is an NCD, version 3.2, device xc6slx150t, package fgg676, speed -3
WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9225)] overrides
   constraint <NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9224)] on the design object 'L_WR_RDY_1_IBUF'.

WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9227)] overrides
   constraint <NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9226)] on the design object 'L_WR_RDY_0_IBUF'.

WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9231)] overrides
   constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9230)] on the design object 'VC_RDY<1>_IBUF'.

WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9233)] overrides
   constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [pfc_wrapper.pcf(9232)] on the design object 'VC_RDY<0>_IBUF'.


Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRELIMINARY 1.10 2010-06-28".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                 3,476 out of 184,304    1%
    Number used as Flip Flops:               3,444
    Number used as Latches:                     32
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      2,209 out of  92,152    2%
    Number used as logic:                    1,793 out of  92,152    1%
      Number using O6 output only:           1,131
      Number using O5 output only:              66
      Number using O5 and O6:                  596
      Number used as ROM:                        0
    Number used as Memory:                       1 out of  21,680    1%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:             1
        Number using O6 output only:             1
        Number using O5 output only:             0
        Number using O5 and O6:                  0
    Number used exclusively as route-thrus:    415
      Number with same-slice register load:    413
      Number with same-slice carry load:         2
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 1,111 out of  23,038    4%
  Number of LUT Flip Flop pairs used:        3,337
    Number with an unused Flip Flop:           529 out of   3,337   15%
    Number with an unused LUT:               1,128 out of   3,337   33%
    Number of fully used LUT-FF pairs:       1,680 out of   3,337   50%
    Number of slice register sites lost
      to control set restrictions:               0 out of 184,304    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        66 out of     396   16%
    Number of LOCed IOBs:                       66 out of      66  100%
    IOB Flip Flops:                              5

Specific Feature Utilization:
  Number of RAMB16BWERs:                        11 out of     268    4%
  Number of RAMB8BWERs:                          0 out of     536    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
    Number used as BUFIO2s:                      1
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             1 out of      32    3%
    Number used as BUFIO2FBs:                    1
    Number used as BUFIO2FB_2CLKs:               0
  Number of BUFG/BUFGMUXs:                       3 out of      16   18%
    Number used as BUFGs:                        3
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of      12    0%
  Number of ILOGIC2/ISERDES2s:                  25 out of     586    4%
    Number used as ILOGIC2s:                     5
    Number used as ISERDES2s:                   20
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         2 out of     586    1%
    Number used as IODELAY2s:                    2
    Number used as IODRP2s:                      0
    Number used as IODRP2_MCBs:                  0
  Number of OLOGIC2/OSERDES2s:                  20 out of     586    3%
    Number used as OLOGIC2s:                     0
    Number used as OSERDES2s:                   20
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     384    0%
  Number of BUFPLLs:                             1 out of       8   12%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of     180    0%
  Number of GTPA1_DUALs:                         0 out of       4    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       4    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            1 out of       6   16%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx
   Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis.  REAL time: 32 secs 
Finished initial Timing Analysis.  REAL time: 32 secs 

WARNING:Par:288 - The signal VC_RDY<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal VC_RDY<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal TX_ERROR_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<0>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GPIO<1>_IBUF has no load.  PAR will not attempt to route this signal.
Starting Router


Phase  1  : 15115 unrouted;      REAL time: 37 secs 

Phase  2  : 12467 unrouted;      REAL time: 46 secs 

Phase  3  : 3144 unrouted;      REAL time: 1 mins 25 secs 

Phase  4  : 3162 unrouted; (Setup:1730, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 46 secs 

Updating file: pfc_wrapper.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:1736, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 36 secs 

Phase  6  : 0 unrouted; (Setup:1736, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 38 secs 

Phase  7  : 0 unrouted; (Setup:948, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 11 secs 

Phase  8  : 0 unrouted; (Setup:948, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 11 secs 

Phase  9  : 0 unrouted; (Setup:948, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 11 secs 

Phase 10  : 0 unrouted; (Setup:579, Hold:0, Component Switching Limit:0)     REAL time: 4 mins 15 secs 
Total REAL time to Router completion: 4 mins 15 secs 
Total CPU time to Router completion: 4 mins 27 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ |              |      |      |            |             |
|                 clk | BUFGMUX_X3Y13| No   |  680 |  0.807     |  2.177      |
+---------------------+--------------+------+------+------------+-------------+
|          l_clk_BUFG | BUFGMUX_X3Y15| No   |  345 |  0.347     |  1.714      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/cmp_ |              |      |      |            |             |
|wbmaster32/_n0440_BU |              |      |      |            |             |
|                  FG |  BUFGMUX_X2Y3| No   |    8 |  0.005     |  1.638      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c |              |      |      |            |             |
|                  lk |         Local|      |   41 |  0.043     |  2.143      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 579 (Setup: 579, Hold: 0, Component Switching Limit: 0)

WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in your design.

   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.

   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
   are set in the tools for timing closure.

   Use the Xilinx "SmartXplorer" script to try special combinations of
   options known to produce very good results.

   Visit the Xilinx technical support web at http://support.xilinx.com and go to
   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
   in your design.

Number of Timing Constraints that were not applied: 11

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
* TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP       |    -0.579ns|     5.579ns|       1|         579
  1_0 = PERIOD TIMEGRP         "cmp_gn4124_ | HOLD        |     0.274ns|            |       0|           0
  core_cmp_clk_in_rx_pllout_x1_0"         T |             |            |            |        |            
  S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0  |             |            |            |        |            
  PHASE 1.25 ns HIGH 50%                    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_l_clkp = PERIOD TIMEGRP "l_clkp_grp" 5 | SETUP       |     0.205ns|     4.795ns|       0|           0
   ns HIGH 50%                              | HOLD        |     0.382ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD   |     1.430ns|     3.570ns|       0|           0
  1 = PERIOD TIMEGRP         "cmp_gn4124_co |             |            |            |        |            
  re_cmp_clk_in_rx_pllout_x1"         TS_cm |             |            |            |        |            
  p_gn4124_core_cmp_clk_in_buf_P_clk PHASE  |             |            |            |        |            
  1.25 ns HIGH 50%                          |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
   = PERIOD TIMEGRP         "cmp_gn4124_cor |             |            |            |        |            
  e_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIG |             |            |            |        |            
  H 50%                                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = | MINLOWPULSE |     2.200ns|     2.800ns|       0|           0
   PERIOD TIMEGRP         "cmp_gn4124_core_ |             |            |            |        |            
  cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50 |             |            |            |        |            
  %                                         |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  NET "P_RD_D_RDY_0_IBUF" MAXDELAY = 2 ns   | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
----------------------------------------------------------------------------------------------------------
  NET "P_RD_D_RDY_1_IBUF" MAXDELAY = 2 ns   | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
----------------------------------------------------------------------------------------------------------
  NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns     | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
----------------------------------------------------------------------------------------------------------
  NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns     | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
----------------------------------------------------------------------------------------------------------
  NET "L2P_RDY_IBUF" MAXDELAY = 2 ns        | MAXDELAY    |     1.676ns|     0.324ns|       0|           0
----------------------------------------------------------------------------------------------------------
  NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns      | MAXDELAY    |     2.000ns|     0.000ns|       0|           0
----------------------------------------------------------------------------------------------------------
  NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns      | MAXDELAY    |     2.000ns|     0.000ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD   |     3.096ns|     1.904ns|       0|           0
  p" 5 ns HIGH 50%                          |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | MINPERIOD   |     3.096ns|     1.904ns|       0|           0
  p" 5 ns HIGH 50%                          |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns      | N/A         |         N/A|         N/A|     N/A|         N/A
----------------------------------------------------------------------------------------------------------
  NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns      | N/A         |         N/A|         N/A|     N/A|         N/A
----------------------------------------------------------------------------------------------------------
  NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns     | N/A         |         N/A|         N/A|     N/A|         N/A
----------------------------------------------------------------------------------------------------------
  TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A         |         N/A|         N/A|     N/A|         N/A
  s_int = PERIOD TIMEGRP         "cmp_gn412 |             |            |            |        |            
  4_core_cmp_clk_in_rx_pllout_xs_int"       |             |            |            |        |            
     TS_cmp_gn4124_core_cmp_clk_in_buf_P_cl |             |            |            |        |            
  k / 2 HIGH 50%                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns     | N/A         |         N/A|         N/A|     N/A|         N/A
----------------------------------------------------------------------------------------------------------
  TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A         |         N/A|         N/A|     N/A|         N/A
  s_int_0 = PERIOD TIMEGRP         "cmp_gn4 |             |            |            |        |            
  124_core_cmp_clk_in_rx_pllout_xs_int_0"   |             |            |            |        |            
         TS_cmp_gn4124_core_cmp_clk_in_buf_ |             |            |            |        |            
  P_clk_0 / 2 HIGH 50%                      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_p2l_clkp
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkp                    |      5.000ns|      1.904ns|      3.570ns|            0|            0|            0|            0|
| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      3.570ns|            0|            0|            0|            0|
| buf_P_clk                     |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
|  _rx_pllout_xs_int            |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      3.570ns|          N/A|            0|            0|            0|            0|
|  _rx_pllout_x1                |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_p2l_clkn
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn                    |      5.000ns|      1.904ns|      5.579ns|            0|            1|            0|        29021|
| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      5.579ns|            0|            1|            0|        29021|
| buf_P_clk_0                   |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
|  _rx_pllout_xs_int_0          |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      5.579ns|          N/A|            1|            0|        29021|            0|
|  _rx_pllout_x1_0              |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 4 mins 21 secs 
Total CPU time to PAR completion: 4 mins 33 secs 

Peak Memory Usage:  412 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 1 errors found.

Number of error messages: 0
Number of warning messages: 13
Number of info messages: 1

Writing design to file pfc_wrapper.ncd



PAR done!
