Release 12.2 - xst M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> 
Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> 
Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> 
Reading design: pfc_wrapper.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "pfc_wrapper.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "pfc_wrapper"
Output Format                      : NGC
Target Device                      : xc6slx150t-3-fgg676

---- Source Options
Top Module Name                    : pfc_wrapper
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"../ip_cores"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../ip_cores/fifo_32x512.vhd" into library work
Parsing entity <fifo_32x512>.
Parsing architecture <fifo_32x512_a> of entity <fifo_32x512>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_n_to_1_s2_se.vhd" into library work
Parsing entity <serdes_n_to_1_s2_se>.
Parsing architecture <arch_serdes_n_to_1_s2_se> of entity <serdes_n_to_1_s2_se>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_n_to_1_s2_diff.vhd" into library work
Parsing entity <serdes_n_to_1_s2_diff>.
Parsing architecture <arch_serdes_n_to_1_s2_diff> of entity <serdes_n_to_1_s2_diff>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" into library work
Parsing entity <serdes_1_to_n_data_s2_se>.
Parsing architecture <arch_serdes_1_to_n_data_s2_se> of entity <serdes_1_to_n_data_s2_se>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/gn4124_core_pkg_s6.vhd" into library work
Parsing package <gn4124_core_pkg>.
Parsing package body <gn4124_core_pkg>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" into library work
Parsing entity <dma_controller_wb_slave>.
Parsing architecture <syn> of entity <dma_controller_wb_slave>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/wbmaster32.vhd" into library work
Parsing entity <wbmaster32>.
Parsing architecture <behaviour> of entity <wbmaster32>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd" into library work
Parsing entity <serdes_1_to_n_clk_pll_s2_diff>.
Parsing architecture <arch_serdes_1_to_n_clk_pll_s2_diff> of entity <serdes_1_to_n_clk_pll_s2_diff>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/p2l_dma_master.vhd" into library work
Parsing entity <p2l_dma_master>.
Parsing architecture <behaviour> of entity <p2l_dma_master>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/p2l_des_s6.vhd" into library work
Parsing entity <p2l_des>.
Parsing architecture <rtl> of entity <p2l_des>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/p2l_decode32.vhd" into library work
Parsing entity <p2l_decode32>.
Parsing architecture <rtl> of entity <p2l_decode32>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/l2p_ser_s6.vhd" into library work
Parsing entity <l2p_ser>.
Parsing architecture <rtl> of entity <l2p_ser>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/l2p_dma_master.vhd" into library work
Parsing entity <l2p_dma_master>.
Parsing architecture <behaviour> of entity <l2p_dma_master>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/l2p_arbiter.vhd" into library work
Parsing entity <l2p_arbiter>.
Parsing architecture <rtl> of entity <l2p_arbiter>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller.vhd" into library work
Parsing entity <dma_controller>.
Parsing architecture <behaviour> of entity <dma_controller>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../ip_cores/ram_2048x32.vhd" into library work
Parsing entity <ram_2048x32>.
Parsing architecture <ram_2048x32_a> of entity <ram_2048x32>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/gn4124_core_s6.vhd" into library work
Parsing entity <gn4124_core>.
Parsing architecture <rtl> of entity <gn4124_core>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" into library work
Parsing entity <dummy_stat_regs_wb_slave>.
Parsing architecture <syn> of entity <dummy_stat_regs_wb_slave>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" into library work
Parsing entity <dummy_ctrl_regs_wb_slave>.
Parsing architecture <syn> of entity <dummy_ctrl_regs_wb_slave>.
Parsing VHDL file "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../rtl/pfc_wrapper.vhd" into library work
Parsing entity <pfc_wrapper>.
Parsing architecture <rtl> of entity <pfc_wrapper>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <pfc_wrapper> (architecture <rtl>) with generics from library <work>.

Elaborating entity <gn4124_core> (architecture <rtl>) with generics from library <work>.

Elaborating entity <serdes_1_to_n_clk_pll_s2_diff> (architecture <arch_serdes_1_to_n_clk_pll_s2_diff>) with generics from library <work>.

Elaborating entity <p2l_des> (architecture <rtl>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/p2l_des_s6.vhd" Line 143: Assignment to p2l_data_bitslip_p ignored, since the identifier is never used

Elaborating entity <serdes_1_to_n_data_s2_se> (architecture <arch_serdes_1_to_n_data_s2_se>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" Line 97: Net <busys[15]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" Line 111: Net <valid_data[15]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" Line 119: Net <incdec_data[15]> does not have a driver.

Elaborating entity <serdes_1_to_n_data_s2_se> (architecture <arch_serdes_1_to_n_data_s2_se>) with generics from library <work>.

Elaborating entity <p2l_decode32> (architecture <rtl>) from library <work>.

Elaborating entity <wbmaster32> (architecture <behaviour>) with generics from library <work>.
INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.
WARNING:HDLCompiler:89 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/gn4124_core_pkg_s6.vhd" Line 461: <fifo_64x512> remains a black-box since it has no binding entity.

Elaborating entity <fifo_32x512> (architecture <fifo_32x512_a>) from library <work>.
INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.

Elaborating entity <dma_controller> (architecture <behaviour>) from library <work>.

Elaborating entity <dma_controller_wb_slave> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 167: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 168: Assignment to bus_clock_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 169: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 170: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 171: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dma_controller_wb_slave.vhd" Line 172: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.

Elaborating entity <l2p_dma_master> (architecture <behaviour>) with generics from library <work>.
INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.

Elaborating entity <p2l_dma_master> (architecture <behaviour>) with generics from library <work>.
INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.

Elaborating entity <l2p_arbiter> (architecture <rtl>) from library <work>.

Elaborating entity <l2p_ser> (architecture <rtl>) from library <work>.

Elaborating entity <serdes_n_to_1_s2_diff> (architecture <arch_serdes_n_to_1_s2_diff>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_n_to_1_s2_diff.vhd" Line 93: Net <mdatainb[3]> does not have a driver.

Elaborating entity <serdes_n_to_1_s2_se> (architecture <arch_serdes_n_to_1_s2_se>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/serdes_n_to_1_s2_se.vhd" Line 92: Net <mdatainb[63]> does not have a driver.

Elaborating entity <serdes_n_to_1_s2_se> (architecture <arch_serdes_n_to_1_s2_se>) with generics from library <work>.

Elaborating entity <dummy_stat_regs_wb_slave> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 56: Assignment to wrdata_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 57: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 59: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 60: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 61: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_stat_regs.vhd" Line 62: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.

Elaborating entity <dummy_ctrl_regs_wb_slave> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 61: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 63: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 64: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 65: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/mcattin/projects/GN4124_core/hdl/pfc/ise_project/../../gn4124core/rtl/dummy_ctrl_regs.vhd" Line 66: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - Case statement is complete. Others clause is never selected and therefore discarded.

Elaborating entity <ram_2048x32> (architecture <ram_2048x32_a>) from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pfc_wrapper>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd".
        TAR_ADDR_WDTH = 13
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 334: Output port <debug_o> of the instance <cmp_gn4124_core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 334: Output port <dma_sel_o> of the instance <cmp_gn4124_core> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 447: Output port <dummy_reg_1_o> of the instance <cmp_dummy_ctrl_regs> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 447: Output port <dummy_reg_2_o> of the instance <cmp_dummy_ctrl_regs> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/pfc/rtl/pfc_wrapper.vhd" line 447: Output port <dummy_reg_3_o> of the instance <cmp_dummy_ctrl_regs> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <USER_IO_0_P>.
    Found 1-bit register for signal <dma_ack_i>.
    Found 4-bit register for signal <clk_div_cnt>.
    Found 4-bit adder for signal <clk_div_cnt[3]_GND_6_o_add_5_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   6 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <pfc_wrapper> synthesized.

Synthesizing Unit <gn4124_core>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd".
        g_IS_SPARTAN6 = true
        g_BAR0_APERTURE = 20
        g_CSR_WB_SLAVES_NB = 2
        g_DMA_WB_SLAVES_NB = 1
        g_DMA_WB_ADDR_WIDTH = 26
WARNING:Xst:647 - Input <p_wr_req_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <vc_rdy_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tx_error_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 338: Output port <datain> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 338: Output port <rx_pll_lckd> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 338: Output port <rx_pllout_xs> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 338: Output port <bitslip> of the instance <cmp_clk_in> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 423: Output port <p2l_hdr_stat_o> of the instance <cmp_p2l_decode32> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" line 423: Output port <p2l_hdr_last_o> of the instance <cmp_p2l_decode32> is unconnected or connected to loadless signal.
    Found 2-bit register for signal <l_wr_rdy_t>.
    Found 2-bit register for signal <l_wr_rdy_t2>.
    Found 2-bit register for signal <l_wr_rdy>.
    Found 2-bit register for signal <p_rd_d_rdy_t>.
    Found 2-bit register for signal <p_rd_d_rdy_t2>.
    Found 2-bit register for signal <p_rd_d_rdy>.
    Found 1-bit register for signal <rst_reg>.
    Found 1-bit register for signal <l2p_rdy_t>.
    Found 1-bit register for signal <l2p_rdy_t2>.
    Found 1-bit register for signal <l2p_rdy>.
    Found 1-bit register for signal <l2p_edb_o>.
    Found 1-bit register for signal <l2p_edb_t>.
    Found 1-bit register for signal <l2p_edb_t2>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <gn4124_core> synthesized.

Synthesizing Unit <serdes_1_to_n_clk_pll_s2_diff>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd".
        PLLD = 1
        PLLX = 2
        CLKIN_PERIOD = 5.0
        S = 2
        BS = false
        DIFF_TERM = false
WARNING:Xst:647 - Input <pattern1<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pattern2<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <enable>.
    Found 1-bit register for signal <cal_clk>.
    Found 1-bit register for signal <rst_clk>.
    Found 1-bit register for signal <bslip>.
    Found 12-bit register for signal <counter>.
    Found 3-bit register for signal <count>.
    Found 4-bit register for signal <state>.
    Found 1-bit register for signal <busyd>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 24                                             |
    | Inputs             | 4                                              |
    | Outputs            | 9                                              |
    | Clock              | rx_bufg_pll_x1_int (rising_edge)               |
    | Reset              | not_rx_bufpll_lckd (positive)                  |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 12-bit adder for signal <counter[11]_GND_10_o_add_1_OUT> created at line 176.
    Found 3-bit adder for signal <count[2]_GND_10_o_add_14_OUT> created at line 205.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  19 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <serdes_1_to_n_clk_pll_s2_diff> synthesized.

Synthesizing Unit <p2l_des>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd".
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd" line 148: Output port <debug> of the instance <cmp_data_in> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd" line 168: Output port <debug> of the instance <cmp_dframe_in> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd" line 191: Output port <debug> of the instance <cmp_valid_in> is unconnected or connected to loadless signal.
    Found 32-bit register for signal <p2l_data_o>.
    Found 32-bit register for signal <p2l_data_t2>.
    Found 1-bit register for signal <p2l_dframe_o>.
    Found 1-bit register for signal <p2l_valid_o>.
    Found 1-bit register for signal <p2l_dframe_t2>.
    Found 1-bit register for signal <p2l_valid_t2>.
    Summary:
	inferred  68 D-type flip-flop(s).
Unit <p2l_des> synthesized.

Synthesizing Unit <serdes_1_to_n_data_s2_se_1>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd".
        USE_PD = false
        S = 2
        D = 16
WARNING:Xst:653 - Signal <busys> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <valid_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <incdec_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 9-bit register for signal <counter>.
    Found 4-bit register for signal <state>.
    Found 16-bit register for signal <mux>.
    Found 1-bit register for signal <cal_data_master>.
    Found 1-bit register for signal <cal_data_sint>.
    Found 1-bit register for signal <enable>.
    Found 1-bit register for signal <rst_data>.
    Found 1-bit register for signal <busy_data_d>.
    Found 16-bit register for signal <ce_data>.
    Found 1-bit register for signal <inc_data_int>.
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 17                                             |
    | Inputs             | 3                                              |
    | Outputs            | 7                                              |
    | Clock              | gclk (rising_edge)                             |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit adder for signal <counter[8]_GND_55_o_add_2_OUT> created at line 150.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  47 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <serdes_1_to_n_data_s2_se_1> synthesized.

Synthesizing Unit <serdes_1_to_n_data_s2_se_2>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd".
        USE_PD = false
        S = 2
        D = 1
WARNING:Xst:653 - Signal <busys> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <valid_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <incdec_data> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 9-bit register for signal <counter>.
    Found 5-bit register for signal <pdcounter>.
    Found 4-bit register for signal <state>.
    Found 1-bit register for signal <cal_data_master>.
    Found 1-bit register for signal <cal_data_sint>.
    Found 1-bit register for signal <enable>.
    Found 1-bit register for signal <ce_data_inta>.
    Found 1-bit register for signal <flag>.
    Found 1-bit register for signal <rst_data>.
    Found 1-bit register for signal <busy_data_d>.
    Found 1-bit register for signal <incdec_data_d>.
    Found 1-bit register for signal <valid_data_d>.
    Found 1-bit register for signal <ce_data>.
    Found 1-bit register for signal <inc_data_int>.
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 17                                             |
    | Inputs             | 3                                              |
    | Outputs            | 9                                              |
    | Clock              | gclk (rising_edge)                             |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit adder for signal <counter[8]_GND_125_o_add_1_OUT> created at line 150.
    Found 5-bit adder for signal <pdcounter[4]_GND_125_o_add_34_OUT> created at line 242.
    Found 5-bit subtractor for signal <GND_125_o_GND_125_o_sub_37_OUT<4:0>>.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  24 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <serdes_1_to_n_data_s2_se_2> synthesized.

Synthesizing Unit <p2l_decode32>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_decode32.vhd".
    Found 10-bit register for signal <p2l_hdr_length>.
    Found 2-bit register for signal <p2l_hdr_cid>.
    Found 2-bit register for signal <p2l_hdr_stat>.
    Found 4-bit register for signal <p2l_hdr_fbe>.
    Found 4-bit register for signal <p2l_hdr_lbe>.
    Found 4-bit register for signal <p2l_be>.
    Found 32-bit register for signal <p2l_addr>.
    Found 32-bit register for signal <p2l_d>.
    Found 1-bit register for signal <des_p2l_valid_d>.
    Found 1-bit register for signal <target_mrd>.
    Found 1-bit register for signal <target_mwr>.
    Found 1-bit register for signal <master_cpld>.
    Found 1-bit register for signal <master_cpln>.
    Found 1-bit register for signal <p2l_hdr_strobe>.
    Found 1-bit register for signal <p2l_hdr_last>.
    Found 1-bit register for signal <p2l_addr_cycle>.
    Found 1-bit register for signal <p2l_addr_start>.
    Found 1-bit register for signal <p2l_data_cycle>.
    Found 1-bit register for signal <p2l_d_valid>.
    Found 1-bit register for signal <p2l_d_last>.
    Found 1-bit register for signal <des_p2l_dframe_d>.
    Found 30-bit adder for signal <p2l_addr[31]_GND_140_o_add_17_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 103 D-type flip-flop(s).
	inferred  38 Multiplexer(s).
Unit <p2l_decode32> synthesized.

Synthesizing Unit <wbmaster32>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd".
        g_BAR0_APERTURE = 20
        g_WB_SLAVES_NB = 3
WARNING:Xst:647 - Input <pd_wbm_hdr_length_i<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_wbm_addr_i<0:30>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_wbm_be_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_wbm_data_last_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 302: Output port <full> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 302: Output port <valid> of the instance <cmp_fifo_to_wb> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Output port <full> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Output port <valid> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd" line 323: Output port <prog_full> of the instance <cmp_from_wb_fifo> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <to_wb_fifo_wr>.
    Found 1-bit register for signal <wbm_arb_req_o>.
    Found 1-bit register for signal <wbm_arb_valid_o>.
    Found 1-bit register for signal <wbm_arb_dframe_o>.
    Found 1-bit register for signal <from_wb_fifo_rd>.
    Found 1-bit register for signal <to_wb_fifo_rd>.
    Found 1-bit register for signal <wb_cyc_t>.
    Found 1-bit register for signal <wb_stb_t>.
    Found 1-bit register for signal <wb_we_t>.
    Found 1-bit register for signal <from_wb_fifo_wr>.
    Found 1-bit register for signal <wb_ack_t>.
    Found 2-bit register for signal <p2l_cid>.
    Found 2-bit register for signal <l2p_read_cpl_current_state>.
    Found 2-bit register for signal <wishbone_current_state>.
    Found 2-bit register for signal <wb_periph_addr>.
    Found 32-bit register for signal <wbm_arb_data_o>.
    Found 32-bit register for signal <wb_dat_o_t>.
    Found 32-bit register for signal <from_wb_fifo_din>.
    Found 32-bit register for signal <wb_dat_i_t>.
    Found 4-bit register for signal <wb_sel_t>.
    Found 31-bit register for signal <wb_adr_t>.
    Found 64-bit register for signal <to_wb_fifo_din>.
    Found finite state machine <FSM_3> for signal <l2p_read_cpl_current_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 5                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | l2p_idle                                       |
    | Power Up State     | l2p_idle                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_4> for signal <wishbone_current_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 10                                             |
    | Clock              | wb_clk_i (rising_edge)                         |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | wb_idle                                        |
    | Power Up State     | wb_idle                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit adder for signal <s_wb_periph_addr[1]_GND_141_o_add_39_OUT> created at line 439.
    Found 8-bit adder for signal <n0264> created at line 477.
    Found 32-bit 3-to-1 multiplexer for signal <l2p_read_cpl_current_state[1]_X_16_o_wide_mux_11_OUT> created at line 256.
    Found 1-bit 3-to-1 multiplexer for signal <wb_periph_addr[1]_X_16_o_Mux_46_o> created at line 466.
    Found 1-bit 3-to-1 multiplexer for signal <_n0304> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0323> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0343> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0362> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0381> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0400> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0419> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0438> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0457> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0476> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0495> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0514> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0533> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0552> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0571> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0590> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0609> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0628> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0647> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0666> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0685> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0704> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0723> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0742> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0761> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0780> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0799> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0818> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0837> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0856> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0875> created at line 477.
    Found 1-bit 3-to-1 multiplexer for signal <_n0894> created at line 477.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<30>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<29>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<28>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<27>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<26>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<25>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<24>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<23>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<22>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<21>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<20>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<19>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<18>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<17>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<16>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<15>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<14>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<13>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<12>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<11>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<10>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<9>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<8>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <s_wb_dat_i_muxed<31>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 2-bit comparator greater for signal <wb_periph_addr[1]_PWR_57_o_LessThan_48_o> created at line 465
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 242 D-type flip-flop(s).
	inferred  32 Latch(s).
	inferred   1 Comparator(s).
	inferred  72 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <wbmaster32> synthesized.

Synthesizing Unit <dma_controller>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd".
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd" line 204: Output port <dma_stat_o> of the instance <dma_controller_wb_slave_0> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd" line 204: Output port <dma_stat_load_o> of the instance <dma_controller_wb_slave_0> is unconnected or connected to loadless signal.
    Found 32-bit register for signal <dma_cstart_reg>.
    Found 32-bit register for signal <dma_hstartl_reg>.
    Found 32-bit register for signal <dma_hstarth_reg>.
    Found 32-bit register for signal <dma_len_reg>.
    Found 32-bit register for signal <dma_nextl_reg>.
    Found 32-bit register for signal <dma_nexth_reg>.
    Found 32-bit register for signal <dma_attrib_reg>.
    Found 32-bit register for signal <dma_ctrl_carrier_addr_o>.
    Found 32-bit register for signal <dma_ctrl_host_addr_h_o>.
    Found 32-bit register for signal <dma_ctrl_host_addr_l_o>.
    Found 32-bit register for signal <dma_ctrl_len_o>.
    Found 32-bit register for signal <dma_ctrl_reg>.
    Found 3-bit register for signal <dma_ctrl_current_state>.
    Found 3-bit register for signal <dma_status>.
    Found 3-bit register for signal <dma_stat_reg>.
    Found 1-bit register for signal <dma_ctrl_start_l2p_o>.
    Found 1-bit register for signal <dma_ctrl_start_p2l_o>.
    Found 1-bit register for signal <dma_ctrl_start_next_o>.
    Found 1-bit register for signal <dma_error_irq>.
    Found 1-bit register for signal <dma_done_irq>.
    Found 1-bit register for signal <dma_ctrl_abort_o>.
    Found finite state machine <FSM_5> for signal <dma_ctrl_current_state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 18                                             |
    | Inputs             | 7                                              |
    | Outputs            | 12                                             |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | dma_idle                                       |
    | Power Up State     | dma_idle                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    WARNING:Xst:2404 -  FFs/Latches <dma_stat_reg<31:3>> (without init value) have a constant value of 0 in block <dma_controller>.
    Summary:
	inferred 396 D-type flip-flop(s).
	inferred  13 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <dma_controller> synthesized.

Synthesizing Unit <dma_controller_wb_slave>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 32-bit register for signal <dma_ctrl_int_write>.
    Found 32-bit register for signal <dma_stat_int_write>.
    Found 32-bit register for signal <dma_cstart_int_write>.
    Found 32-bit register for signal <dma_hstartl_int_write>.
    Found 32-bit register for signal <dma_hstarth_int_write>.
    Found 32-bit register for signal <dma_len_int_write>.
    Found 32-bit register for signal <dma_nextl_int_write>.
    Found 32-bit register for signal <dma_nexth_int_write>.
    Found 32-bit register for signal <dma_attrib_int_write>.
    Found 32-bit register for signal <dma_ctrl_o>.
    Found 32-bit register for signal <dma_ctrl_int_read>.
    Found 32-bit register for signal <dma_stat_o>.
    Found 32-bit register for signal <dma_stat_int_read>.
    Found 32-bit register for signal <dma_cstart_o>.
    Found 32-bit register for signal <dma_cstart_int_read>.
    Found 32-bit register for signal <dma_hstartl_o>.
    Found 32-bit register for signal <dma_hstartl_int_read>.
    Found 32-bit register for signal <dma_hstarth_o>.
    Found 32-bit register for signal <dma_hstarth_int_read>.
    Found 32-bit register for signal <dma_len_o>.
    Found 32-bit register for signal <dma_len_int_read>.
    Found 32-bit register for signal <dma_nextl_o>.
    Found 32-bit register for signal <dma_nextl_int_read>.
    Found 32-bit register for signal <dma_nexth_o>.
    Found 32-bit register for signal <dma_nexth_int_read>.
    Found 32-bit register for signal <dma_attrib_o>.
    Found 32-bit register for signal <dma_attrib_int_read>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <dma_ctrl_lw>.
    Found 1-bit register for signal <dma_ctrl_lw_delay>.
    Found 1-bit register for signal <dma_ctrl_lw_read_in_progress>.
    Found 1-bit register for signal <dma_ctrl_rwsel>.
    Found 1-bit register for signal <dma_stat_lw>.
    Found 1-bit register for signal <dma_stat_lw_delay>.
    Found 1-bit register for signal <dma_stat_lw_read_in_progress>.
    Found 1-bit register for signal <dma_stat_rwsel>.
    Found 1-bit register for signal <dma_cstart_lw>.
    Found 1-bit register for signal <dma_cstart_lw_delay>.
    Found 1-bit register for signal <dma_cstart_lw_read_in_progress>.
    Found 1-bit register for signal <dma_cstart_rwsel>.
    Found 1-bit register for signal <dma_hstartl_lw>.
    Found 1-bit register for signal <dma_hstartl_lw_delay>.
    Found 1-bit register for signal <dma_hstartl_lw_read_in_progress>.
    Found 1-bit register for signal <dma_hstartl_rwsel>.
    Found 1-bit register for signal <dma_hstarth_lw>.
    Found 1-bit register for signal <dma_hstarth_lw_delay>.
    Found 1-bit register for signal <dma_hstarth_lw_read_in_progress>.
    Found 1-bit register for signal <dma_hstarth_rwsel>.
    Found 1-bit register for signal <dma_len_lw>.
    Found 1-bit register for signal <dma_len_lw_delay>.
    Found 1-bit register for signal <dma_len_lw_read_in_progress>.
    Found 1-bit register for signal <dma_len_rwsel>.
    Found 1-bit register for signal <dma_nextl_lw>.
    Found 1-bit register for signal <dma_nextl_lw_delay>.
    Found 1-bit register for signal <dma_nextl_lw_read_in_progress>.
    Found 1-bit register for signal <dma_nextl_rwsel>.
    Found 1-bit register for signal <dma_nexth_lw>.
    Found 1-bit register for signal <dma_nexth_lw_delay>.
    Found 1-bit register for signal <dma_nexth_lw_read_in_progress>.
    Found 1-bit register for signal <dma_nexth_rwsel>.
    Found 1-bit register for signal <dma_attrib_lw>.
    Found 1-bit register for signal <dma_attrib_lw_delay>.
    Found 1-bit register for signal <dma_attrib_lw_read_in_progress>.
    Found 1-bit register for signal <dma_attrib_rwsel>.
    Found 1-bit register for signal <dma_ctrl_lw_s0>.
    Found 1-bit register for signal <dma_ctrl_lw_s1>.
    Found 1-bit register for signal <dma_ctrl_lw_s2>.
    Found 1-bit register for signal <dma_ctrl_load_o>.
    Found 1-bit register for signal <dma_stat_lw_s0>.
    Found 1-bit register for signal <dma_stat_lw_s1>.
    Found 1-bit register for signal <dma_stat_lw_s2>.
    Found 1-bit register for signal <dma_stat_load_o>.
    Found 1-bit register for signal <dma_cstart_lw_s0>.
    Found 1-bit register for signal <dma_cstart_lw_s1>.
    Found 1-bit register for signal <dma_cstart_lw_s2>.
    Found 1-bit register for signal <dma_cstart_load_o>.
    Found 1-bit register for signal <dma_hstartl_lw_s0>.
    Found 1-bit register for signal <dma_hstartl_lw_s1>.
    Found 1-bit register for signal <dma_hstartl_lw_s2>.
    Found 1-bit register for signal <dma_hstartl_load_o>.
    Found 1-bit register for signal <dma_hstarth_lw_s0>.
    Found 1-bit register for signal <dma_hstarth_lw_s1>.
    Found 1-bit register for signal <dma_hstarth_lw_s2>.
    Found 1-bit register for signal <dma_hstarth_load_o>.
    Found 1-bit register for signal <dma_len_lw_s0>.
    Found 1-bit register for signal <dma_len_lw_s1>.
    Found 1-bit register for signal <dma_len_lw_s2>.
    Found 1-bit register for signal <dma_len_load_o>.
    Found 1-bit register for signal <dma_nextl_lw_s0>.
    Found 1-bit register for signal <dma_nextl_lw_s1>.
    Found 1-bit register for signal <dma_nextl_lw_s2>.
    Found 1-bit register for signal <dma_nextl_load_o>.
    Found 1-bit register for signal <dma_nexth_lw_s0>.
    Found 1-bit register for signal <dma_nexth_lw_s1>.
    Found 1-bit register for signal <dma_nexth_lw_s2>.
    Found 1-bit register for signal <dma_nexth_load_o>.
    Found 1-bit register for signal <dma_attrib_lw_s0>.
    Found 1-bit register for signal <dma_attrib_lw_s1>.
    Found 1-bit register for signal <dma_attrib_lw_s2>.
    Found 1-bit register for signal <dma_attrib_load_o>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <dma_controller_wb_slave>.
    Summary:
	inferred 978 D-type flip-flop(s).
	inferred  41 Multiplexer(s).
Unit <dma_controller_wb_slave> synthesized.

Synthesizing Unit <l2p_dma_master>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd".
        g_BYTE_SWAP = false
WARNING:Xst:647 - Input <dma_ctrl_target_addr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_ctrl_len_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_ctrl_byte_swap_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 481: Output port <full> of the instance <cmp_addr_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 497: Output port <full> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd" line 497: Output port <valid> of the instance <cmp_data_fifo> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <dma_ctrl_error_o>.
    Found 1-bit register for signal <addr_fifo_wr>.
    Found 1-bit register for signal <l2p_64b_address>.
    Found 1-bit register for signal <l2p_last_packet>.
    Found 1-bit register for signal <ldm_arb_req_o>.
    Found 1-bit register for signal <ldm_arb_valid_o>.
    Found 1-bit register for signal <ldm_arb_dframe_o>.
    Found 1-bit register for signal <data_fifo_rd>.
    Found 1-bit register for signal <dma_ctrl_done_o>.
    Found 1-bit register for signal <l2p_edb_o>.
    Found 1-bit register for signal <l2p_dma_stb_t>.
    Found 1-bit register for signal <l2p_dma_cyc_t>.
    Found 30-bit register for signal <dma_length_cnt>.
    Found 30-bit register for signal <l2p_len_cnt>.
    Found 30-bit register for signal <target_addr_cnt>.
    Found 11-bit register for signal <l2p_data_cnt>.
    Found 32-bit register for signal <l2p_address_h>.
    Found 32-bit register for signal <l2p_address_l>.
    Found 32-bit register for signal <ldm_arb_data_o>.
    Found 32-bit register for signal <l2p_dma_adr_o>.
    Found 10-bit register for signal <l2p_len_header>.
    Found 3-bit register for signal <l2p_dma_current_state>.
    Found 4-bit register for signal <l2p_dma_sel_o>.
    Found 7-bit register for signal <wb_read_cnt>.
    Found 7-bit register for signal <wb_ack_cnt>.
    Found 32-bit register for signal <addr_fifo_din>.
    Found finite state machine <FSM_6> for signal <l2p_dma_current_state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 23                                             |
    | Inputs             | 9                                              |
    | Outputs            | 11                                             |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | l2p_idle                                       |
    | Power Up State     | l2p_idle                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 30-bit adder for signal <target_addr_cnt[29]_GND_190_o_add_4_OUT> created at line 1241.
    Found 32-bit adder for signal <l2p_address_l[31]_GND_190_o_add_35_OUT> created at line 269.
    Found 7-bit adder for signal <wb_read_cnt[6]_GND_190_o_add_111_OUT> created at line 1241.
    Found 7-bit adder for signal <wb_ack_cnt[6]_GND_190_o_add_114_OUT> created at line 1241.
    Found 30-bit subtractor for signal <GND_190_o_GND_190_o_sub_6_OUT<29:0>>.
    Found 30-bit subtractor for signal <GND_190_o_GND_190_o_sub_31_OUT<29:0>>.
    Found 11-bit subtractor for signal <GND_190_o_GND_190_o_sub_34_OUT<10:0>>.
    Found 7-bit subtractor for signal <GND_190_o_GND_190_o_sub_108_OUT<6:0>>.
    Found 30-bit comparator greater for signal <GND_190_o_l2p_len_cnt[29]_LessThan_37_o> created at line 271
    Found 11-bit comparator greater for signal <n0097> created at line 401
    Found 11-bit comparator greater for signal <n0109> created at line 414
    Found 7-bit comparator equal for signal <wb_ack_cnt[6]_GND_190_o_equal_109_o> created at line 557
    Summary:
	inferred   8 Adder/Subtractor(s).
	inferred 301 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  23 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <l2p_dma_master> synthesized.

Synthesizing Unit <p2l_dma_master>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd".
        g_BYTE_SWAP = false
WARNING:Xst:647 - Input <dma_ctrl_carrier_addr_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_ctrl_len_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <dma_ctrl_byte_swap_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_pdm_hdr_length_i<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_pdm_hdr_cid_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_pdm_be_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <p2l_dma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_pdm_hdr_start_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3010 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd" line 493: Output port <full> of the instance <cmp_to_wb_fifo> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <l2p_64b_address>.
    Found 1-bit register for signal <is_next_item>.
    Found 1-bit register for signal <l2p_last_packet>.
    Found 1-bit register for signal <pdm_arb_req_o>.
    Found 1-bit register for signal <pdm_arb_valid_o>.
    Found 1-bit register for signal <pdm_arb_dframe_o>.
    Found 1-bit register for signal <dma_ctrl_done_t>.
    Found 1-bit register for signal <next_item_valid_o>.
    Found 1-bit register for signal <completion_error>.
    Found 1-bit register for signal <rx_error_t>.
    Found 1-bit register for signal <rx_error_o>.
    Found 1-bit register for signal <dma_ctrl_done_o>.
    Found 1-bit register for signal <dma_busy_error>.
    Found 1-bit register for signal <to_wb_fifo_din<61>>.
    Found 1-bit register for signal <to_wb_fifo_din<60>>.
    Found 1-bit register for signal <to_wb_fifo_din<59>>.
    Found 1-bit register for signal <to_wb_fifo_din<58>>.
    Found 1-bit register for signal <to_wb_fifo_din<57>>.
    Found 1-bit register for signal <to_wb_fifo_din<56>>.
    Found 1-bit register for signal <to_wb_fifo_din<55>>.
    Found 1-bit register for signal <to_wb_fifo_din<54>>.
    Found 1-bit register for signal <to_wb_fifo_din<53>>.
    Found 1-bit register for signal <to_wb_fifo_din<52>>.
    Found 1-bit register for signal <to_wb_fifo_din<51>>.
    Found 1-bit register for signal <to_wb_fifo_din<50>>.
    Found 1-bit register for signal <to_wb_fifo_din<49>>.
    Found 1-bit register for signal <to_wb_fifo_din<48>>.
    Found 1-bit register for signal <to_wb_fifo_din<47>>.
    Found 1-bit register for signal <to_wb_fifo_din<46>>.
    Found 1-bit register for signal <to_wb_fifo_din<45>>.
    Found 1-bit register for signal <to_wb_fifo_din<44>>.
    Found 1-bit register for signal <to_wb_fifo_din<43>>.
    Found 1-bit register for signal <to_wb_fifo_din<42>>.
    Found 1-bit register for signal <to_wb_fifo_din<41>>.
    Found 1-bit register for signal <to_wb_fifo_din<40>>.
    Found 1-bit register for signal <to_wb_fifo_din<39>>.
    Found 1-bit register for signal <to_wb_fifo_din<38>>.
    Found 1-bit register for signal <to_wb_fifo_din<37>>.
    Found 1-bit register for signal <to_wb_fifo_din<36>>.
    Found 1-bit register for signal <to_wb_fifo_din<35>>.
    Found 1-bit register for signal <to_wb_fifo_din<34>>.
    Found 1-bit register for signal <to_wb_fifo_din<33>>.
    Found 1-bit register for signal <to_wb_fifo_din<32>>.
    Found 1-bit register for signal <to_wb_fifo_din<31>>.
    Found 1-bit register for signal <to_wb_fifo_din<30>>.
    Found 1-bit register for signal <to_wb_fifo_din<29>>.
    Found 1-bit register for signal <to_wb_fifo_din<28>>.
    Found 1-bit register for signal <to_wb_fifo_din<27>>.
    Found 1-bit register for signal <to_wb_fifo_din<26>>.
    Found 1-bit register for signal <to_wb_fifo_din<25>>.
    Found 1-bit register for signal <to_wb_fifo_din<24>>.
    Found 1-bit register for signal <to_wb_fifo_din<23>>.
    Found 1-bit register for signal <to_wb_fifo_din<22>>.
    Found 1-bit register for signal <to_wb_fifo_din<21>>.
    Found 1-bit register for signal <to_wb_fifo_din<20>>.
    Found 1-bit register for signal <to_wb_fifo_din<19>>.
    Found 1-bit register for signal <to_wb_fifo_din<18>>.
    Found 1-bit register for signal <to_wb_fifo_din<17>>.
    Found 1-bit register for signal <to_wb_fifo_din<16>>.
    Found 1-bit register for signal <to_wb_fifo_din<15>>.
    Found 1-bit register for signal <to_wb_fifo_din<14>>.
    Found 1-bit register for signal <to_wb_fifo_din<13>>.
    Found 1-bit register for signal <to_wb_fifo_din<12>>.
    Found 1-bit register for signal <to_wb_fifo_din<11>>.
    Found 1-bit register for signal <to_wb_fifo_din<10>>.
    Found 1-bit register for signal <to_wb_fifo_din<9>>.
    Found 1-bit register for signal <to_wb_fifo_din<8>>.
    Found 1-bit register for signal <to_wb_fifo_din<7>>.
    Found 1-bit register for signal <to_wb_fifo_din<6>>.
    Found 1-bit register for signal <to_wb_fifo_din<5>>.
    Found 1-bit register for signal <to_wb_fifo_din<4>>.
    Found 1-bit register for signal <to_wb_fifo_din<3>>.
    Found 1-bit register for signal <to_wb_fifo_din<2>>.
    Found 1-bit register for signal <to_wb_fifo_din<1>>.
    Found 1-bit register for signal <to_wb_fifo_din<0>>.
    Found 1-bit register for signal <to_wb_fifo_wr>.
    Found 1-bit register for signal <p2l_dma_cyc_t>.
    Found 1-bit register for signal <p2l_dma_stb_t>.
    Found 32-bit register for signal <l2p_address_l>.
    Found 32-bit register for signal <pdm_arb_data_o>.
    Found 32-bit register for signal <next_item_carrier_addr_o>.
    Found 32-bit register for signal <next_item_host_addr_h_o>.
    Found 32-bit register for signal <next_item_host_addr_l_o>.
    Found 32-bit register for signal <next_item_len_o>.
    Found 32-bit register for signal <next_item_next_l_o>.
    Found 32-bit register for signal <next_item_next_h_o>.
    Found 32-bit register for signal <next_item_attrib_o>.
    Found 32-bit register for signal <p2l_dma_adr_o>.
    Found 32-bit register for signal <p2l_dma_dat_o>.
    Found 32-bit register for signal <l2p_address_h>.
    Found 30-bit register for signal <l2p_len_cnt>.
    Found 30-bit register for signal <target_addr_cnt>.
    Found 10-bit register for signal <l2p_len_header>.
    Found 3-bit register for signal <p2l_dma_current_state>.
    Found 11-bit register for signal <p2l_data_cnt>.
    Found 4-bit register for signal <p2l_dma_sel_o>.
    Found 7-bit register for signal <wb_write_cnt>.
    Found 7-bit register for signal <wb_ack_cnt>.
    Found finite state machine <FSM_7> for signal <p2l_dma_current_state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 16                                             |
    | Inputs             | 9                                              |
    | Outputs            | 13                                             |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_n_i (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | p2l_idle                                       |
    | Power Up State     | p2l_idle                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 30-bit adder for signal <target_addr_cnt[29]_GND_203_o_add_79_OUT> created at line 1241.
    Found 7-bit adder for signal <wb_write_cnt[6]_GND_203_o_add_93_OUT> created at line 1241.
    Found 7-bit adder for signal <wb_ack_cnt[6]_GND_203_o_add_96_OUT> created at line 1241.
    Found 30-bit subtractor for signal <GND_203_o_GND_203_o_sub_12_OUT<29:0>>.
    Found 11-bit subtractor for signal <GND_203_o_GND_203_o_sub_50_OUT<10:0>>.
    Found 7-bit subtractor for signal <GND_203_o_GND_203_o_sub_89_OUT<6:0>>.
    Found 30-bit comparator greater for signal <GND_203_o_l2p_len_cnt[29]_LessThan_7_o> created at line 233
    Found 11-bit comparator greater for signal <n0046> created at line 338
    Found 7-bit comparator equal for signal <wb_ack_cnt[6]_GND_203_o_equal_90_o> created at line 550
    Summary:
	inferred   6 Adder/Subtractor(s).
	inferred 561 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   7 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <p2l_dma_master> synthesized.

Synthesizing Unit <l2p_arbiter>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_arbiter.vhd".
    Found 32-bit register for signal <arb_ser_data_t>.
    Found 32-bit register for signal <arb_ser_data_o>.
    Found 1-bit register for signal <arb_pdm_gnt>.
    Found 1-bit register for signal <arb_ldm_gnt>.
    Found 1-bit register for signal <arb_ser_valid_t>.
    Found 1-bit register for signal <arb_ser_dframe_t>.
    Found 1-bit register for signal <arb_ser_valid_o>.
    Found 1-bit register for signal <arb_ser_dframe_o>.
    Found 1-bit register for signal <arb_wbm_gnt>.
    Summary:
	inferred  71 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <l2p_arbiter> synthesized.

Synthesizing Unit <l2p_ser>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_ser_s6.vhd".
    Summary:
	no macro.
Unit <l2p_ser> synthesized.

Synthesizing Unit <serdes_n_to_1_s2_diff>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_diff.vhd".
        S = 2
        D = 1
WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <serdes_n_to_1_s2_diff> synthesized.

Synthesizing Unit <serdes_n_to_1_s2_se_1>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_se.vhd".
        S = 2
        D = 16
WARNING:Xst:653 - Signal <mdatainb<63:62>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<59:58>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<55:54>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<51:50>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<47:46>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<43:42>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<39:38>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<35:34>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<31:30>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<27:26>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<23:22>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<19:18>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<15:14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<11:10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<7:6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <serdes_n_to_1_s2_se_1> synthesized.

Synthesizing Unit <serdes_n_to_1_s2_se_2>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_se.vhd".
        S = 2
        D = 1
WARNING:Xst:653 - Signal <mdatainb<3:2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <serdes_n_to_1_s2_se_2> synthesized.

Synthesizing Unit <dummy_stat_regs_wb_slave>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_stat_regs.vhd".
WARNING:Xst:647 - Input <wb_data_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 32-bit 4-to-1 multiplexer for signal <rwaddr_reg[1]_dummy_stat_reg_switch_i[31]_wide_mux_8_OUT> created at line 82.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <dummy_stat_regs_wb_slave>.
    Summary:
	inferred  42 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
Unit <dummy_stat_regs_wb_slave> synthesized.

Synthesizing Unit <dummy_ctrl_regs_wb_slave>.
    Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dummy_ctrl_regs.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 8-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 32-bit register for signal <dummy_reg_1_int>.
    Found 32-bit register for signal <dummy_reg_2_int>.
    Found 32-bit register for signal <dummy_reg_3_int>.
    Found 32-bit register for signal <dummy_reg_led_int>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 32-bit 4-to-1 multiplexer for signal <rwaddr_reg[1]_dummy_reg_led_int[31]_wide_mux_13_OUT> created at line 90.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <dummy_ctrl_regs_wb_slave>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <dummy_ctrl_regs_wb_slave>.
    Summary:
	inferred 169 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
Unit <dummy_ctrl_regs_wb_slave> synthesized.
RTL-Simplification CPUSTAT: 2.09 
RTL-BasicInf CPUSTAT: 3.16 
RTL-BasicOpt CPUSTAT: 0.02 
RTL-Remain-Bus CPUSTAT: 0.15 

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 25
 11-bit subtractor                                     : 2
 12-bit adder                                          : 1
 2-bit adder                                           : 1
 3-bit adder                                           : 1
 30-bit adder                                          : 3
 30-bit subtractor                                     : 3
 32-bit adder                                          : 1
 4-bit adder                                           : 1
 5-bit addsub                                          : 2
 7-bit adder                                           : 4
 7-bit subtractor                                      : 2
 8-bit adder                                           : 1
 9-bit adder                                           : 3
# Registers                                            : 365
 1-bit register                                        : 245
 10-bit register                                       : 3
 11-bit register                                       : 2
 12-bit register                                       : 1
 16-bit register                                       : 2
 2-bit register                                        : 10
 3-bit register                                        : 3
 30-bit register                                       : 5
 31-bit register                                       : 1
 32-bit register                                       : 73
 4-bit register                                        : 7
 5-bit register                                        : 2
 64-bit register                                       : 1
 7-bit register                                        : 4
 8-bit register                                        : 1
 9-bit register                                        : 5
# Latches                                              : 32
 1-bit latch                                           : 32
# Comparators                                          : 8
 11-bit comparator greater                             : 3
 2-bit comparator greater                              : 1
 30-bit comparator greater                             : 2
 7-bit comparator equal                                : 2
# Multiplexers                                         : 258
 1-bit 2-to-1 multiplexer                              : 142
 1-bit 3-to-1 multiplexer                              : 33
 10-bit 2-to-1 multiplexer                             : 3
 11-bit 2-to-1 multiplexer                             : 6
 12-bit 2-to-1 multiplexer                             : 1
 2-bit 2-to-1 multiplexer                              : 1
 30-bit 2-to-1 multiplexer                             : 8
 32-bit 2-to-1 multiplexer                             : 46
 32-bit 3-to-1 multiplexer                             : 1
 32-bit 4-to-1 multiplexer                             : 2
 4-bit 2-to-1 multiplexer                              : 5
 5-bit 2-to-1 multiplexer                              : 6
 64-bit 2-to-1 multiplexer                             : 1
 9-bit 2-to-1 multiplexer                              : 3
# FSMs                                                 : 9

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <../ip_cores/ram_2048x32.ngc>.
Reading core <../ip_cores/fifo_32x512.ngc>.
Reading core <../ip_cores/fifo_64x512.ngc>.
Loading core <ram_2048x32> for timing and area information for instance <cmp_test_ram>.
Loading core <fifo_32x512> for timing and area information for instance <cmp_data_fifo>.
Loading core <fifo_32x512> for timing and area information for instance <cmp_addr_fifo>.
Loading core <fifo_64x512> for timing and area information for instance <cmp_to_wb_fifo>.
Loading core <fifo_64x512> for timing and area information for instance <cmp_fifo_to_wb>.
Loading core <fifo_32x512> for timing and area information for instance <cmp_from_wb_fifo>.
INFO:Xst:2261 - The FF/Latch <addr_fifo_din_30> in Unit <cmp_l2p_dma_master> is equivalent to the following FF/Latch, which will be removed : <addr_fifo_din_31> 
INFO:Xst:2261 - The FF/Latch <p2l_dma_adr_o_30> in Unit <cmp_p2l_dma_master> is equivalent to the following FF/Latch, which will be removed : <p2l_dma_adr_o_31> 
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_8> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_9> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_10> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_11> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_12> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_13> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_14> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_15> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_16> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_17> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_18> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_19> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_20> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_21> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_22> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_23> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_24> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_25> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_26> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_27> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_28> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_29> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_30> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_31> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_8> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_8> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_1> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_2> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_3> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_4> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_5> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_6> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_7> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_8> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_9> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_10> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_11> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_12> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_5> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_4> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <p2l_dma_adr_o_30> (without init value) has a constant value of 0 in block <cmp_p2l_dma_master>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <addr_fifo_din_30> (without init value) has a constant value of 0 in block <cmp_l2p_dma_master>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_valid_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_13> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_14> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_15> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_valid_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <cmp_dframe_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <cmp_dframe_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <inc_data_int> (without init value) has a constant value of 0 in block <cmp_data_in>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <wb_adr_t_4> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_5> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_6> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_7> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_8> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_9> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_10> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_11> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_12> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_13> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_14> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_15> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_21> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_22> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_len_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_len_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2404 -  FFs/Latches <addr_fifo_din<31:30>> (without init value) have a constant value of 0 in block <l2p_dma_master>.
WARNING:Xst:2404 -  FFs/Latches <p2l_dma_adr_o<31:30>> (without init value) have a constant value of 0 in block <p2l_dma_master>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:6>> (without init value) have a constant value of 0 in block <dma_controller_wb_slave>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:1>> (without init value) have a constant value of 0 in block <dummy_stat_regs_wb_slave>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<7:1>> (without init value) have a constant value of 0 in block <dummy_ctrl_regs_wb_slave>.

Synthesizing (advanced) Unit <l2p_dma_master>.
The following registers are absorbed into counter <dma_length_cnt>: 1 register on signal <dma_length_cnt>.
The following registers are absorbed into counter <target_addr_cnt>: 1 register on signal <target_addr_cnt>.
The following registers are absorbed into counter <wb_read_cnt>: 1 register on signal <wb_read_cnt>.
The following registers are absorbed into counter <wb_ack_cnt>: 1 register on signal <wb_ack_cnt>.
Unit <l2p_dma_master> synthesized (advanced).

Synthesizing (advanced) Unit <p2l_dma_master>.
The following registers are absorbed into counter <target_addr_cnt>: 1 register on signal <target_addr_cnt>.
The following registers are absorbed into counter <p2l_data_cnt>: 1 register on signal <p2l_data_cnt>.
The following registers are absorbed into counter <wb_write_cnt>: 1 register on signal <wb_write_cnt>.
The following registers are absorbed into counter <wb_ack_cnt>: 1 register on signal <wb_ack_cnt>.
Unit <p2l_dma_master> synthesized (advanced).

Synthesizing (advanced) Unit <pfc_wrapper>.
The following registers are absorbed into counter <clk_div_cnt>: 1 register on signal <clk_div_cnt>.
Unit <pfc_wrapper> synthesized (advanced).

Synthesizing (advanced) Unit <serdes_1_to_n_clk_pll_s2_diff>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <serdes_1_to_n_clk_pll_s2_diff> synthesized (advanced).

Synthesizing (advanced) Unit <serdes_1_to_n_data_s2_se_1>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <serdes_1_to_n_data_s2_se_1> synthesized (advanced).

Synthesizing (advanced) Unit <serdes_1_to_n_data_s2_se_2>.
The following registers are absorbed into counter <counter>: 1 register on signal <counter>.
Unit <serdes_1_to_n_data_s2_se_2> synthesized (advanced).
WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_21> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_22> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <wbmaster32>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 11
 11-bit subtractor                                     : 1
 2-bit adder                                           : 1
 30-bit adder                                          : 1
 30-bit subtractor                                     : 2
 32-bit adder                                          : 1
 5-bit addsub                                          : 2
 7-bit subtractor                                      : 2
 8-bit adder                                           : 1
# Counters                                             : 14
 11-bit down counter                                   : 1
 12-bit up counter                                     : 1
 3-bit up counter                                      : 1
 30-bit down counter                                   : 1
 30-bit up counter                                     : 2
 4-bit up counter                                      : 1
 7-bit up counter                                      : 4
 9-bit up counter                                      : 3
# Registers                                            : 2860
 Flip-Flops                                            : 2860
# Comparators                                          : 8
 11-bit comparator greater                             : 3
 2-bit comparator greater                              : 1
 30-bit comparator greater                             : 2
 7-bit comparator equal                                : 2
# Multiplexers                                         : 589
 1-bit 2-to-1 multiplexer                              : 492
 1-bit 3-to-1 multiplexer                              : 33
 10-bit 2-to-1 multiplexer                             : 3
 11-bit 2-to-1 multiplexer                             : 5
 2-bit 2-to-1 multiplexer                              : 1
 30-bit 2-to-1 multiplexer                             : 5
 32-bit 2-to-1 multiplexer                             : 37
 32-bit 3-to-1 multiplexer                             : 1
 32-bit 4-to-1 multiplexer                             : 2
 4-bit 2-to-1 multiplexer                              : 4
 5-bit 2-to-1 multiplexer                              : 6
# FSMs                                                 : 9

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <inc_data_int> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_15> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_14> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_13> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_12> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_11> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_10> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_9> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_8> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_7> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_6> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_5> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_4> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_3> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_2> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_1> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ce_data_0> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <incdec_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <busy_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <valid_data_d> (without init value) has a constant value of 0 in block <serdes_1_to_n_data_s2_se_2>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <l2p_dma_sel_o_0> in Unit <l2p_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <l2p_dma_sel_o_1> <l2p_dma_sel_o_2> <l2p_dma_sel_o_3> <l2p_dma_stb_t> 
INFO:Xst:2261 - The FF/Latch <p2l_dma_stb_t> in Unit <p2l_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <p2l_dma_sel_o_0> <p2l_dma_sel_o_1> <p2l_dma_sel_o_2> <p2l_dma_sel_o_3> 
INFO:Xst:2261 - The FF/Latch <dma_stat_int_read_3> in Unit <dma_controller_wb_slave> is equivalent to the following 28 FFs/Latches, which will be removed : <dma_stat_int_read_4> <dma_stat_int_read_5> <dma_stat_int_read_6> <dma_stat_int_read_7> <dma_stat_int_read_8> <dma_stat_int_read_9> <dma_stat_int_read_10> <dma_stat_int_read_11> <dma_stat_int_read_12> <dma_stat_int_read_13> <dma_stat_int_read_14> <dma_stat_int_read_15> <dma_stat_int_read_16> <dma_stat_int_read_17> <dma_stat_int_read_18> <dma_stat_int_read_19> <dma_stat_int_read_20> <dma_stat_int_read_21> <dma_stat_int_read_22> <dma_stat_int_read_23> <dma_stat_int_read_24> <dma_stat_int_read_25> <dma_stat_int_read_26> <dma_stat_int_read_27> <dma_stat_int_read_28> <dma_stat_int_read_29> <dma_stat_int_read_30> <dma_stat_int_read_31> 
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/FSM_1> on signal <state[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0010  | 0010
 0011  | 0011
 0100  | 0100
 0101  | 0101
 0110  | 0110
 0111  | 0111
 0001  | 0001
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/FSM_2> on signal <state[1:4]> with user encoding.
Optimizing FSM <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/FSM_2> on signal <state[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0010  | 0010
 0011  | 0011
 0100  | 0100
 0101  | 0101
 0110  | 0110
 0111  | 0111
 0001  | 0001
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_l2p_dma_master/FSM_6> on signal <l2p_dma_current_state[1:3]> with user encoding.
---------------------------
 State         | Encoding
---------------------------
 l2p_idle      | 000
 l2p_wait_data | 001
 l2p_header    | 010
 l2p_addr_h    | 011
 l2p_addr_l    | 100
 l2p_data      | 101
 l2p_last_data | 110
 l2p_wait_rdy  | 111
---------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_p2l_dma_master/FSM_7> on signal <p2l_dma_current_state[1:3]> with user encoding.
--------------------------------------
 State                    | Encoding
--------------------------------------
 p2l_idle                 | 000
 p2l_header               | 001
 p2l_addr_h               | 010
 p2l_addr_l               | 011
 p2l_wait_read_completion | 100
--------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_clk_in/FSM_0> on signal <state[1:9]> with one-hot encoding.
--------------------
 State | Encoding
--------------------
 0000  | 000000001
 0001  | 000000010
 0010  | 000000100
 0011  | 000001000
 0100  | 000010000
 0101  | 000100000
 0111  | 001000000
 1001  | 010000000
 0110  | 100000000
--------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_wbmaster32/FSM_3> on signal <l2p_read_cpl_current_state[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 l2p_idle   | 00
 l2p_header | 01
 l2p_data   | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_wbmaster32/FSM_4> on signal <wishbone_current_state[1:2]> with user encoding.
--------------------------
 State        | Encoding
--------------------------
 wb_idle      | 00
 wb_read_fifo | 01
 wb_cycle     | 10
 wb_wait_ack  | 11
--------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_gn4124_core/cmp_dma_controller/FSM_5> on signal <dma_ctrl_current_state[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 dma_idle           | 000
 dma_start_transfer | 001
 dma_transfer       | 010
 dma_start_chain    | 011
 dma_chain          | 100
 dma_error          | 101
 dma_abort          | 110
--------------------------------
WARNING:Xst:1710 - FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <wb_sel_t_0> in Unit <wbmaster32> is equivalent to the following 3 FFs/Latches, which will be removed : <wb_sel_t_1> <wb_sel_t_2> <wb_sel_t_3> 
INFO:Xst:2261 - The FF/Latch <wb_cyc_t> in Unit <wbmaster32> is equivalent to the following FF/Latch, which will be removed : <wb_stb_t> 

Optimizing unit <pfc_wrapper> ...

Optimizing unit <gn4124_core> ...

Optimizing unit <p2l_des> ...

Optimizing unit <serdes_1_to_n_data_s2_se_1> ...

Optimizing unit <serdes_1_to_n_data_s2_se_2> ...

Optimizing unit <l2p_dma_master> ...

Optimizing unit <p2l_dma_master> ...

Optimizing unit <serdes_1_to_n_clk_pll_s2_diff> ...

Optimizing unit <wbmaster32> ...

Optimizing unit <dma_controller> ...

Optimizing unit <dma_controller_wb_slave> ...

Optimizing unit <p2l_decode32> ...

Optimizing unit <l2p_arbiter> ...

Optimizing unit <serdes_n_to_1_s2_se_1> ...

Optimizing unit <dummy_stat_regs_wb_slave> ...

Optimizing unit <dummy_ctrl_regs_wb_slave> ...
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_1> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/ce_data_inta> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/inc_data_int> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/ce_data_0> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_1> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/ce_data_inta> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/inc_data_int> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/ce_data_0> (without init value) has a constant value of 0 in block <pfc_wrapper>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_sint> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_15> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_14> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_13> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_12> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_11> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_10> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_9> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_8> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_7> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_6> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_5> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_4> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_data_in/mux_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/cal_data_sint> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/cal_data_sint> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_31> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_30> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_29> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_28> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_27> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_26> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_25> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_24> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_23> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_22> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_21> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_20> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_19> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_18> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_17> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_16> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_15> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_14> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_13> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_12> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_11> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_29> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_28> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_27> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_26> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_25> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_24> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_23> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_22> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_21> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_20> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_19> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_18> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_17> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_16> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_15> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_14> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_13> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_12> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_adr_o_11> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_sel_t_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_15> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_14> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_13> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_12> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_11> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_10> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_9> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_8> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_7> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_6> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_5> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_4> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_len_o_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_len_o_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_load_o> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_31> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_30> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_29> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_28> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_27> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_26> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_25> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_24> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_23> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_22> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_21> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_20> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_19> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_18> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_17> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_16> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_15> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_14> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_13> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_12> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_11> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_10> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_9> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_8> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_7> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_6> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_5> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_4> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_o_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_31> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_30> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_29> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_28> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_27> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_26> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_25> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_24> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_23> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_22> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_21> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_20> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_19> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_18> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_17> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_16> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_15> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_14> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_13> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_12> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_11> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_10> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_9> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_8> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_7> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_6> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_5> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_4> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_int_write_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_be_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_last> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_lbe_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_fbe_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_stat_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_stat_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_9> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_8> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_7> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_6> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_5> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_4> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_1> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_4> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/pdcounter_0> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_4> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_3> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_2> of sequential type is unconnected in block <pfc_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/pdcounter_0> of sequential type is unconnected in block <pfc_wrapper>.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pfc_wrapper, actual ratio is 5.
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <BU2> is equivalent to the following 2 FFs/Latches : <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> <U0/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> 
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i> 

Final Macro Processing ...

Processing Unit <pfc_wrapper> :
	Found 4-bit shift register for signal <cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1>.
Unit <pfc_wrapper> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 2805
 Flip-Flops                                            : 2805
# Shift Registers                                      : 1
 4-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : pfc_wrapper.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 3127
#      GND                         : 7
#      INV                         : 72
#      LUT1                        : 56
#      LUT2                        : 331
#      LUT3                        : 654
#      LUT4                        : 389
#      LUT5                        : 363
#      LUT6                        : 512
#      MUXCY                       : 438
#      MUXF7                       : 13
#      VCC                         : 7
#      XORCY                       : 285
# FlipFlops/Latches                : 3622
#      FD                          : 23
#      FDC                         : 950
#      FDCE                        : 2484
#      FDE                         : 31
#      FDP                         : 72
#      FDPE                        : 30
#      LDC                         : 32
# RAMS                             : 11
#      RAMB16BWER                  : 11
# Shift Registers                  : 1
#      SRLC16E                     : 1
# Clock Buffers                    : 3
#      BUFG                        : 3
# IO Buffers                       : 59
#      BUFIO2                      : 1
#      IBUF                        : 24
#      IBUFDS                      : 3
#      OBUF                        : 30
#      OBUFDS                      : 1
# Others                           : 62
#      BUFIO2FB                    : 1
#      BUFPLL                      : 1
#      IODELAY2                    : 20
#      ISERDES2                    : 20
#      OSERDES2                    : 19
#      PLL_ADV                     : 1

Device utilization summary:
---------------------------

Selected Device : 6slx150tfgg676-3 


Slice Logic Utilization: 
 Number of Slice Registers:            3622  out of  184304     1%  
 Number of Slice LUTs:                 2378  out of  92152     2%  
    Number used as Logic:              2377  out of  92152     2%  
    Number used as Memory:                1  out of  21680     0%  
       Number used as SRL:                1

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   4463
   Number with an unused Flip Flop:     841  out of   4463    18%  
   Number with an unused LUT:          2085  out of   4463    46%  
   Number of fully used LUT-FF pairs:  1537  out of   4463    34%  
   Number of unique control sets:       169

IO Utilization: 
 Number of IOs:                          68
 Number of bonded IOBs:                  62  out of    396    15%  

Specific Feature Utilization:
 Number of Block RAM/FIFO:               11  out of    268     4%  
    Number using Block RAM only:         11
 Number of BUFG/BUFGCTRLs:                3  out of     16    18%  
 Number of PLL_ADVs:                      1  out of      6    16%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
Clock Signal                                                                   | Clock buffer(FF name)                                                                                     | Load  |
-------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
L_CLKp                                                                         | IBUFDS+BUFG                                                                                               | 1116  |
cmp_gn4124_core/cmp_clk_in/buf_P_clk                                           | cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst:CLKOUT2                                                        | 2493  |
cmp_gn4124_core/cmp_wbmaster32/_n0326(cmp_gn4124_core/cmp_wbmaster32/_n03261:O)| BUFG(*)(cmp_gn4124_core/cmp_wbmaster32/s_wb_dat_i_muxed_0)                                                | 32    |
cmp_test_ram/BU2/doutb(0)                                                      | NONE(cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram)| 4     |
-------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 6.848ns (Maximum Frequency: 146.022MHz)
   Minimum input arrival time before clock: 4.574ns
   Maximum output required time after clock: 4.828ns
   Maximum combinational path delay: 4.115ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'L_CLKp'
  Clock period: 5.849ns (frequency: 170.962MHz)
  Total number of paths / destination ports: 9719 / 2378
-------------------------------------------------------------------------
Delay:               5.849ns (Levels of Logic = 4)
  Source:            cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1 (FF)
  Destination:       cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_31 (FF)
  Source Clock:      L_CLKp rising
  Destination Clock: L_CLKp rising

  Data Path: cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1 to cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            56   0.525   1.588  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_1)
     LUT2:I1->O           31   0.254   1.506  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg[1]_dma_cstart_lw_read_in_progress_AND_109_o1 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg[1]_dma_cstart_lw_read_in_progress_AND_109_o)
     LUT6:I3->O            1   0.235   0.580  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT962 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT961)
     LUT6:I5->O            1   0.254   0.580  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT963 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT962)
     LUT6:I5->O            1   0.254   0.000  cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/Mmux_rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT964 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg[31]_dma_attrib_int_read[31]_mux_12_OUT<9>)
     FDCE:D                    0.074          cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_9
    ----------------------------------------
    Total                      5.849ns (1.596ns logic, 4.253ns route)
                                       (27.3% logic, 72.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cmp_gn4124_core/cmp_clk_in/buf_P_clk'
  Clock period: 6.848ns (frequency: 146.022MHz)
  Total number of paths / destination ports: 31681 / 6549
-------------------------------------------------------------------------
Delay:               6.848ns (Levels of Logic = 3)
  Source:            cmp_gn4124_core/cmp_dma_controller/dma_len_reg_27 (FF)
  Destination:       cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_31 (FF)
  Source Clock:      cmp_gn4124_core/cmp_clk_in/buf_P_clk rising +90
  Destination Clock: cmp_gn4124_core/cmp_clk_in/buf_P_clk rising +90

  Data Path: cmp_gn4124_core/cmp_dma_controller/dma_len_reg_27 to cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             3   0.525   1.106  cmp_gn4124_core/cmp_dma_controller/dma_len_reg_27 (cmp_gn4124_core/cmp_dma_controller/dma_len_reg_27)
     LUT6:I0->O            1   0.254   1.010  cmp_gn4124_core/cmp_dma_controller/_n0212_inv31 (cmp_gn4124_core/cmp_dma_controller/_n0212_inv3)
     LUT5:I0->O          101   0.254   1.880  cmp_gn4124_core/cmp_dma_controller/_n0212_inv36 (cmp_gn4124_core/cmp_dma_controller/_n0212_inv_bdd2)
     LUT4:I3->O           30   0.254   1.263  cmp_gn4124_core/cmp_dma_controller/_n0212_inv11 (cmp_gn4124_core/cmp_dma_controller/_n0212_inv)
     FDCE:CE                   0.302          cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o_2
    ----------------------------------------
    Total                      6.848ns (1.589ns logic, 5.259ns route)
                                       (23.2% logic, 76.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'L_CLKp'
  Total number of paths / destination ports: 201 / 201
-------------------------------------------------------------------------
Offset:              4.574ns (Levels of Logic = 2)
  Source:            L_RST_N (PAD)
  Destination:       dma_ack_i (FF)
  Destination Clock: L_CLKp rising

  Data Path: L_RST_N to dma_ack_i
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.228   0.579  L_RST_N_IBUF (L_RST_N_IBUF)
     INV:I->O            201   0.255   2.053  L_RST_N_inv1_INV_0 (L_RST_N_inv)
     FDC:CLR                   0.459          dma_ack_i
    ----------------------------------------
    Total                      4.574ns (1.942ns logic, 2.632ns route)
                                       (42.5% logic, 57.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'cmp_gn4124_core/cmp_clk_in/buf_P_clk'
  Total number of paths / destination ports: 63 / 63
-------------------------------------------------------------------------
Offset:              4.574ns (Levels of Logic = 2)
  Source:            L_RST_N (PAD)
  Destination:       cmp_gn4124_core/rst_reg (FF)
  Destination Clock: cmp_gn4124_core/cmp_clk_in/buf_P_clk rising +90

  Data Path: L_RST_N to cmp_gn4124_core/rst_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.228   0.579  L_RST_N_IBUF (L_RST_N_IBUF)
     INV:I->O            201   0.255   2.053  L_RST_N_inv1_INV_0 (L_RST_N_inv)
     FDCE:CLR                  0.459          cmp_gn4124_core/rst_reg
    ----------------------------------------
    Total                      4.574ns (1.942ns logic, 2.632ns route)
                                       (42.5% logic, 57.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cmp_gn4124_core/cmp_clk_in/buf_P_clk'
  Total number of paths / destination ports: 119 / 117
-------------------------------------------------------------------------
Offset:              4.828ns (Levels of Logic = 3)
  Source:            cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i (FF)
  Destination:       P2L_RDY (PAD)
  Source Clock:      cmp_gn4124_core/cmp_clk_in/buf_P_clk rising +90

  Data Path: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i to P2L_RDY
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              3   0.525   0.759  U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i (prog_full)
     end scope: 'BU2'
     end scope: 'cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb'
     LUT2:I0->O            1   0.250   0.579  cmp_gn4124_core/p2l_rdy_o1 (P2L_RDY_OBUF)
     OBUF:I->O                 2.715          P2L_RDY_OBUF (P2L_RDY)
    ----------------------------------------
    Total                      4.828ns (3.490ns logic, 1.338ns route)
                                       (72.3% logic, 27.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'L_CLKp'
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset:              3.856ns (Levels of Logic = 1)
  Source:            cmp_dummy_ctrl_regs/dummy_reg_led_int_0 (FF)
  Destination:       LED_RED (PAD)
  Source Clock:      L_CLKp rising

  Data Path: cmp_dummy_ctrl_regs/dummy_reg_led_int_0 to LED_RED
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.525   0.616  cmp_dummy_ctrl_regs/dummy_reg_led_int_0 (cmp_dummy_ctrl_regs/dummy_reg_led_int_0)
     OBUF:I->O                 2.715          LED_RED_OBUF (LED_RED)
    ----------------------------------------
    Total                      3.856ns (3.240ns logic, 0.616ns route)
                                       (84.0% logic, 16.0% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 165 / 163
-------------------------------------------------------------------------
Delay:               4.115ns (Levels of Logic = 2)
  Source:            L_RST_N (PAD)
  Destination:       cmp_gn4124_core/cmp_clk_in/iserdes_s:RST (PAD)

  Data Path: L_RST_N to cmp_gn4124_core/cmp_clk_in/iserdes_s:RST
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.228   0.579  L_RST_N_IBUF (L_RST_N_IBUF)
     INV:I->O            201   0.255   2.053  L_RST_N_inv1_INV_0 (L_RST_N_inv)
    ISERDES2:RST               0.000          cmp_gn4124_core/cmp_clk_in/iserdes_m
    ----------------------------------------
    Total                      4.115ns (1.483ns logic, 2.632ns route)
                                       (36.0% logic, 64.0% route)

=========================================================================


Total REAL time to Xst completion: 87.00 secs
Total CPU time to Xst completion: 86.97 secs
 
--> 


Total memory usage is 181284 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  434 (   0 filtered)
Number of infos    :   80 (   0 filtered)

