--------------------------------------------------------------------------------
Release 12.2 Trace  (lin)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

/opt/Xilinx/12.2/ISE_DS/ISE/bin/lin/unwrapped/trce -intstyle ise -v 3 -s 3 -n 3
-fastpaths -xml pfc_wrapper.twx pfc_wrapper.ncd -o pfc_wrapper.twr
pfc_wrapper.pcf

Design file:              pfc_wrapper.ncd
Physical constraint file: pfc_wrapper.pcf
Device,package,speed:     xc6slx150t,fgg676,C,-3 (PRELIMINARY 1.10 2010-06-28)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: NET "L2P_RDY_IBUF" MAXDELAY = 2 ns;

 1 net analyzed, 0 failing nets detected.
 0 timing errors detected.
 Maximum net delay is   0.324ns.
--------------------------------------------------------------------------------
Slack:                  1.676ns L2P_RDY_IBUF
Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
From                              To                                Delay(ns)
U9.I                              ILOGIC_X0Y41.D                        0.324  

--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;

 0 nets analyzed, 0 failing nets detected.
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;

 1 net analyzed, 0 failing nets detected.
 0 timing errors detected.
 Maximum net delay is   0.324ns.
--------------------------------------------------------------------------------
Slack:                  1.676ns L_WR_RDY_1_IBUF
Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
From                              To                                Delay(ns)
R4.I                              ILOGIC_X0Y109.D                       0.324  

--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;

 0 nets analyzed, 0 failing nets detected.
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;

 1 net analyzed, 0 failing nets detected.
 0 timing errors detected.
 Maximum net delay is   0.324ns.
--------------------------------------------------------------------------------
Slack:                  1.676ns L_WR_RDY_0_IBUF
Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
From                              To                                Delay(ns)
V7.I                              ILOGIC_X0Y21.D                        0.324  

--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "P_RD_D_RDY_1_IBUF" MAXDELAY = 2 ns;

 1 net analyzed, 0 failing nets detected.
 0 timing errors detected.
 Maximum net delay is   0.324ns.
--------------------------------------------------------------------------------
Slack:                  1.676ns P_RD_D_RDY_1_IBUF
Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
From                              To                                Delay(ns)
U5.I                              ILOGIC_X0Y97.D                        0.324  

--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "P_RD_D_RDY_0_IBUF" MAXDELAY = 2 ns;

 1 net analyzed, 0 failing nets detected.
 0 timing errors detected.
 Maximum net delay is   0.324ns.
--------------------------------------------------------------------------------
Slack:                  1.676ns P_RD_D_RDY_0_IBUF
Report:    0.324ns delay meets   2.000ns timing constraint by 1.676ns
From                              To                                Delay(ns)
U2.I                              ILOGIC_X0Y85.D                        0.324  

--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;

 0 nets analyzed, 0 failing nets detected.
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;

 1 net analyzed, 0 failing nets detected.
 0 timing errors detected.
 Maximum net delay is   0.000ns.
--------------------------------------------------------------------------------
Slack:                  2.000ns VC_RDY<1>_IBUF
Report:    0.000ns delay meets   2.000ns timing constraint by 2.000ns
From                              To                                Delay(ns)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;

 0 nets analyzed, 0 failing nets detected.
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;

 1 net analyzed, 0 failing nets detected.
 0 timing errors detected.
 Maximum net delay is   0.000ns.
--------------------------------------------------------------------------------
Slack:                  2.000ns VC_RDY<0>_IBUF
Report:    0.000ns delay meets   2.000ns timing constraint by 2.000ns
From                              To                                Delay(ns)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_l_clkp = PERIOD TIMEGRP "l_clkp_grp" 5 ns HIGH 50%;

 9309 paths analyzed, 3250 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   4.795ns.
--------------------------------------------------------------------------------

Paths for end point cmp_dummy_ctrl_regs/dummy_reg_3_int_6 (SLICE_X56Y72.CX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.205ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_6 (FF)
  Destination:          cmp_dummy_ctrl_regs/dummy_reg_3_int_6 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.804ns (Levels of Logic = 0)
  Clock Path Skew:      0.044ns (0.893 - 0.849)
  Source Clock:         l_clk_BUFG rising at 0.000ns
  Destination Clock:    l_clk_BUFG rising at 5.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_6 to cmp_dummy_ctrl_regs/dummy_reg_3_int_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X43Y48.CQ      Tcko                  0.430   cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t<7>
                                                       cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_6
    SLICE_X56Y72.CX      net (fanout=12)       4.289   cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t<6>
    SLICE_X56Y72.CLK     Tdick                 0.085   cmp_dummy_ctrl_regs/dummy_reg_3_int<7>
                                                       cmp_dummy_ctrl_regs/dummy_reg_3_int_6
    -------------------------------------------------  ---------------------------
    Total                                      4.804ns (0.515ns logic, 4.289ns route)
                                                       (10.7% logic, 89.3% route)

--------------------------------------------------------------------------------

Paths for end point cmp_dummy_ctrl_regs/dummy_reg_3_int_20 (SLICE_X50Y72.AX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.207ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_20 (FF)
  Destination:          cmp_dummy_ctrl_regs/dummy_reg_3_int_20 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.802ns (Levels of Logic = 0)
  Clock Path Skew:      0.044ns (0.892 - 0.848)
  Source Clock:         l_clk_BUFG rising at 0.000ns
  Destination Clock:    l_clk_BUFG rising at 5.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_20 to cmp_dummy_ctrl_regs/dummy_reg_3_int_20
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X42Y49.AMUX    Tshcko                0.535   cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t<11>
                                                       cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t_20
    SLICE_X50Y72.AX      net (fanout=12)       4.153   cmp_gn4124_core/cmp_wbmaster32/wb_dat_o_t<20>
    SLICE_X50Y72.CLK     Tdick                 0.114   cmp_dummy_ctrl_regs/dummy_reg_3_int<23>
                                                       cmp_dummy_ctrl_regs/dummy_reg_3_int_20
    -------------------------------------------------  ---------------------------
    Total                                      4.802ns (0.649ns logic, 4.153ns route)
                                                       (13.5% logic, 86.5% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_0 (SLICE_X70Y73.AX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.207ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_0 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.545ns (Levels of Logic = 0)
  Clock Path Skew:      -0.213ns (0.715 - 0.928)
  Source Clock:         l_clk_BUFG rising at 0.000ns
  Destination Clock:    l_clk_BUFG rising at 5.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram to cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X2Y38.DOB0    Trcko_DOB             2.100   cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    SLICE_X70Y73.AX      net (fanout=1)        2.331   cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_dout<0>
    SLICE_X70Y73.CLK     Tdick                 0.114   cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o<2>
                                                       cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_adr_o_0
    -------------------------------------------------  ---------------------------
    Total                                      4.545ns (2.214ns logic, 2.331ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------

Hold Paths: TS_l_clkp = PERIOD TIMEGRP "l_clkp_grp" 5 ns HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6 (SLICE_X24Y38.C5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.382ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_6 (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.382ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         l_clk_BUFG rising at 5.000ns
  Destination Clock:    l_clk_BUFG rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_6 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y38.CQ      Tcko                  0.200   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<7>
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_6
    SLICE_X24Y38.C5      net (fanout=1)        0.061   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<6>
    SLICE_X24Y38.CLK     Tah         (-Th)    -0.121   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<7>
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<6>_rt
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6
    -------------------------------------------------  ---------------------------
    Total                                      0.382ns (0.321ns logic, 0.061ns route)
                                                       (84.0% logic, 16.0% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3_8 (SLICE_X16Y82.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.392ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d2_8 (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.392ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         l_clk_BUFG rising at 5.000ns
  Destination Clock:    l_clk_BUFG rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d2_8 to cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y82.CQ      Tcko                  0.200   cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3<8>
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d2_8
    SLICE_X16Y82.DX      net (fanout=2)        0.144   cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d2<8>
    SLICE_X16Y82.CLK     Tckdi       (-Th)    -0.048   cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3<8>
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/wpntr/gic0.gc1.count_d3_8
    -------------------------------------------------  ---------------------------
    Total                                      0.392ns (0.248ns logic, 0.144ns route)
                                                       (63.3% logic, 36.7% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5 (SLICE_X24Y38.B5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.392ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5 (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.392ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         l_clk_BUFG rising at 5.000ns
  Destination Clock:    l_clk_BUFG rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y38.BQ      Tcko                  0.200   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<7>
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5
    SLICE_X24Y38.B5      net (fanout=1)        0.071   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<5>
    SLICE_X24Y38.CLK     Tah         (-Th)    -0.121   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<7>
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg<5>_rt
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5
    -------------------------------------------------  ---------------------------
    Total                                      0.392ns (0.321ns logic, 0.071ns route)
                                                       (81.9% logic, 18.1% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_l_clkp = PERIOD TIMEGRP "l_clkp_grp" 5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X3Y34.CLKA
  Clock network: l_clk_BUFG
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X3Y38.CLKA
  Clock network: l_clk_BUFG
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X3Y36.CLKA
  Clock network: l_clk_BUFG
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_grp" 5 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.904ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_grp" 5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 3.096ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 1.904ns (525.210MHz) (Tbufper_I)
  Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
  Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
  Location pin: BUFIO2_X1Y9.I
  Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   1.904ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 3.096ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 1.904ns (525.210MHz) (Tbufper_I)
  Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
  Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
  Location pin: BUFIO2_X1Y9.I
  Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP     
    "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.800ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clkp HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.549ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
  Location pin: PLL_ADV_X0Y0.CLKOUT0
  Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.000ns
  Low pulse: 2.500ns
  Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.000ns
  High pulse: 2.500ns
  High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP   
      "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   2.800ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clkn HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.549ns (period - min period limit)
  Period: 2.500ns
  Min period limit: 0.951ns (1051.525MHz) (Tpllper_CLKOUT(Foutmax))
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
  Location pin: PLL_ADV_X0Y0.CLKOUT0
  Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.000ns
  Low pulse: 2.500ns
  Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
--------------------------------------------------------------------------------
Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.000ns
  High pulse: 2.500ns
  High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
  Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
  Location pin: PLL_ADV_X0Y0.CLKIN2
  Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int = PERIOD 
TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int"         
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP  
       "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"         
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   3.570ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"
        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X3Y20.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X3Y22.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X2Y22.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0 = PERIOD 
TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0"         
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 / 2 HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD 
TIMEGRP         "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"         
TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;

 29021 paths analyzed, 8719 endpoints analyzed, 1 failing endpoint
 1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
 Minimum period is   5.579ns.
--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/l2p_rdy (SLICE_X32Y70.CX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     -0.579ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/l2p_rdy_t (FF)
  Destination:          cmp_gn4124_core/l2p_rdy (FF)
  Requirement:          5.000ns
  Data Path Delay:      5.065ns (Levels of Logic = 0)
  Clock Path Skew:      -0.439ns (0.892 - 1.331)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/l2p_rdy_t to cmp_gn4124_core/l2p_rdy
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X0Y41.Q4      Tickq                 1.220   cmp_gn4124_core/l2p_rdy_t
                                                       cmp_gn4124_core/l2p_rdy_t
    SLICE_X32Y70.CX      net (fanout=1)        3.731   cmp_gn4124_core/l2p_rdy_t
    SLICE_X32Y70.CLK     Tdick                 0.114   cmp_gn4124_core/l2p_rdy
                                                       cmp_gn4124_core/l2p_rdy
    -------------------------------------------------  ---------------------------
    Total                                      5.065ns (1.334ns logic, 3.731ns route)
                                                       (26.3% logic, 73.7% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/l_wr_rdy_0 (SLICE_X3Y59.DX), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.114ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/l_wr_rdy_t_0 (FF)
  Destination:          cmp_gn4124_core/l_wr_rdy_0 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.218ns (Levels of Logic = 0)
  Clock Path Skew:      -0.593ns (0.823 - 1.416)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/l_wr_rdy_t_0 to cmp_gn4124_core/l_wr_rdy_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X0Y21.Q4      Tickq                 1.220   cmp_gn4124_core/l_wr_rdy_t<0>
                                                       cmp_gn4124_core/l_wr_rdy_t_0
    SLICE_X3Y59.DX       net (fanout=1)        2.884   cmp_gn4124_core/l_wr_rdy_t<0>
    SLICE_X3Y59.CLK      Tdick                 0.114   cmp_gn4124_core/l_wr_rdy<0>
                                                       cmp_gn4124_core/l_wr_rdy_0
    -------------------------------------------------  ---------------------------
    Total                                      4.218ns (1.334ns logic, 2.884ns route)
                                                       (31.6% logic, 68.4% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_24 (SLICE_X44Y80.C6), 1 path
--------------------------------------------------------------------------------
Slack (setup path):     0.128ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Destination:          cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_24 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.957ns (Levels of Logic = 1)
  Clock Path Skew:      0.160ns (0.956 - 0.796)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 1.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.075ns

  Clock Uncertainty:          0.075ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.132ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_24
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X3Y42.DOB24   Trcko_DOB             2.100   cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    SLICE_X44Y80.C6      net (fanout=1)        2.518   cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_dout<24>
    SLICE_X44Y80.CLK     Tas                   0.339   cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<24>
                                                       cmp_gn4124_core/cmp_l2p_dma_master/Mmux_l2p_dma_current_state[2]_ldm_arb_data_o[31]_wide_mux_95_OUT17
                                                       cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_24
    -------------------------------------------------  ---------------------------
    Total                                      4.957ns (2.439ns logic, 2.518ns route)
                                                       (49.2% logic, 50.8% route)

--------------------------------------------------------------------------------

Hold Paths: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y24.DIA19), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.274ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_21 (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.277ns (Levels of Logic = 0)
  Clock Path Skew:      0.003ns (0.076 - 0.073)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_21 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X43Y50.BQ      Tcko                  0.198   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<23>
                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_21
    RAMB16_X2Y24.DIA19   net (fanout=2)        0.132   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<21>
    RAMB16_X2Y24.CLKA    Trckd_DIA   (-Th)     0.053   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.277ns (0.145ns logic, 0.132ns route)
                                                       (52.3% logic, 47.7% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y24.DIA21), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.274ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_23 (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.277ns (Levels of Logic = 0)
  Clock Path Skew:      0.003ns (0.076 - 0.073)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_23 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X43Y50.DQ      Tcko                  0.198   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<23>
                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_23
    RAMB16_X2Y24.DIA21   net (fanout=2)        0.132   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<23>
    RAMB16_X2Y24.CLKA    Trckd_DIA   (-Th)     0.053   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.277ns (0.145ns logic, 0.132ns route)
                                                       (52.3% logic, 47.7% route)

--------------------------------------------------------------------------------

Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAMB16_X2Y24.DIPA2), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.275ns (requirement - (clock path skew + uncertainty - data path))
  Source:               cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_26 (FF)
  Destination:          cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.278ns (Levels of Logic = 0)
  Clock Path Skew:      0.003ns (0.076 - 0.073)
  Source Clock:         cmp_gn4124_core/sys_clk rising at 6.250ns
  Destination Clock:    cmp_gn4124_core/sys_clk rising at 6.250ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_26 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X42Y50.CQ      Tcko                  0.200   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<27>
                                                       cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din_26
    RAMB16_X2Y24.DIPA2   net (fanout=2)        0.131   cmp_gn4124_core/cmp_wbmaster32/to_wb_fifo_din<26>
    RAMB16_X2Y24.CLKA    Trckd_DIPA  (-Th)     0.053   cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
                                                       cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram
    -------------------------------------------------  ---------------------------
    Total                                      0.278ns (0.147ns logic, 0.131ns route)
                                                       (52.9% logic, 47.1% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
        "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
        TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X3Y20.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X3Y22.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------
Slack: 1.430ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram/CLKA
  Location pin: RAMB16_X2Y22.CLKA
  Clock network: cmp_gn4124_core/sys_clk
--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_p2l_clkp
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkp                    |      5.000ns|      1.904ns|      3.570ns|            0|            0|            0|            0|
| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      3.570ns|            0|            0|            0|            0|
| buf_P_clk                     |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
|  _rx_pllout_xs_int            |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      3.570ns|          N/A|            0|            0|            0|            0|
|  _rx_pllout_x1                |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_p2l_clkn
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn                    |      5.000ns|      1.904ns|      5.579ns|            0|            1|            0|        29021|
| TS_cmp_gn4124_core_cmp_clk_in_|      5.000ns|      2.800ns|      5.579ns|            0|            1|            0|        29021|
| buf_P_clk_0                   |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      2.500ns|          N/A|          N/A|            0|            0|            0|            0|
|  _rx_pllout_xs_int_0          |             |             |             |             |             |             |             |
|  TS_cmp_gn4124_core_cmp_clk_in|      5.000ns|      5.579ns|          N/A|            1|            0|        29021|            0|
|  _rx_pllout_x1_0              |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock L_CLKn
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
L_CLKn         |    4.795|         |         |         |
L_CLKp         |    4.795|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock L_CLKp
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
L_CLKn         |    4.795|         |         |         |
L_CLKp         |    4.795|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock P2L_CLKn
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
P2L_CLKn       |    5.579|         |         |         |
P2L_CLKp       |    5.579|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock P2L_CLKp
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
P2L_CLKn       |    5.579|         |         |         |
P2L_CLKp       |    5.579|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 1  Score: 579  (Setup/Max: 579, Hold: 0)

Constraints cover 38330 paths, 7 nets, and 11571 connections

Design statistics:
   Minimum period:   5.579ns{1}   (Maximum frequency: 179.244MHz)
   Maximum net delay:   0.324ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Fri Dec 10 09:50:59 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 300 MB



