GN4124 core - Release 2.0
Sources
- "HDL sources":
Interface (entity) changes
- Additional generic, to set the ACk wait timeout (in wishbone clock
cycles).
- g_ACK_TIMEOUT
- Additional ports
- csr_err_i, used to terminate the wishbone cycle if asserted.
- csr_rty_i, not used. Reserved for future use.
- csr_int_i, not used. Reserved for future use.
- dma_err_i, not used. Reserved for future use.
- dma_rty_i, not used. Reserved for future use.
- dma_int_i, not used. Reserved for future use.
Release date
- 01 March 2014
04 February 2014