Skip to content

H
HDL Core Lib
Commit 17d7965e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

--no commit message 

--no commit message
parent cc54a8c2
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 2072 additions and 36 deletions
trunk/software/wbgen2/cgen_c_headers.lua
View file @ 17d7965e
......@@ -9,26 +9,22 @@
--
function cgen_c_field_define(field, reg)
local prefix=string.upper(periph.c_prefix).."_"..string.upper(reg.c_prefix).."_"..string.upper(field.c_prefix);
local prefix=string.upper(periph.c_prefix).."_"..string.upper(reg.c_prefix).."_"..string.upper(field.c_prefix);
emit("");
emit("/* definitions for field: "..field.name.." in reg: "..reg.name.." */");
if(field.type == BIT or field.type == MONOSTABLE) then
emit("#define "..prefix.." (1<<"..field.offset..")");
emit(string.format("%-45s %s", "#define "..prefix, "WBGEN2_GEN_MASK("..field.offset..", 1)"));
else
print(field.offset, field.size);
emit("#define "..prefix.."_MASK "..string.format("0x%08x", (math.pow(2, field.size)-1) * math.pow(2, field.offset)));
emit("#define "..prefix.."_SHIFT "..string.format("%d", field.offset));
emit("#define "..prefix.."_W(value) "..string.format("(((value) & 0x%08x) << %d)", math.pow(2, field.size)-1, field.offset));
-- emit("#define "..prefix.."_MASK "..string.format("0x%08x", (math.pow(2, field.size)-1) * math.pow(2, field.offset)));
emit(string.format("%-45s %s", "#define "..prefix.."_MASK", "WBGEN2_GEN_MASK("..field.offset..", "..field.size..")"));
emit(string.format("%-45s %d", "#define "..prefix.."_SHIFT", field.offset));
emit(string.format("%-45s %s", "#define "..prefix.."_W(value)", "WBGEN2_GEN_WRITE(value, "..field.offset..", "..field.size..")"));
if(field.type == SIGNED) then
emit("#define "..prefix.."_R(reg) "..string.format("( ((reg)&0x%08x ? 0x%08x : 0) | (((reg) >> %d) & 0x%08x))",
math.pow(2, field.offset + field.size - 1), -- sign mask
(math.pow(2, 32-field.size)-1) * math.pow(2, field.size), -- sign extension mask
field.offset,
math.pow(2, field.size)-1));
emit(string.format("%-45s %s", "#define "..prefix.."_R(reg)", "WBGEN2_SIGN_EXTEND(WBGEN2_GEN_READ(reg, "..field.offset..", "..field.size.."), "..field.size..")"));
else
emit("#define "..prefix.."_R(reg) "..string.format("(((reg) >> %d) & 0x%08x)", field.offset, math.pow(2, field.size)-1));
emit(string.format("%-45s %s", "#define "..prefix.."_R(reg)", "WBGEN2_GEN_READ(reg, "..field.offset..", "..field.size..")"));
end
end
end
......@@ -36,7 +32,7 @@ end
function cgen_c_ramdefs(ram)
local prefix = string.upper(periph.c_prefix).."_"..string.upper(ram.c_prefix);
emit("/* definitions for RAM: "..ram.name.." *);
emit("/* definitions for RAM: "..ram.name.." */");
emit(string.format("#define "..prefix.."_BYTES 0x%08x %-50s", ram.size * ram.width / 8, "/* size in bytes */"));
emit(string.format("#define "..prefix.."_WORDS 0x%08x %-50s", ram.size, "/* size in "..ram.width.."-bit words, 32-bit aligned */"));
......@@ -45,7 +41,8 @@ end
function cgen_c_field_masks()
foreach_reg(function(reg)
if(reg.__type == TYPE_REG and reg.num_fields ~= nil and reg.num_fields > 0) then
emit("/* definitions for register: "..reg.name.." */);
emit("");
emit("/* definitions for register: "..reg.name.." */");
foreach_subfield(reg, function(field, reg) cgen_c_field_define(field, reg) end);
elseif (reg.__type == TYPE_RAM) then
cgen_c_ramdefs(reg);
......@@ -102,8 +99,8 @@ function cgen_c_struct()
foreach_reg(function(reg)
if(reg.__type == TYPE_REG) then
pad_struct(reg.base);
emit("/* "..reg.name.." */");
emit("volatile uint32_t "..string.upper(reg.prefix)..";");
emit(string.format("/* [0x%x]: REG "..reg.name.." */", reg.base * DATA_BUS_WIDTH / 8));
emit("uint32_t "..string.upper(reg.prefix)..";");
cur_offset = cur_offset + 1;
end
end);
......@@ -116,7 +113,7 @@ function cgen_c_struct()
pad_struct(base);
emiti();
emitx("/* RAM: "..ram.name..", "..ram.size.." "..ram.width.."-bit words, "..DATA_BUS_WIDTH.."-bit aligned, "..csel(ram.byte_select, "byte", "word").."-addressable");
emitx(string.format("/* [0x%x - 0x%x]: RAM "..ram.name..", "..ram.size.." "..ram.width.."-bit words, "..DATA_BUS_WIDTH.."-bit aligned, "..csel(ram.byte_select, "byte", "word").."-addressable", base * DATA_BUS_WIDTH / 8, (base + math.pow(2, ram.wrap_bits)*ram.size) * (DATA_BUS_WIDTH / 8) - 1));
if(ram.wrap_bits > 0) then
emitx(", mirroring: "..math.pow(2, ram.wrap_bits).." times */\n");
......@@ -125,9 +122,9 @@ function cgen_c_struct()
end
if(ram.byte_select) then
emit("volatile uint8_t "..string.upper(ram.prefix).." ["..(ram.size * (DATA_BUS_WIDTH/8) * math.pow(2, ram.wrap_bits)) .."];");
emit("uint8_t "..string.upper(ram.prefix).." ["..(ram.size * (DATA_BUS_WIDTH/8) * math.pow(2, ram.wrap_bits)) .."];");
else
emit("volatile uint32_t "..string.upper(ram.prefix).." ["..(ram.size * math.pow(2, ram.wrap_bits)) .."];");
emit("uint32_t "..string.upper(ram.prefix).." ["..(ram.size * math.pow(2, ram.wrap_bits)) .."];");
end
end
end);
......@@ -162,8 +159,10 @@ function cgen_generate_c_header_code()
emit("#ifndef __WBGEN2_MACROS_DEFINED__");
emit("#define __WBGEN2_MACROS_DEFINED__");
emit("#define WBGEN2_GENMASK(offset, size) (((1<<(size))-1) << (offset))");
emit("#define WBGEN2_GENWRITE(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))");
emit("#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))");
emit("#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))");
emit("#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))");
emit("#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))");
emit("#endif");
......
trunk/software/wbgen2/cgen_common.lua
View file @ 17d7965e
......@@ -319,3 +319,25 @@ end
function cgen_generate_done()
output_code_file.close(output_code_file);
end
function cgen_gen_vlog_constants(filename)
local file = io.open(filename, "w");
if(file == nil) then
die("can't open "..filename.." for writing.");
end
foreach_reg(function(reg)
if(reg.__type == TYPE_REG) then
file.write(file, string.format("`define %-30s %d'h%x\n", "ADDR_"..string.upper(periph.hdl_prefix.."_"..reg.hdl_prefix), address_bus_width, reg.base));
end
if(reg.__type == TYPE_RAM) then
local base = math.pow(2, reg.select_bits) *
math.pow (2, address_bus_width - address_bus_select_bits);
file.write(file, string.format("`define %-30s %d'h%x\n", "BASE_"..string.upper(periph.hdl_prefix.."_"..reg.hdl_prefix), address_bus_width, base));
end
end
);
io.close(file);
end
trunk/software/wbgen2/examples/RAMs/gpio_port.mpf 0 → 100644
View file @ 17d7965e
This diff is collapsed.
trunk/software/wbgen2/examples/RAMs/gpio_port.vhdl 0 → 100644
View file @ 17d7965e
-------------------------------------------------------------------------------
-- Title : A sample GPIO port (wbgen2 example)
-- Project :
-------------------------------------------------------------------------------
-- File : gpio_port.vhdl
-- Author : T.W.
-- Company :
-- Created : 2010-02-22
-- Last update: 2010-03-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2010 T.W.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-02-22 1.0 slayer Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
entity gpio_port is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- our port :)
gpio_pins_b : inout std_logic_vector(31 downto 0)
);
end gpio_port;
architecture syn of gpio_port is
component wb_slave_gpio_port
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
gpio_ddr_o : out std_logic_vector(31 downto 0);
gpio_psr_i : in std_logic_vector(31 downto 0);
gpio_pdr_o : out std_logic_vector(31 downto 0);
gpio_pdr_wr_o : out std_logic;
gpio_sopr_o : out std_logic_vector(31 downto 0);
gpio_sopr_wr_o : out std_logic;
gpio_copr_o : out std_logic_vector(31 downto 0);
gpio_copr_wr_o : out std_logic);
end component;
signal gpio_ddr : std_logic_vector(31 downto 0);
signal gpio_psr : std_logic_vector(31 downto 0);
signal gpio_pdr : std_logic_vector(31 downto 0);
signal gpio_pdr_wr : std_logic;
signal gpio_sopr : std_logic_vector(31 downto 0);
signal gpio_sopr_wr : std_logic;
signal gpio_copr : std_logic_vector(31 downto 0);
signal gpio_copr_wr : std_logic;
-- regsiter containing current output state
signal gpio_reg : std_logic_vector(31 downto 0);
-- registers for synchronization of input pins
signal gpio_pins_sync1 : std_logic_vector(31 downto 0);
signal gpio_pins_sync0 : std_logic_vector(31 downto 0);
begin -- syn
wb_slave : wb_slave_gpio_port
port map (
rst_n_i => rst_n_i,
wb_clk_i => wb_clk_i,
wb_addr_i => wb_addr_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
gpio_ddr_o => gpio_ddr,
gpio_psr_i => gpio_pins_sync1,
gpio_pdr_o => gpio_pdr,
gpio_pdr_wr_o => gpio_pdr_wr,
gpio_sopr_o => gpio_sopr,
gpio_sopr_wr_o => gpio_sopr_wr,
gpio_copr_o => gpio_copr,
gpio_copr_wr_o => gpio_copr_wr);
process (wb_clk_i, rst_n_i)
begin -- process
if(rst_n_i = '0') then
gpio_reg <= (others => '0');
elsif rising_edge(wb_clk_i) then
if(gpio_pdr_wr = '1') then -- write operation to "PDR" register -
-- set the new values of GPIO outputs
gpio_reg <= gpio_pdr;
end if;
if(gpio_sopr_wr = '1') then -- write to "SOPR" reg - set ones
for i in 0 to 31 loop
if(gpio_sopr(i) = '1') then
gpio_reg(i) <= '1';
end if;
end loop;
end if;
if(gpio_copr_wr = '1') then -- write to "COPR" reg - set zeros
for i in 0 to 31 loop
if(gpio_copr(i) = '1') then
gpio_reg(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
-- synchronizing process for input pins
synchronize_input_pins : process (wb_clk_i, rst_n_i)
begin -- process
if(rst_n_i = '0') then
gpio_pins_sync0 <= (others => '0');
gpio_pins_sync1 <= (others => '0');
elsif rising_edge(wb_clk_i) then
gpio_pins_sync0 <= gpio_pins_b;
gpio_pins_sync1 <= gpio_pins_sync0;
end if;
end process;
-- generate the tristate buffers for I/O pins
gen_tristates : for i in 0 to 31 generate
gpio_pins_b(i) <= gpio_reg(i) when gpio_ddr(i) = '1' else 'Z';
end generate gen_tristates;
end syn;
trunk/software/wbgen2/examples/RAMs/gpio_port.wb 0 → 100644
View file @ 17d7965e
-- here comes our peripheral definition
peripheral {
-- short (human-readable) name for the peripheral.
name = "GPIO Port";
-- a longer description, if you want
description = "A sample 32-bit general-purpose bidirectional I/O port, explaining how to use SLV and PASS-THROUGH registers.";
-- name of the target VHDL entity to be generated
hdl_entity = "wb_slave_gpio_port";
-- prefix for all the generated ports belonging to our peripheral
prefix = "gpio";
-- Pin direction register. Readable and writable from the bus, readable from the device.
reg {
name = "Pin direction register";
description = "A register defining the direction of the GPIO potr pins.";
prefix = "ddr";
-- a single, anonymous field (no prefix) of type SLV.
field {
name = "Pin directions";
description = "Each bit in this register defines the direction of corresponding pin of the GPIO port. 1 means the pin is an OUTPUT, 0 means the pin is an INPUT";
-- there is (deliberately) no prefix defined for this field. Since we have only one field in the register "ddr", we can omit the prefix - wbgen2 will produce signal names
-- containing only prefixes of the peripheral and the parent register.
-- type of our field - std_logic_vector
type = SLV;
-- size - we want 32-bits wide port :)
size = 32;
-- the field will be readable/writable from the Wishbone bus
access_bus = READ_WRITE;
-- .. and readable from the peripheral
access_dev = READ_ONLY;
};
};
-- Pin input state register. Readable the bus, writable from the device.
reg {
name = "Pin input state register";
description = "A register containing the current state of input pins.";
prefix = "psr";
-- a single, anonymous field (no prefix) of type SLV.
field {
name = "Pin input state";
description = "Each bit in this register reflects the state of corresponding GPIO port pin.";
-- no prefix here as well (see above)
-- type of our field - std_logic_vector
type = SLV;
-- size - we want 32-bits wide port :)
size = 32;
-- the field will be readable from the Wishbone bus
access_bus = READ_ONLY;
-- .. and writable from the peripheral
access_dev = WRITE_ONLY;
};
};
-- Port output register. Shows how to use PASS-THROUGH regs
reg {
name = "Port output register";
description = "Register containing the output pin state.";
prefix = "pdr";
-- a single, anonymous field (no prefix) of type PASS-THROUGH.
field {
name = "Port output value";
-- the description isn't really necessary here :)
-- description = "Writing '1' sets the corresponding GPIO pin to '1'";
-- type of our field - PASS_THROUGH. In this mode, the slave core is not storing the register value. Instead it provides the raw value
-- (taken from the wishbone data input) and a strobe signal, asserted for single clock cycle upon write operation to the register.
-- The wishbone data input will be fed directly to gpio_pdr_o and each write operation to this register will generate a single-cycle positive
-- pulse on gpio_pdr_wr_o signal.
type = PASS_THROUGH;
size = 32;
-- access flags don't apply for the PASS-THROUGH regsiters, so we can omit them.
};
};
-- Set output register. Shows how to use PASS-THROUGH regs
reg {
name = "Set output pin register";
description = "Writing '1' sets the corresponding GPIO pin to '1'";
prefix = "sopr";
-- Our driver developer would want these two (SOPR and COPR) registers' addresses to be aligned to multiple of 4 :)
align = 4;
field {
name = "Set output pin register";
type = PASS_THROUGH;
size = 32;
};
};
-- Clear output register. Designed identically as the previous reg.
reg {
name = "Clear output pin register";
description = "Writing '1' clears the corresponding GPIO pin";
prefix = "copr";
field {
name = "Clear output pin register";
type = PASS_THROUGH;
size = 32;
};
};
};
trunk/software/wbgen2/examples/RAMs/rams.wb 0 → 100644
View file @ 17d7965e
-- here comes our peripheral definition
peripheral {
-- short (human-readable) name for the peripheral.
name = "Test RAM memories";
-- a longer description, if you want
description = "A slave containing various types of RAM memories";
-- name of the target VHDL entity to be generated
hdl_entity = "wb_slave_test_rams";
-- prefix for all the generated ports belonging to our peripheral
prefix = "RAMS";
-- RAM 1: 256 32-bit words, using asynchronous clock, writable from both the bus and the core, with 1 address wrap bit (mirrored 2 times)
ram {
name = "Memory 1";
prefix = "mem1k";
-- number of words of size 'width' in the RAM
size = 256;
-- width (bit count) of the memory's data bus
width = 32;
-- yes, we want the memory to be byte-addressable
byte_select = true;
-- core ports work in different clock domain
clock = "clk1_i";
-- here we define address wraparound. The memory address space is extended by 'wrap_bits' number of bits, thus mirroring the memory 2^(wrap_bits) times.
-- This allows for wrap-around read/write operations passing from the end to the beginning of the memory with no extra math. Useful for implementing circular buffers, etc.
wrap_bits = 1;
-- access. Defined the same way as for the registers.
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
-- simple, 2-kilobyte (1024 x 16 bits) memory with no extra features.
ram {
name = "Memory 2";
prefix = "mem2K";
size = 1024;
width = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
trunk/software/wbgen2/examples/RAMs/run.do 0 → 100644
View file @ 17d7965e
vlib work
vlib wbgen2
../../wbgen2.lua rams.wb -vo ./output/wb_slave_test_rams.vhdl -consto ./output/vlog_constants.v
vcom -work wbgen2 ../../lib/wbgen2_pkg.vhd
vcom -work wbgen2 ../../lib/wbgen2_dpssram.vhd
vcom -work work ./output/wb_slave_test_rams.vhdl
vlog ./testbench.v
vsim work.main
radix -hexadecimal
do wave.do
run 15us
wave zoomfull
trunk/software/wbgen2/examples/RAMs/run.do.bak 0 → 100644
View file @ 17d7965e
vlib work
vlib wbgen2
../../wbgen2.lua rams.wb -vo ./output/wb_slave_test_rams.vhdl -consto ./output/vlog_constants.v
vcom -work work ./output/wb_slave_test_rams.vhdl
vcom -work wbgen2 ../../lib/wbgen2_pkg.vhd
vcom -work wbgen2 ../../lib/wbgen2_dpssram.vhd
vlog ./testbench.v
vsim work.main
radix -hexadecimal
do wave.do
run 15us
wave zoomfull
trunk/software/wbgen2/examples/RAMs/testbench.v 0 → 100644
View file @ 17d7965e
`timescale 1ns/1ps
`define wbclk_period 100
`include "output/vlog_constants.v"
module main;
reg clk=1;
reg rst=0;
wire [3:0] ones = 'b1111;
always #(`wbclk_period/2) clk <= ~clk;
initial #1000 rst <= 1;
`include "wishbone_stuff.v"
wire [31:0] gpio_pins_b;
reg [31:0] gpio_reg = 32'bz;
gpio_port dut(
.rst_n_i (rst),
.wb_clk_i (clk),
.wb_addr_i (wb_addr[2:0]),
.wb_data_i (wb_data_o),
.wb_data_o (wb_data_i),
.wb_cyc_i (wb_cyc),
.wb_stb_i (wb_stb),
.wb_we_i (wb_we),
.wb_ack_o (wb_ack),
.wb_sel_i(ones),
.gpio_pins_b (gpio_pins_b)
);
assign gpio_pins_b = gpio_reg;
reg[31:0] data;
integer i;
initial begin
#2001; // wait until the DUT is reset
$display("Set half of the pins to outputs, other half to inputs");
wb_write(`ADDR_GPIO_DDR, 32'hffff0000);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
$display("Set every even byte to '1'");
wb_write(`ADDR_GPIO_SOPR, 32'hff00ff00);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
$display("Clear every even bit");
wb_write(`ADDR_GPIO_COPR, 32'h55555555);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
$display("Write an arbitrary value");
wb_write(`ADDR_GPIO_PDR, 32'hdeadbeef);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
$display("Force something tasty on the GPIO input pins");
gpio_reg[15:0] = 16'hcafe;
delay_cycles(1);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
delay_cycles(10); // wait for a while for the sync logic
wb_read(`ADDR_GPIO_PSR, data);
$display("Time for %x!", data[15:0]);
end
endmodule
trunk/software/wbgen2/examples/RAMs/wave.do 0 → 100644
View file @ 17d7965e
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /main/dut/rst_n_i
add wave -noupdate -format Logic /main/dut/wb_clk_i
add wave -noupdate -format Literal /main/dut/wb_addr_i
add wave -noupdate -format Literal /main/dut/wb_data_i
add wave -noupdate -format Literal /main/dut/wb_data_o
add wave -noupdate -format Logic /main/dut/wb_cyc_i
add wave -noupdate -format Logic /main/dut/wb_sel_i
add wave -noupdate -format Logic /main/dut/wb_stb_i
add wave -noupdate -format Logic /main/dut/wb_we_i
add wave -noupdate -format Logic /main/dut/wb_ack_o
add wave -noupdate -format Literal /main/dut/gpio_pins_b
add wave -noupdate -format Literal /main/dut/gpio_ddr
add wave -noupdate -format Literal /main/dut/gpio_psr
add wave -noupdate -format Literal /main/dut/gpio_pdr
add wave -noupdate -format Logic /main/dut/gpio_pdr_wr
add wave -noupdate -format Literal /main/dut/gpio_sopr
add wave -noupdate -format Logic /main/dut/gpio_sopr_wr
add wave -noupdate -format Literal /main/dut/gpio_copr
add wave -noupdate -format Logic /main/dut/gpio_copr_wr
add wave -noupdate -format Literal /main/dut/gpio_reg
add wave -noupdate -format Literal /main/dut/gpio_pins_sync1
add wave -noupdate -format Literal /main/dut/gpio_pins_sync0
add wave -noupdate -format Logic /main/dut/wb_slave/rst_n_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_clk_i
add wave -noupdate -format Literal /main/dut/wb_slave/wb_addr_i
add wave -noupdate -format Literal /main/dut/wb_slave/wb_data_i
add wave -noupdate -format Literal /main/dut/wb_slave/wb_data_o
add wave -noupdate -format Logic /main/dut/wb_slave/wb_cyc_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_sel_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_stb_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_we_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_ack_o
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_async_clk_i
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_ddr_o
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_psr_i
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_pdr_o
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_o
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_sopr_o
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_o
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_copr_o
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_o
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_ddr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb_s0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb_s1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb_s2
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_psr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_in_progress
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_s0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_s1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_s2
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_int_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_sync0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_sync1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_sync2
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_int_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_sync0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_sync1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_sync2
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_int_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_sync0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_sync1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_sync2
add wave -noupdate -format Logic /main/dut/wb_slave/wb_ack_regbank
add wave -noupdate -format Literal /main/dut/wb_slave/ack_cntr
add wave -noupdate -format Logic /main/dut/wb_slave/ack_in_progress
add wave -noupdate -format Logic /main/dut/wb_slave/tmpbit
add wave -noupdate -format Literal /main/dut/wb_slave/wb_data_out_int
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 333
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {15750 ns}
trunk/software/wbgen2/examples/RAMs/wbgen2/_info 0 → 100644
View file @ 17d7965e
m255
13
cModel Technology
d/home/slayer/wbgen2_svn/wbgen2/examples/RAMs
Pwbgen2_pkg
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1268865151
F../../lib/wbgen2_pkg.vhd
l0
L6
VFVWLjXUGZQ=jP2HMgk91;3
OE;C;6.2b;35
32
M1 ieee std_logic_1164
o-work wbgen2
tExplicit 1
trunk/software/wbgen2/examples/RAMs/wishbone_stuff.v 0 → 100644
View file @ 17d7965e
reg [31:0] wb_addr, wb_data_o, tmp;
wire [31:0] wb_data_i;
wire wb_ack;
reg wb_sel =0, wb_cyc=0, wb_stb=0, wb_we= 0;
task delay_cycles;
input [31:0] n;
begin
#(n * `wbclk_period);
end
endtask // delay_cycles
task wb_write;
input[31:0] addr;
input [31:0] data;
begin
$display("WB write: addr %x, data %x", addr, data);
wb_sel=1;
wb_stb=1;
wb_cyc=1;
wb_addr = addr;
wb_data_o=data;
wb_we = 1;
delay_cycles(1);
while(wb_ack == 0)
delay_cycles(1);
delay_cycles(1);
wb_cyc = 0;
wb_sel=0;
wb_we=0;
wb_stb=0;
end
endtask // wb_write
task wb_read;
input[31:0] addr;
output [31:0] data;
begin
wb_sel=1;
wb_stb=1;
wb_cyc=1;
wb_addr = addr;
wb_data_o=data;
wb_we = 0;
delay_cycles(1);
while(wb_ack == 0)
delay_cycles(1);
data = wb_data_i;
delay_cycles(1);
wb_cyc = 0;
wb_sel=0;
wb_we=0;
wb_stb=0;
end
endtask // wb_read
trunk/software/wbgen2/examples/RAMs/work/_info 0 → 100644
View file @ 17d7965e
m255
13
cModel Technology
d/home/slayer/wbgen2_svn/wbgen2/examples/RAMs
T_opt
Vf9b?XRk;HFN=5Q[hJ?3@B1
04 4 4 work main fast 0
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
Egpio_port
w1268865151
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
F./gpio_port.vhdl
l0
L27
V=48Cd@cI0EFDRnHinnSkI2
OE;C;6.2b;35
32
tExplicit 1
Asyn
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work gpio_port =48Cd@cI0EFDRnHinnSkI2
l86
L46
VE9ChVMG=a34IjH39JN^@>2
OE;C;6.2b;35
32
M1 ieee std_logic_1164
tExplicit 1
vmain
IOT`WFa]ZX5_Ob[Mb8Clm33
VEAT@0_d?1jQUQ5cgEJon`1
w1268865151
F./testbench.v
Foutput/vlog_constants.v
Fwishbone_stuff.v
L0 7
VEAT@0_d?1jQUQ5cgEJon`1
OE;L;6.2b;35
r1
31
Ewb_slave_gpio_port
w1268867801
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
F./output/wb_slave_gpio_port.vhdl
l0
L17
VjCZBzXQYDT`TMj1DM8gO;0
OE;C;6.2b;35
32
tExplicit 1
Asyn
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work wb_slave_gpio_port jCZBzXQYDT`TMj1DM8gO;0
l60
L45
VN=Coe86jG20]Cd<;BBnLC1
OE;C;6.2b;35
32
M2 ieee std_logic_1164
M1 ieee numeric_std
tExplicit 1
trunk/software/wbgen2/examples/RAMs/work/_opt/__model_tech_.._ieee__info 0 → 100644
View file @ 17d7965e
m255
cModel Technology Builtin Library
13
dD:\qa\patch6_2\nightly\master\modeltech
Pmath_complex
DP work math_real zjAF7SKfg_RPI0GT^n1N`1
OL;C;6.2b;35
31
b1
M1 work math_real
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/ieee/1076-2code.vhd
l0
L687
V1a;R8Z_kc3Q7^>9;gKVIV0
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/1076-2code.vhd
tExplicit 1
Bbody
DB work math_complex 1a;R8Z_kc3Q7^>9;gKVIV0
DP work math_real zjAF7SKfg_RPI0GT^n1N`1
OL;C;6.2b;35
31
M1 work math_real
OP;C;6.2b;35
l0
L687
VIMmI^hXJEW@Uoa4kJFX:K1
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/1076-2code.vhd
tExplicit 1
nbody
Pmath_real
OL;C;6.2b;35
31
b1
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/ieee/1076-2code.vhd
l0
L55
VzjAF7SKfg_RPI0GT^n1N`1
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/1076-2code.vhd
tExplicit 1
Bbody
DB work math_real zjAF7SKfg_RPI0GT^n1N`1
OL;C;6.2b;35
31
OP;C;6.2b;35
l0
L55
V:TOmE?QHig?1Xi[gFIA[l1
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/1076-2code.vhd
tExplicit 1
nbody
Pnumeric_bit
OL;C;6.2b;35
31
b1
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/ieee/mti_numeric_bit.vhd
l0
L58
VK1ChclJ;R]bj:<QN8`za13
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/mti_numeric_bit.vhd -nowarn 3
tExplicit 1
Bbody
DB work numeric_bit K1ChclJ;R]bj:<QN8`za13
OL;C;6.2b;35
31
OP;C;6.2b;35
l0
L58
VMl`J4ca2be3ejNXY`>k4Y1
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/mti_numeric_bit.vhd -nowarn 3
tExplicit 1
nbody
Pnumeric_std
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
b1
M1 ieee std_logic_1164
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/ieee/mti_numeric_std.vhd
l0
L57
V=NSdli^?T5OD8;4F<blj<3
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/mti_numeric_std.vhd -nowarn 3
tExplicit 1
Bbody
DB work numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
M1 ieee std_logic_1164
OP;C;6.2b;35
l0
L57
V;m@IM<mVXokEM:EdoJkM40
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/mti_numeric_std.vhd -nowarn 3
tExplicit 1
nbody
Pstd_logic_1164
OL;C;6.2b;35
31
b1
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/ieee/stdlogic.vhd
l0
L36
VGH1=`jDDBJ=`LM;:Ak`kf2
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/stdlogic.vhd
tExplicit 1
Bbody
DB work std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
OP;C;6.2b;35
l0
L36
V?YNEkS<^lY?<6LBZLFa8D0
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/ieee/stdlogic.vhd
tExplicit 1
nbody
Pstd_logic_arith
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
b1
M1 ieee std_logic_1164
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_arith.vhd
l0
L25
VGJbAT?7@hRQU9IQ702DT]2
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_arith.vhd
tExplicit 1
Bbody
DB work std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
M1 ieee std_logic_1164
OP;C;6.2b;35
l0
L25
VWh`K2GRna_=ITGj@XNmX80
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_arith.vhd
tExplicit 1
nbody
Pstd_logic_misc
DP synopsys attributes oP@SNI848YZ9iazan5Mg_2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
b1
M2 ieee std_logic_1164
M1 synopsys attributes
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_misc.vhd
l0
L24
VD2f;@P3IKJA9T^H8HI[9K0
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_misc.vhd
tExplicit 1
Bbody
DB work std_logic_misc D2f;@P3IKJA9T^H8HI[9K0
DP synopsys attributes oP@SNI848YZ9iazan5Mg_2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
M2 ieee std_logic_1164
M1 synopsys attributes
OP;C;6.2b;35
l0
L24
V>2Z50F2Um7SR`gOQH`oSK0
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_misc.vhd
tExplicit 1
nbody
Pstd_logic_signed
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
b1
M2 ieee std_logic_1164
M1 ieee std_logic_arith
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_signed.vhd
l0
L35
V<9<Kcl:S52:oW`F]FQhb20
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_signed.vhd
tExplicit 1
Bbody
DB work std_logic_signed <9<Kcl:S52:oW`F]FQhb20
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
M2 ieee std_logic_1164
M1 ieee std_logic_arith
OP;C;6.2b;35
l0
L35
VDR>6>65S7FR:e[I>ADUQO1
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_signed.vhd
tExplicit 1
nbody
Pstd_logic_textio
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
OL;C;6.2b;35
31
b1
M2 std textio
M1 ieee std_logic_1164
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/synopsys/std_logic_textio.vhd
l0
L22
V8YS?iX`WD1REQG`ZRYQGB2
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/std_logic_textio.vhd
tExplicit 1
Bbody
DB work std_logic_textio 8YS?iX`WD1REQG`ZRYQGB2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DP std textio K]Z^fghZ6B=BjnK5NomDT3
OL;C;6.2b;35
31
M2 std textio
M1 ieee std_logic_1164
OP;C;6.2b;35
l0
L22
Vj9DSczGXI>dbiF;m2[GMa2
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/std_logic_textio.vhd
tExplicit 1
nbody
Pstd_logic_unsigned
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
b1
M2 ieee std_logic_1164
M1 ieee std_logic_arith
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_unsigned.vhd
l0
L34
VhEMVMlaNCR^<OOoVNV;m90
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_unsigned.vhd
tExplicit 1
Bbody
DB work std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
31
M2 ieee std_logic_1164
M1 ieee std_logic_arith
OP;C;6.2b;35
l0
L34
V1=Y]oOSl8JChnzj5R39ha2
OE;C;6.2b;35
o-93 -work ieee -path $MODEL_TECH/../vhdl_src/synopsys/mti_std_logic_unsigned.vhd
tExplicit 1
nbody
Pvital_primitives
DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
30
b1
M2 ieee std_logic_1164
M1 ieee vital_timing
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/vital95/prmtvs_p.vhd
l0
L47
VE9g6AWKAc2T]enMfl94If3
OE;C;6.2b;35
o-87 -novital -novital -work ieee -path $MODEL_TECH/../vhdl_src/vital95/prmtvs_p.vhd
tExplicit 1
Bbody
DB work vital_primitives E9g6AWKAc2T]enMfl94If3
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
30
M3 ieee std_logic_1164
M2 ieee vital_timing
M1 std textio
OP;C;6.2b;35
F$MODEL_TECH/../vhdl_src/vital95/prmtvs_b.vhd
l0
L47
V>[EMmIIzoCHn?@614I_=a3
OE;C;6.2b;35
o-87 -novital -novital -work ieee -path $MODEL_TECH/../vhdl_src/vital95/prmtvs_b.vhd
tExplicit 1
nbody
Pvital_timing
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
30
b1
M1 ieee std_logic_1164
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/vital95/timing_p.vhd
l0
L46
VOBWK>;kUYmkG<OChK2lhV1
OE;C;6.2b;35
o-87 -novital -novital -work ieee -path $MODEL_TECH/../vhdl_src/vital95/timing_p.vhd
tExplicit 1
Bbody
DB work vital_timing OBWK>;kUYmkG<OChK2lhV1
DP std textio K]Z^fghZ6B=BjnK5NomDT3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
OL;C;6.2b;35
30
M2 ieee std_logic_1164
M1 std textio
OP;C;6.2b;35
F$MODEL_TECH/../vhdl_src/vital95/timing_b.vhd
l0
L46
VfN[Pf:HE;^Z^LCeH6gGI81
OE;C;6.2b;35
o-87 -novital -novital -work ieee -path $MODEL_TECH/../vhdl_src/vital95/timing_b.vhd
tExplicit 1
nbody
trunk/software/wbgen2/examples/RAMs/work/_opt/__model_tech_.._std__info 0 → 100644
View file @ 17d7965e
m255
cModel Technology Builtin Library
13
dD:\qa\patch6_2\nightly\master\modeltech
Pstandard
OL;C;6.2b;35
31
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/std/standard.vhd
l0
L8
V9SL6g`:IK^4S07MiOU]DY2
OE;C;6.2b;35
o-s -93 -work std -path $MODEL_TECH/../vhdl_src/std/standard.vhd
tExplicit 1
Ptextio
OL;C;6.2b;35
31
b1
OP;C;6.2b;35
d.
F$MODEL_TECH/../vhdl_src/std/textio.vhd
l0
L11
VK]Z^fghZ6B=BjnK5NomDT3
OE;C;6.2b;35
o-93 -work std -path $MODEL_TECH/../vhdl_src/std/textio.vhd
tExplicit 1
Bbody
DB work textio K]Z^fghZ6B=BjnK5NomDT3
OL;C;6.2b;35
31
OP;C;6.2b;35
l0
L11
V<aSA_n5_Z?BQ97PO]oKmn2
OE;C;6.2b;35
o-93 -work std -path $MODEL_TECH/../vhdl_src/std/textio.vhd
tExplicit 1
nbody
trunk/software/wbgen2/examples/RAMs/work/_opt/_deps 0 → 100644
View file @ 17d7965e
H 2141964 10 3 0 3 2 0 0 0 0
L 4 ieee 19 $MODEL_TECH/../ieee
L 3 std 18 $MODEL_TECH/../std
L 4 work 4 work
D 19 work.gpio_port(syn) E9ChVMG=a34IjH39JN^@>2 1 1
D 9 work.main OT`WFa]ZX5_Ob[Mb8Clm33 2 0
D 28 work.wb_slave_gpio_port(syn) N=Coe86jG20]Cd<;BBnLC1 0 1
2 0 0 4R35zeN1:dQH=0e^;9PT:2 0 0 1
2 4 fast 0 H7QnTAo`W3H:Ti041l:DH1 1 2 1
trunk/software/wbgen2/examples/RAMs/work/_opt/work__info 0 → 100644
View file @ 17d7965e
m255
13
cModel Technology
d/home/slayer/wbgen2_svn/wbgen2/examples/RAMs
T_opt
Vf9b?XRk;HFN=5Q[hJ?3@B1
04 4 4 work main fast 0
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
Egpio_port
w1268865151
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
F./gpio_port.vhdl
l0
L27
V=48Cd@cI0EFDRnHinnSkI2
OE;C;6.2b;35
tExplicit 1
Asyn
DE work wb_slave_gpio_port jCZBzXQYDT`TMj1DM8gO;0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work gpio_port =48Cd@cI0EFDRnHinnSkI2
32
M1 ieee std_logic_1164
l86
L46
VE9ChVMG=a34IjH39JN^@>2
OE;C;6.2b;35
tExplicit 1
vmain
IOT`WFa]ZX5_Ob[Mb8Clm33
VEAT@0_d?1jQUQ5cgEJon`1
w1268865151
F./testbench.v
Foutput/vlog_constants.v
Fwishbone_stuff.v
L0 7
VEAT@0_d?1jQUQ5cgEJon`1
OE;L;6.2b;35
r1
31
Ewb_slave_gpio_port
w1268867795
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
F./output/wb_slave_gpio_port.vhdl
l0
L17
VjCZBzXQYDT`TMj1DM8gO;0
OE;C;6.2b;35
tExplicit 1
Asyn
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work wb_slave_gpio_port jCZBzXQYDT`TMj1DM8gO;0
32
M2 ieee std_logic_1164
M1 ieee numeric_std
l60
L45
VN=Coe86jG20]Cd<;BBnLC1
OE;C;6.2b;35
tExplicit 1
trunk/software/wbgen2/examples/RAMs/work/main/_primary.vhd 0 → 100644
View file @ 17d7965e
library verilog;
use verilog.vl_types.all;
entity main is
end main;
trunk/software/wbgen2/examples/gpio_port/gpio_port.mpf
View file @ 17d7965e
......@@ -802,6 +802,6 @@ XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
EditorState = {tabbed horizontal 1}
EditorState = {tabbed horizontal 1} {/home/slayer/TWVGA/core_verilog/run.do 0 0} {/home/slayer/TWVGA/core_verilog/testbench-uart.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 2
trunk/software/wbgen2/examples/gpio_port/run.do
View file @ 17d7965e
vlib work
../../wbgen2.lua gpio_port.wb -vo ./output/wb_slave_gpio_port.vhdl --gen-vlog-constants ./output/vlog_constants.v
../../wbgen2.lua gpio_port.wb -vo ./output/wb_slave_gpio_port.vhdl -consto ./output/vlog_constants.v
vcom ./output/wb_slave_gpio_port.vhdl
vcom ./gpio_port.vhdl
......
trunk/software/wbgen2/examples/gpio_port_async/run.do
View file @ 17d7965e
vlib work
../../wbgen2.lua gpio_port_async.wb -vo ./output/wb_slave_gpio_port_async.vhdl --gen-vlog-constants ./output/vlog_constants.v
../../wbgen2.lua gpio_port_async.wb -vo ./output/wb_slave_gpio_port_async.vhdl -consto ./output/vlog_constants.v
vcom ./output/wb_slave_gpio_port_async.vhdl
vcom ./gpio_port_async.vhdl
......
trunk/software/wbgen2/regs_with_fields.wb
View file @ 17d7965e
......@@ -99,7 +99,7 @@ peripheral {
field {
name = "UnSigned with range";
prefix = "unsignedrange";
prefix = "unsrange";
type = UNSIGNED;
range = {-200, 250};
access_bus = READ_WRITE;
......
trunk/software/wbgen2/wbgen2.lua
View file @ 17d7965e
......@@ -35,12 +35,14 @@ function parse_args(arg)
print("wbgen2 version "..wbgen2_version);
print("(c) Tomasz Wlostowski/CERN BE-Co-HT 2010");
print("");
print("usage: "..arg[0].." input_file.wb -t target -vo output.vhdl -co output.c -do output.html [additional options]");
print("where target is the target FPGA architecture [altera/xilinx]");
print("usage: "..arg[0].." input_file.wb [options]");
print("");
print("Additional options: ");
print("--gen-reg-constants - generates VHDL constants containing addresses of all registers. Useful for writing testbenches.");
print("--gen-vlog-constants file.v - generates Verilog constants containing addresses of all registers and writes them to file.v. Useful for writing testbenches.");
print("Options: ");
print("-target [classic / pipelined] - chooses between classic Wishbone bus and HT pipelined Wishbone.");
print("-lang [vhdl / verilog] - chooses the HDL language to be generated");
print("-vo [file.vhdl / file.v] - generates VHDL/Verilog code for the slave Wishbone core.");
print("-co [file.h] - generates C header file containing register definitions and access macros");
print("-consto [constants.v] - generates Verilog file containing addresses of all registers/rams and writes them to specified file. Useful for writing testbenches.");
print("");
os.exit(0);
end
......@@ -60,12 +62,8 @@ function parse_args(arg)
elseif(sw == "-co") then
options.output_c_header_file = chk_nil(arg[n+1], "C header output filename expected");
n=n+2;
elseif(sw == "--gen-reg-constants") then
vhdl_gen_reg_constants = true;
n=n+1;
elseif(sw == "--gen-vlog-constants") then
output_vlog_constants_file = chk_nil(arg[n+1],"Verilog constants filename expected");
vlog_gen_reg_constants = true;
elseif(sw == "-consto") then
options.output_vlog_constants_file = chk_nil(arg[n+1],"Verilog constants filename expected");
n=n+2;
else
n=n+1;
......@@ -121,3 +119,8 @@ if(options.output_c_header_file ~= nil) then
cgen_generate_done();
end
if(options.output_vlog_constants_file ~= nil) then
cgen_gen_vlog_constants(options.output_vlog_constants_file);
end
trunk/software/wbgen2/wbgen_sic.lua 0 → 100644
View file @ 17d7965e
-- -*- Mode: LUA; tab-width: 2 -*-
-- wbgen2 - a simple Wishbone slave generator
-- (c) 2010 Tomasz Wlostowski
-- CERN BE-Co-HT
-- LICENSED UNDER GPL v2
-- EIC (tm) = Embedded Interrupt Controller
-- regs:
--
-- EIC_IER = interrupt enable reg [passthru]
-- EIC_IDR = interrupt disable reg [passthru]
-- EIC_IMR = interrupt mask reg [rw, load-ext]
-- EIC_ISR = interrupt status reg [rw, reset on write 1]
--
function wbgen_gen_irq_controller()
-- trigger = IRQ_POSEDGE, NEGEDGE, HIGH, LOW
-- name
-- prefix
end
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment