@@ -792,7 +792,7 @@ Do not use default values (or initialization) for signals and variables, such an
All signals or variables of type integer should be declared constrained, because standard is a 32-bit bus. If you don't want to use the full range in your design this would result in unnecessary use of resources on your hardware. Therefore, you should declare your integer signals, ports and variables always like that:
\texttt{signal integer\_signal : integer range 0 to 16;}
\texttt{signal integer\_signal : integer range 0 to 15;}
\subsection{(*) Entity Port Types}
...
...
@@ -948,7 +948,7 @@ VHDL for RTL should be as generic as possible. Stick to standard templates for c
\label{fig:CombBlck}
\end{figure}
Critical paths should be entirely included in a single design entity. As a general rule, a design should exist in a designer's mind before describing it in VHDL (the 'D' stands for Description). See for example \cite{Rus00} as a book which emphasises this approach.
As a general rule, a design should exist in a designer's mind before describing it in VHDL (the 'D' stands for Description). See for example \cite{Rus00} as a book which emphasises this approach.
