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HDL Core Lib
Commit ed76e70f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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trunk/software/wbgen2/README
View file @ ed76e70f
This is the initial version of wbgen2. Requires Lua 5.1.4+. Enjoy it :)
There is still some stuff to do:
- add RAMs and FIFOs
- add C code generator
- add FIFOs
- add documentation generator
- CONSTANT registers
\ No newline at end of file
- CONSTANT registers
- add EIC
\ No newline at end of file
trunk/software/wbgen2/cgen_c_headers.lua
View file @ ed76e70f
......@@ -8,19 +8,33 @@
-- The C header code generator.
--
-- generates #defines for a register field:
-- NAME_MASK - bit mask of the field
-- NAME_SHIFT - bit offset of the field
-- NAME_W - write access macro packing given field value into the register:
-- regs_struct->reg = FIELD1_W(value1) | FIELD2_W(value2) | ....;
--
-- NAME_R - read access macro extracting the value of certain field from the register:
-- field1_value = FIELD1_R(regs_struct->reg);
--
function cgen_c_field_define(field, reg)
local prefix=string.upper(periph.c_prefix).."_"..string.upper(reg.c_prefix).."_"..string.upper(field.c_prefix);
emit("");
emit("/* definitions for field: "..field.name.." in reg: "..reg.name.." */");
-- for bit-type fields, emit only masks
if(field.type == BIT or field.type == MONOSTABLE) then
emit(string.format("%-45s %s", "#define "..prefix, "WBGEN2_GEN_MASK("..field.offset..", 1)"));
else
-- SLV/signed/unsigned fields: emit masks, shifts and access macros
print(field.offset, field.size);
-- emit("#define "..prefix.."_MASK "..string.format("0x%08x", (math.pow(2, field.size)-1) * math.pow(2, field.offset)));
emit(string.format("%-45s %s", "#define "..prefix.."_MASK", "WBGEN2_GEN_MASK("..field.offset..", "..field.size..")"));
emit(string.format("%-45s %d", "#define "..prefix.."_SHIFT", field.offset));
emit(string.format("%-45s %s", "#define "..prefix.."_W(value)", "WBGEN2_GEN_WRITE(value, "..field.offset..", "..field.size..")"));
-- if the field is signed, generate read operation with sign-extension
if(field.type == SIGNED) then
emit(string.format("%-45s %s", "#define "..prefix.."_R(reg)", "WBGEN2_SIGN_EXTEND(WBGEN2_GEN_READ(reg, "..field.offset..", "..field.size.."), "..field.size..")"));
else
......@@ -29,6 +43,8 @@ function cgen_c_field_define(field, reg)
end
end
-- generates some definitions for RAM memory block
function cgen_c_ramdefs(ram)
local prefix = string.upper(periph.c_prefix).."_"..string.upper(ram.c_prefix);
......@@ -38,6 +54,7 @@ function cgen_c_ramdefs(ram)
emit(string.format("#define "..prefix.."_WORDS 0x%08x %-50s", ram.size, "/* size in "..ram.width.."-bit words, 32-bit aligned */"));
end
-- iterates all regs and rams and generates appropriate #define-s
function cgen_c_field_masks()
foreach_reg(function(reg)
if(reg.__type == TYPE_REG and reg.num_fields ~= nil and reg.num_fields > 0) then
......@@ -50,38 +67,49 @@ function cgen_c_field_masks()
end);
end
function cgen_c_headers_reg(reg)
foreach_subfield(reg, function(field, reg)
emit()
end);
end
function cgen_c_headers_ram()
end
-- generates C file header
function cgen_c_fileheader()
emit ("/*");
emit (" Register definitions for slave core: "..periph.name);
emit ("");
emit (" * File : "..options.output_c_header_file);
emit (" * Author : auto-generated by wbgen2 from "..input_wb_file);
emit (" * Created : "..os.date());
emit (" * Standard : ANSI C");
emit ("");
emit (" THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE "..input_wb_file);
emit (" DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!");
emit ("");
emit ("*/");
emit ("/*");
emit (" Register definitions for slave core: "..periph.name);
emit ("");
emit (" * File : "..options.output_c_header_file);
emit (" * Author : auto-generated by wbgen2 from "..input_wb_file);
emit (" * Created : "..os.date());
emit (" * Standard : ANSI C");
emit ("");
emit (" THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE "..input_wb_file);
emit (" DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!");
emit ("");
emit ("*/");
emit("");
emit("#ifndef __WBGEN2_REGDEFS_"..string.upper(string.gsub(input_wb_file,"%.","_")))
emit("#define __WBGEN2_REGDEFS_"..string.upper(string.gsub(input_wb_file,"%.","_")))
emit("");
emit("#include <inttypes.h>");
emit("");
emit("#if defined( __GNUC__)");
emit("#define PACKED __attribute__ ((packed))");
emit("#else");
emit("#error \"Unsupported compiler?\"");
emit("#endif");
emit("");
emit("#ifndef __WBGEN2_MACROS_DEFINED__");
emit("#define __WBGEN2_MACROS_DEFINED__");
emit("#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))");
emit("#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))");
emit("#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))");
emit("#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))");
emit("#endif");
emit("");
end
-- generates C structure reflecting the memory map of the peripheral.
function cgen_c_struct()
local cur_offset = 0;
local pad_id = 0;
-- generates padding entry (if the offset of the register in memory is ahead of current offset in the structure)
function pad_struct(base)
if(cur_offset < base) then
emit("/* padding to: "..base.." words */");
......@@ -91,6 +119,8 @@ function cgen_c_struct()
end
end
-- emit the structure definition...
emit("");
emit("PACKED struct "..string.upper(periph.c_prefix).."_WB {");
indent_right();
......@@ -100,6 +130,8 @@ function cgen_c_struct()
if(reg.__type == TYPE_REG) then
pad_struct(reg.base);
emit(string.format("/* [0x%x]: REG "..reg.name.." */", reg.base * DATA_BUS_WIDTH / 8));
-- this is just simple :)
emit("uint32_t "..string.upper(reg.prefix)..";");
cur_offset = cur_offset + 1;
end
......@@ -108,10 +140,16 @@ function cgen_c_struct()
-- .. and for RAMs
foreach_reg(function(ram)
if(ram.__type == TYPE_RAM) then
local base = math.pow(2, ram.select_bits) *
-- calculate base address of the RAM
-- print("SelBits: ram "..ram.name.." sb "..ram.select_bits);
local base = ram.select_bits *
math.pow (2, address_bus_width - address_bus_select_bits);
pad_struct(base);
-- output some comments
emiti();
emitx(string.format("/* [0x%x - 0x%x]: RAM "..ram.name..", "..ram.size.." "..ram.width.."-bit words, "..DATA_BUS_WIDTH.."-bit aligned, "..csel(ram.byte_select, "byte", "word").."-addressable", base * DATA_BUS_WIDTH / 8, (base + math.pow(2, ram.wrap_bits)*ram.size) * (DATA_BUS_WIDTH / 8) - 1));
......@@ -121,6 +159,7 @@ function cgen_c_struct()
emitx(" */\n");
end
-- and the RAM, as an array
if(ram.byte_select) then
emit("uint8_t "..string.upper(ram.prefix).." ["..(ram.size * (DATA_BUS_WIDTH/8) * math.pow(2, ram.wrap_bits)) .."];");
else
......@@ -129,47 +168,20 @@ function cgen_c_struct()
end
end);
indent_left();
emit("};");
emit("");
end
function cgen_generate_c_header_code()
-- main C code generator function. Takes the peripheral definition and generates C code.
function cgen_generate_c_header_code()
cgen_new_snippet();
cgen_c_fileheader();
emit("");
emit("#ifndef __WBGEN2_REGDEFS_"..string.upper(string.gsub(input_wb_file,"%.","_")))
emit("#define __WBGEN2_REGDEFS_"..string.upper(string.gsub(input_wb_file,"%.","_")))
emit("");
emit("#include <inttypes.h>");
emit("");
emit("#if defined( __GNUC__)");
emit("#define PACKED __attribute__ ((packed))");
emit("#else");
emit("#error \"Unsupported compiler?\"");
emit("#endif");
emit("");
emit("#ifndef __WBGEN2_MACROS_DEFINED__");
emit("#define __WBGEN2_MACROS_DEFINED__");
emit("#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))");
emit("#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))");
emit("#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))");
emit("#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))");
emit("#endif");
cgen_c_fileheader();
cgen_c_field_masks();
emit("");
cgen_c_struct();
emit("");
emit("#endif");
cgen_write_current_snippet();
end
trunk/software/wbgen2/cgen_common.lua
View file @ ed76e70f
......@@ -314,6 +314,9 @@ end
function cgen_generate_init(filename)
output_code_file = io.open(filename, "w");
if(output_code_file == nil) then
die("Can't open code output file: "..filename);
end
end
function cgen_generate_done()
......@@ -329,12 +332,13 @@ function cgen_gen_vlog_constants(filename)
foreach_reg(function(reg)
if(reg.__type == TYPE_REG) then
file.write(file, string.format("`define %-30s %d'h%x\n", "ADDR_"..string.upper(periph.hdl_prefix.."_"..reg.hdl_prefix), address_bus_width, reg.base));
file.write(file, string.format("`define %-30s %d'h%x\n", "ADDR_"..string.upper(periph.hdl_prefix.."_"..reg.hdl_prefix), address_bus_width, (DATA_BUS_WIDTH/8) * reg.base));
end
if(reg.__type == TYPE_RAM) then
local base = math.pow(2, reg.select_bits) *
local base = reg.select_bits *
math.pow (2, address_bus_width - address_bus_select_bits);
file.write(file, string.format("`define %-30s %d'h%x\n", "BASE_"..string.upper(periph.hdl_prefix.."_"..reg.hdl_prefix), address_bus_width, base));
file.write(file, string.format("`define %-30s %d'h%x\n", "BASE_"..string.upper(periph.hdl_prefix.."_"..reg.hdl_prefix), address_bus_width+2, (DATA_BUS_WIDTH/8) *base));
file.write(file, string.format("`define %-30s 32'h%x\n", "SIZE_"..string.upper(periph.hdl_prefix.."_"..reg.hdl_prefix), reg.size));
end
end
);
......
trunk/software/wbgen2/cgen_verilog.lua
View file @ ed76e70f
This diff is collapsed.
trunk/software/wbgen2/cgen_vhdl.lua
View file @ ed76e70f
......@@ -244,7 +244,8 @@ function cgen_generate_vhdl_code(tree)
local ts = {};
local sig;
-- if(node==nil) then print(""..node); end
ts.node = node;
-- if it's a direct signal or a numeric constant, it simply returns it.
......@@ -300,6 +301,11 @@ function cgen_generate_vhdl_code(tree)
-- generates the signal name with subrange (if applies): signame, signame(h downto l) or signame(h).
function gen_subrange(t)
-- node is a VHDL "open" pin declaration?
if(type(t.node) == "table" and t.node.t == "openpin") then
return "open";
end
if(t.h ~= nil and t.l == nil) then
return t.name.."("..t.h..")";
elseif(t.h ~= nil and t.l ~= nil) then
......
trunk/software/wbgen2/examples/RAMs/run.do
View file @ ed76e70f
vlib work
vlib wbgen2
../../wbgen2.lua rams.wb -vo ./output/wb_slave_test_rams.vhdl -consto ./output/vlog_constants.v
../../wbgen2.lua rams.wb -vo ./output/wb_slave_test_rams.vhdl -consto ./output/vlog_constants.v -co ./output/test_rams.h
vcom -work wbgen2 ../../lib/wbgen2_pkg.vhd
vcom -work wbgen2 ../../lib/wbgen2_dpssram.vhd
......@@ -13,6 +13,6 @@ vsim work.main
radix -hexadecimal
do wave.do
run 15us
run 1000us
wave zoomfull
trunk/software/wbgen2/examples/RAMs/testbench.v
View file @ ed76e70f
`timescale 1ns/1ps
`define wbclk_period 100
`define async_clk_period 63
`include "output/vlog_constants.v"
module main;
reg clk=1;
reg rst=0;
wire [3:0] ones = 'b1111;
reg ram1_clk = 1;
reg [31:0] rval;
reg rst=0;
// generate clocks & reset
always #(`wbclk_period/2) clk <= ~clk;
always #(`async_clk_period/2) ram1_clk <= ~ram1_clk;
initial #1000 rst <= 1;
`include "wishbone_stuff.v"
wire [31:0] gpio_pins_b;
reg [31:0] gpio_reg = 32'bz;
gpio_port dut(
reg [7:0] ram1_addr = 0;
reg [31:0] ram1_data_wr = 0;
wire [31:0] ram1_data_rd;
reg [3:0] ram1_bwsel = 4'b1111;
reg ram1_wr = 0, ram1_rd = 0;
reg [9:0] ram2_addr = 0;
wire [15:0] ram2_data_rd;
reg ram2_rd = 0;
task ram1_read;
input[31:0] addr;
output [31:0] data;
begin
ram1_addr = {2'b00, addr[9:2]};
ram1_rd = 1;
@(posedge ram1_clk);
#1 data = ram1_data_rd;
ram1_rd = 0;
end
endtask // wb_write
task ram1_write;
input[31:0] addr;
input [31:0] data;
begin
#1 ram1_addr = {2'b00, addr[9:2]};
ram1_data_wr = data;
ram1_wr = 1;
@(posedge ram1_clk);
#1 ram1_wr = 0;
end
endtask
task ram2_read;
input[31:0] addr;
output [31:0] data;
begin
#1 ram2_addr = {2'b00, addr[11:2]};
ram2_rd = 1;
@(posedge clk);
#1 data = ram2_data_rd;
ram2_rd = 0;
end
endtask // wb_write
wb_slave_test_rams
dut(
.rst_n_i (rst),
.wb_clk_i (clk),
.wb_addr_i (wb_addr[10:0]),
.wb_data_i (wb_data_o),
.wb_data_o (wb_data_i),
.wb_cyc_i (wb_cyc),
.wb_sel_i (wb_bwsel),
.wb_stb_i (wb_stb),
.wb_we_i (wb_we),
.wb_ack_o (wb_ack),
.clk1_i (ram1_clk),
.rams_mem1k_addr_i (ram1_addr),
.rams_mem1k_data_o (ram1_data_rd),
.rams_mem1k_rd_i (ram1_rd),
.rams_mem1k_data_i (ram1_data_wr),
.rams_mem1k_wr_i (ram1_wr),
.rams_mem1k_bwsel_i (ram1_bwsel),
.rams_mem2k_addr_i (ram2_addr),
.rams_mem2k_data_o (ram2_data_rd),
.rams_mem2k_rd_i (ram2_rd)
);
integer i;
integer fail = 0;
.rst_n_i (rst),
.wb_clk_i (clk),
.wb_addr_i (wb_addr[2:0]),
.wb_data_i (wb_data_o),
.wb_data_o (wb_data_i),
.wb_cyc_i (wb_cyc),
.wb_stb_i (wb_stb),
.wb_we_i (wb_we),
.wb_ack_o (wb_ack),
.wb_sel_i(ones),
initial begin
#2000; @(posedge clk); #1; // wait until the DUT is reset
.gpio_pins_b (gpio_pins_b)
);
$display("Test simple bus reads/writes...");
assign gpio_pins_b = gpio_reg;
wb_verbose(1);
wb_write(`BASE_RAMS_MEM1K, 32'hdeadbeef);
wb_write(`BASE_RAMS_MEM1K + 4, 32'hcafecafe);
wb_write(`BASE_RAMS_MEM1K + 'h200, 32'hfacedead);
reg[31:0] data;
wb_read(`BASE_RAMS_MEM1K, rval); if(rval != 'hdeadbeef) fail = 1;
wb_read(`BASE_RAMS_MEM1K + 4, rval);if(rval != 'hcafecafe) fail = 1;
wb_read(`BASE_RAMS_MEM1K + 'h200, rval);if(rval != 'hfacedead) fail = 1;
integer i;
$display("Test mirrored bus reads/writes...");
wb_write(`BASE_RAMS_MEM1K + 16, 32'h55555555);
wb_read(`BASE_RAMS_MEM1K + 16, rval);if(rval != 'h55555555) fail = 1;
wb_write(`BASE_RAMS_MEM1K + 4*`SIZE_RAMS_MEM1K + 16, 32'haaaaaaaa);
wb_read(`BASE_RAMS_MEM1K + 16, rval);if(rval != 'haaaaaaaa) fail = 1;
initial begin
#2001; // wait until the DUT is reset
$display("Set half of the pins to outputs, other half to inputs");
wb_write(`ADDR_GPIO_DDR, 32'hffff0000);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
$display("Set every even byte to '1'");
wb_write(`ADDR_GPIO_SOPR, 32'hff00ff00);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
$display("Clear every even bit");
wb_write(`ADDR_GPIO_COPR, 32'h55555555);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
$display("Write an arbitrary value");
wb_write(`ADDR_GPIO_PDR, 32'hdeadbeef);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
$display("Force something tasty on the GPIO input pins");
gpio_reg[15:0] = 16'hcafe;
delay_cycles(1);
$display("Pins state: %b (%x)", gpio_pins_b, gpio_pins_b);
delay_cycles(10); // wait for a while for the sync logic
wb_read(`ADDR_GPIO_PSR, data);
$display("Time for %x!", data[15:0]);
end
$display("Byte-access test...");
wb_verbose(0);
for(i=0;i<32;i=i+1) wb_write_byte(`BASE_RAMS_MEM1K + i, i + 1);
for(i=0;i<32;i=i+1) begin
wb_read_byte(`BASE_RAMS_MEM1K + i, rval);
if(rval != i+1)
fail = 1;
end
$display("mem1k: Bus write/mem read test...");
for(i=0;i<256;i=i+1) wb_write(`BASE_RAMS_MEM1K + i*4, i+1);
@(posedge ram1_clk); // sync ourselves to the edge of RAM1 async clock
for(i=0;i<256;i=i+1) begin
ram1_read(i*4, rval);
if(rval != i+1) fail =1;
end
$display("mem1k: Mem write/bus read test...");
for(i=0;i<256;i=i+1)
ram1_write(i*4, 257-i);
@(posedge clk); // sync back to wb clock
for(i=0;i<256;i=i+1) begin
wb_read(`BASE_RAMS_MEM1K+i*4, rval);
if(rval != 257-i)
fail =1;
end
$display("mem2k: Bus write/mem read test...");
for(i=0;i<512;i=i+1) wb_write(`BASE_RAMS_MEM2K + i*4, 113*i+41);
@(posedge clk); // sync back to wb clock
for(i=0;i<512;i=i+1) begin
ram2_read(i*4, rval);
if(rval != 113*i+41)
fail =1;
end
if(fail)
$display("TESTS FAILED");
else
$display("TESTS PASSED");
end
endmodule
trunk/software/wbgen2/examples/RAMs/wave.do
View file @ ed76e70f
......@@ -6,77 +6,84 @@ add wave -noupdate -format Literal /main/dut/wb_addr_i
add wave -noupdate -format Literal /main/dut/wb_data_i
add wave -noupdate -format Literal /main/dut/wb_data_o
add wave -noupdate -format Logic /main/dut/wb_cyc_i
add wave -noupdate -format Logic /main/dut/wb_sel_i
add wave -noupdate -format Literal /main/dut/wb_sel_i
add wave -noupdate -format Logic /main/dut/wb_stb_i
add wave -noupdate -format Logic /main/dut/wb_we_i
add wave -noupdate -format Logic /main/dut/wb_ack_o
add wave -noupdate -format Literal /main/dut/gpio_pins_b
add wave -noupdate -format Literal /main/dut/gpio_ddr
add wave -noupdate -format Literal /main/dut/gpio_psr
add wave -noupdate -format Literal /main/dut/gpio_pdr
add wave -noupdate -format Logic /main/dut/gpio_pdr_wr
add wave -noupdate -format Literal /main/dut/gpio_sopr
add wave -noupdate -format Logic /main/dut/gpio_sopr_wr
add wave -noupdate -format Literal /main/dut/gpio_copr
add wave -noupdate -format Logic /main/dut/gpio_copr_wr
add wave -noupdate -format Literal /main/dut/gpio_reg
add wave -noupdate -format Literal /main/dut/gpio_pins_sync1
add wave -noupdate -format Literal /main/dut/gpio_pins_sync0
add wave -noupdate -format Logic /main/dut/wb_slave/rst_n_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_clk_i
add wave -noupdate -format Literal /main/dut/wb_slave/wb_addr_i
add wave -noupdate -format Literal /main/dut/wb_slave/wb_data_i
add wave -noupdate -format Literal /main/dut/wb_slave/wb_data_o
add wave -noupdate -format Logic /main/dut/wb_slave/wb_cyc_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_sel_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_stb_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_we_i
add wave -noupdate -format Logic /main/dut/wb_slave/wb_ack_o
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_async_clk_i
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_ddr_o
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_psr_i
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_pdr_o
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_o
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_sopr_o
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_o
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_copr_o
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_o
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_ddr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb_s0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb_s1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_ddr_swb_s2
add wave -noupdate -format Literal /main/dut/wb_slave/gpio_psr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_in_progress
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_s0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_s1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_psr_lwb_s2
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_int_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_sync0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_sync1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_pdr_wr_sync2
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_int_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_sync0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_sync1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_sopr_wr_sync2
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_int
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_int_delay
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_sync0
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_sync1
add wave -noupdate -format Logic /main/dut/wb_slave/gpio_copr_wr_sync2
add wave -noupdate -format Logic /main/dut/wb_slave/wb_ack_regbank
add wave -noupdate -format Literal /main/dut/wb_slave/ack_cntr
add wave -noupdate -format Logic /main/dut/wb_slave/ack_in_progress
add wave -noupdate -format Logic /main/dut/wb_slave/tmpbit
add wave -noupdate -format Literal /main/dut/wb_slave/wb_data_out_int
add wave -noupdate -format Logic /main/dut/rams_mem1k_raminst/clk_a_i
add wave -noupdate -format Logic /main/dut/rams_mem1k_raminst/clk_b_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/addr_a_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/addr_b_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/data_a_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/data_a_o
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/data_b_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/bwsel_a_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/bwsel_b_i
add wave -noupdate -format Logic /main/dut/rams_mem1k_raminst/rd_a_i
add wave -noupdate -format Logic /main/dut/rams_mem1k_raminst/rd_b_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/data_b_o
add wave -noupdate -format Logic /main/dut/rams_mem1k_raminst/wr_a_i
add wave -noupdate -format Logic /main/dut/rams_mem1k_raminst/wr_b_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/clksel
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/bwsel_int_a
add wave -noupdate -format Literal /main/dut/rams_mem1k_raminst/bwsel_int_b
add wave -noupdate -format Logic /main/dut/rst_n_i
add wave -noupdate -format Logic /main/dut/wb_clk_i
add wave -noupdate -format Literal /main/dut/wb_addr_i
add wave -noupdate -format Literal /main/dut/wb_data_i
add wave -noupdate -format Literal /main/dut/wb_data_o
add wave -noupdate -format Logic /main/dut/wb_cyc_i
add wave -noupdate -format Literal /main/dut/wb_sel_i
add wave -noupdate -format Logic /main/dut/wb_stb_i
add wave -noupdate -format Logic /main/dut/wb_we_i
add wave -noupdate -format Logic /main/dut/wb_ack_o
add wave -noupdate -format Logic /main/dut/clk1_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_addr_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_data_o
add wave -noupdate -format Logic /main/dut/rams_mem1k_rd_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_data_i
add wave -noupdate -format Logic /main/dut/rams_mem1k_wr_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_bwsel_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_addr_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_data_o
add wave -noupdate -format Logic /main/dut/rams_mem2k_rd_i
add wave -noupdate -format Literal /main/dut/rams_mem1k_rddata_int
add wave -noupdate -format Logic /main/dut/rams_mem1k_rd_int
add wave -noupdate -format Logic /main/dut/rams_mem1k_wr_int
add wave -noupdate -format Literal /main/dut/rams_mem2k_rddata_int
add wave -noupdate -format Logic /main/dut/rams_mem2k_rd_int
add wave -noupdate -format Logic /main/dut/rams_mem2k_wr_int
add wave -noupdate -format Literal /main/dut/ack_sreg
add wave -noupdate -format Literal /main/dut/rddata_reg
add wave -noupdate -format Literal /main/dut/wrdata_reg
add wave -noupdate -format Literal /main/dut/bwsel_reg
add wave -noupdate -format Literal /main/dut/rwaddr_reg
add wave -noupdate -format Logic /main/dut/ack_in_progress
add wave -noupdate -format Logic /main/dut/wr_int
add wave -noupdate -format Logic /main/dut/rd_int
add wave -noupdate -format Logic /main/dut/bus_clock_int
add wave -noupdate -format Literal /main/dut/allones
add wave -noupdate -format Literal /main/dut/allzeros
add wave -noupdate -format Logic /main/dut/rams_mem2k_raminst/clk_a_i
add wave -noupdate -format Logic /main/dut/rams_mem2k_raminst/clk_b_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/addr_a_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/addr_b_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/data_a_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/data_b_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/data_a_o
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/data_b_o
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/bwsel_a_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/bwsel_b_i
add wave -noupdate -format Logic /main/dut/rams_mem2k_raminst/rd_a_i
add wave -noupdate -format Logic /main/dut/rams_mem2k_raminst/rd_b_i
add wave -noupdate -format Logic /main/dut/rams_mem2k_raminst/wr_a_i
add wave -noupdate -format Logic /main/dut/rams_mem2k_raminst/wr_b_i
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/clksel
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/bwsel_int_a
add wave -noupdate -format Literal /main/dut/rams_mem2k_raminst/bwsel_int_b
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
configure wave -namecolwidth 333
WaveRestoreCursors {{Cursor 1} {192662970 ps} 0}
configure wave -namecolwidth 524
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
......@@ -89,4 +96,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {15750 ns}
WaveRestoreZoom {0 ps} {1050148864 ps}
trunk/software/wbgen2/examples/RAMs/wbgen2/_info
View file @ ed76e70f
......@@ -2,13 +2,35 @@ m255
13
cModel Technology
d/home/slayer/wbgen2_svn/wbgen2/examples/RAMs
Ewbgen2_dpssram
w1269003774
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
F../../lib/wbgen2_dpssram.vhd
l0
L11
V^GZe>D]^?P9JVgYAAikm:3
OE;C;6.2b;35
32
o-work wbgen2
tExplicit 1
Asyn
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work wbgen2_dpssram ^GZe>D]^?P9JVgYAAikm:3
l99
L46
VZD:]3B@TAeo`KW[NHAIkP0
OE;C;6.2b;35
32
M1 ieee std_logic_1164
o-work wbgen2
tExplicit 1
Pwbgen2_pkg
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
w1268865151
w1268907251
F../../lib/wbgen2_pkg.vhd
l0
L6
VFVWLjXUGZQ=jP2HMgk91;3
VO41XCVO6fF0I4?bScoJKd3
OE;C;6.2b;35
32
M1 ieee std_logic_1164
......
trunk/software/wbgen2/examples/RAMs/wishbone_stuff.v
View file @ ed76e70f
reg [31:0] wb_addr, wb_data_o, tmp;
reg [31:0] wb_addr = 0, wb_data_o = 0;
reg [3:0] wb_bwsel =4'b1111;
wire [31:0] wb_data_i;
wire wb_ack;
reg wb_sel =0, wb_cyc=0, wb_stb=0, wb_we= 0;
reg wb_cyc=0, wb_stb=0, wb_we= 0;
reg wb_tb_verbose = 1;
task delay_cycles;
input [31:0] n;
task wb_verbose;
input onoff;
begin
#(n * `wbclk_period);
wb_tb_verbose = onoff;
end
endtask // delay_cycles
endtask // wb_verbose
task wb_write;
input[31:0] addr;
input [31:0] data;
task wb_write;
input[31:0] addr;
input [31:0] data;
begin
if(wb_tb_verbose) $display("WB write: addr %x, data %x", addr, data);
wb_stb=1;
wb_cyc=1;
wb_addr = {2'b00, addr[31:2]};
wb_data_o=data;
wb_we = 1;
wb_bwsel = 4'hf;
while(wb_ack == 0) begin @(posedge clk); #1; end
@(posedge clk); #1
wb_cyc = 0;
wb_we=0;
wb_stb=0;
end
endtask // wb_write
task wb_write_byte;
input[31:0] addr;
input [31:0] data;
begin
$display("WB write: addr %x, data %x", addr, data);
wb_sel=1;
wb_stb=1;
wb_cyc=1;
wb_addr = addr;
wb_data_o=data;
wb_we = 1;
if(wb_tb_verbose) $display("WB write_byte: addr %x, data %x", addr, data);
wb_stb=1;
wb_cyc=1;
wb_addr ={ 2'b00, addr[31:2] };
wb_data_o= (addr [1:0] == 2'b00) ? {data[7:0], 24'bx} :
(addr [1:0] == 2'b01) ? {8'bx, data[7:0], 16'bx} :
(addr [1:0] == 2'b10) ? {16'bx, data[7:0], 8'bx} :
(addr [1:0] == 2'b11) ? {24'bx, data[7:0]} : 32'bx;
wb_we = 1;
wb_bwsel = (addr [1:0] == 2'b00) ? 'b1000 :
(addr [1:0] == 2'b01) ? 'b0100 :
(addr [1:0] == 2'b10) ? 'b0010 :
(addr [1:0] == 2'b11) ? 'b0001 : 4'bxxxx;
delay_cycles(1);
while(wb_ack == 0)
delay_cycles(1);
delay_cycles(1);
wb_cyc = 0;
wb_sel=0;
wb_we=0;
wb_stb=0;
while(wb_ack == 0) begin @(posedge clk); #1; end
@(posedge clk); #1;
wb_cyc = 0;
wb_we=0;
wb_stb=0;
end
endtask // wb_write
......@@ -40,24 +84,53 @@
input[31:0] addr;
output [31:0] data;
begin
wb_sel=1;
wb_stb=1;
wb_cyc=1;
wb_addr = addr;
wb_data_o=data;
wb_we = 0;
delay_cycles(1);
while(wb_ack == 0)
delay_cycles(1);
data = wb_data_i;
delay_cycles(1);
wb_cyc = 0;
wb_sel=0;
wb_we=0;
wb_stb=0;
wb_bwsel=4'hf;
wb_stb=1;
wb_cyc=1;
wb_addr = {2'b00, addr[31:2]};
wb_data_o=data;
wb_we = 0;
while(wb_ack == 0) @(posedge clk);
#1 data = wb_data_i;
@(posedge clk);
wb_cyc = 0;
wb_we=0;
wb_stb=0;
if(wb_tb_verbose) $display("WB read: addr %x data %x", addr, data);
end
endtask // wb_read
task wb_read_byte;
input[31:0] addr;
output [31:0] data;
begin : task_wb_read_byte
reg [31:0] data_tmp;
wb_bwsel=4'hf;
wb_stb=1;
wb_cyc=1;
wb_addr = {2'b00, addr[31:2]};
wb_data_o=data;
wb_we = 0;
while(wb_ack == 0) @(posedge clk);
#1 data = (addr [1:0] == 2'b00) ? wb_data_i[31:24] :
(addr [1:0] == 2'b01) ? wb_data_i[23:16] :
(addr [1:0] == 2'b10) ? wb_data_i[15:8] :
(addr [1:0] == 2'b11) ? wb_data_i[7:0] : 4'bxxxx;
@(posedge clk);
wb_cyc = 0;
wb_we=0;
wb_stb=0;
if(wb_tb_verbose) $display("WB read byte: addr %x data %x", addr, data);
end
endtask // wb_read
\ No newline at end of file
trunk/software/wbgen2/examples/RAMs/work/_info
View file @ ed76e70f
......@@ -3,11 +3,19 @@ m255
cModel Technology
d/home/slayer/wbgen2_svn/wbgen2/examples/RAMs
T_opt
Vf9b?XRk;HFN=5Q[hJ?3@B1
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
T_opt1
VA:`f030HMAPjdST`l7eQQ2
04 4 4 work main fast 0
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
T_opt2
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
Egpio_port
w1268865151
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
......@@ -29,13 +37,13 @@ OE;C;6.2b;35
M1 ieee std_logic_1164
tExplicit 1
vmain
IOT`WFa]ZX5_Ob[Mb8Clm33
IgRg>D1noQ7dH21j:7TPk12
VEAT@0_d?1jQUQ5cgEJon`1
w1268865151
w1269015033
F./testbench.v
Foutput/vlog_constants.v
Fwishbone_stuff.v
L0 7
L0 8
VEAT@0_d?1jQUQ5cgEJon`1
OE;L;6.2b;35
r1
......@@ -63,3 +71,31 @@ OE;C;6.2b;35
M2 ieee std_logic_1164
M1 ieee numeric_std
tExplicit 1
Ewb_slave_test_rams
w1269015033
DP wbgen2 wbgen2_pkg O41XCVO6fF0I4?bScoJKd3
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
F./output/wb_slave_test_rams.vhdl
l0
L19
VhQNYdf_X>K:Gz6`0m;=G=2
OE;C;6.2b;35
32
o-work work
tExplicit 1
Asyn
DP wbgen2 wbgen2_pkg O41XCVO6fF0I4?bScoJKd3
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work wb_slave_test_rams hQNYdf_X>K:Gz6`0m;=G=2
l73
L53
V_1C5NMmc]ZDzB^ZZSV72o2
OE;C;6.2b;35
32
M3 ieee std_logic_1164
M2 ieee numeric_std
M1 wbgen2 wbgen2_pkg
o-work work
tExplicit 1
trunk/software/wbgen2/examples/RAMs/work/_opt/work__info
View file @ ed76e70f
......@@ -3,64 +3,97 @@ m255
cModel Technology
d/home/slayer/wbgen2_svn/wbgen2/examples/RAMs
T_opt
Vf9b?XRk;HFN=5Q[hJ?3@B1
04 4 4 work main fast 0
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
T_opt1
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
T_opt2
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
Egpio_port
w1268865151
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
F./gpio_port.vhdl
l0
L27
V=48Cd@cI0EFDRnHinnSkI2
OE;C;6.2b;35
32
tExplicit 1
Asyn
DE work wb_slave_gpio_port jCZBzXQYDT`TMj1DM8gO;0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work gpio_port =48Cd@cI0EFDRnHinnSkI2
32
M1 ieee std_logic_1164
l86
L46
VE9ChVMG=a34IjH39JN^@>2
OE;C;6.2b;35
32
M1 ieee std_logic_1164
tExplicit 1
vmain
IOT`WFa]ZX5_Ob[Mb8Clm33
IJ];cmm_je45gB057SFl7E0
VEAT@0_d?1jQUQ5cgEJon`1
w1268865151
w1268907328
F./testbench.v
Foutput/vlog_constants.v
Fwishbone_stuff.v
L0 7
L0 8
VEAT@0_d?1jQUQ5cgEJon`1
OE;L;6.2b;35
r1
31
Ewb_slave_gpio_port
w1268867795
w1268867801
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
F./output/wb_slave_gpio_port.vhdl
l0
L17
VjCZBzXQYDT`TMj1DM8gO;0
OE;C;6.2b;35
32
tExplicit 1
Asyn
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work wb_slave_gpio_port jCZBzXQYDT`TMj1DM8gO;0
32
M2 ieee std_logic_1164
M1 ieee numeric_std
l60
L45
VN=Coe86jG20]Cd<;BBnLC1
OE;C;6.2b;35
32
M2 ieee std_logic_1164
M1 ieee numeric_std
tExplicit 1
Ewb_slave_test_rams
w1268907328
DP wbgen2 wbgen2_pkg O41XCVO6fF0I4?bScoJKd3
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
F./output/wb_slave_test_rams.vhdl
l0
L19
VhQNYdf_X>K:Gz6`0m;=G=2
OE;C;6.2b;35
32
o-work work
tExplicit 1
Asyn
DP wbgen2 wbgen2_pkg O41XCVO6fF0I4?bScoJKd3
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work wb_slave_test_rams hQNYdf_X>K:Gz6`0m;=G=2
l73
L53
V_1630@AdY0_LcU47bLKNL3
OE;C;6.2b;35
32
M3 ieee std_logic_1164
M2 ieee numeric_std
M1 wbgen2 wbgen2_pkg
o-work work
tExplicit 1
trunk/software/wbgen2/examples/gpio_port/gpio_port.mpf
View file @ ed76e70f
......@@ -802,6 +802,6 @@ XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
EditorState = {tabbed horizontal 1} {/home/slayer/TWVGA/core_verilog/run.do 0 0} {/home/slayer/TWVGA/core_verilog/testbench-uart.v 0 0}
EditorState = {tabbed horizontal 1}
Project_Major_Version = 6
Project_Minor_Version = 2
trunk/software/wbgen2/lib/wbgen2_dpssram.vhd
View file @ ed76e70f
......@@ -30,8 +30,8 @@ entity wbgen2_dpssram is
data_a_o : out std_logic_vector(g_data_width-1 downto 0);
data_b_o : out std_logic_vector(g_data_width-1 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
rd_a_i : in std_logic;
rd_b_i : in std_logic;
......@@ -79,57 +79,88 @@ architecture syn of wbgen2_dpssram is
clock0 : in std_logic;
wren_b : in std_logic;
clock1 : in std_logic;
byteena_a : in std_logic_vector (3 downto 0);
byteena_b : in std_logic_vector (3 downto 0);
address_a : in std_logic_vector (4 downto 0);
address_b : in std_logic_vector (4 downto 0);
byteena_a : in std_logic_vector ((g_data_width+7)/8-1 downto 0);
byteena_b : in std_logic_vector ((g_data_width+7)/8-1 downto 0);
address_a : in std_logic_vector ((g_addr_width-1) downto 0);
address_b : in std_logic_vector ((g_addr_width-1) downto 0);
rden_a : in std_logic;
q_a : out std_logic_vector (31 downto 0);
q_a : out std_logic_vector ((g_data_width-1) downto 0);
rden_b : in std_logic;
q_b : out std_logic_vector (31 downto 0);
data_a : in std_logic_vector (31 downto 0);
data_b : in std_logic_vector (31 downto 0));
q_b : out std_logic_vector ((g_data_width-1) downto 0);
data_a : in std_logic_vector ((g_data_width-1) downto 0);
data_b : in std_logic_vector ((g_data_width-1) downto 0));
end component;
signal clksel : string(1 to 6);
signal bwsel_int_a : std_logic_vector((g_data_width+7)/8 downto 0);
signal bwsel_int_b : std_logic_vector((g_data_width+7)/8 downto 0);
signal bwsel_int_a : std_logic_vector((g_data_width+7)/8-1 downto 0);
signal bwsel_int_b : std_logic_vector((g_data_width+7)/8-1 downto 0);
begin -- syn
-- genclksel1: if(g_dual_clock = true) generate
-- clksel <= "CLOCK1";
-- end generate genclksel1;
genram1: if(g_dual_clock = true) generate
-- genclksel2: if(g_dual_clock = false) generate
-- clksel <= "CLOCK0";
-- end generate genclksel2;
altsyncram_component : altsyncram
generic map (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => g_size,
numwords_b => g_size,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "OLD_DATA",
read_during_write_mode_port_b => "OLD_DATA",
widthad_a => g_addr_width,
widthad_b => g_addr_width,
width_a => g_data_width,
width_b => g_data_width,
width_byteena_a => (g_data_width+7)/8,
width_byteena_b => (g_data_width+7)/8,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
port map (
wren_a => wr_a_i,
wren_b => wr_b_i,
clock0 => clk_a_i,
clock1 => clk_b_i,
byteena_a => bwsel_int_a,
byteena_b => bwsel_int_b,
address_a => addr_a_i,
address_b => addr_b_i,
rden_a => rd_a_i,
rden_b => rd_b_i,
data_a => data_a_i,
data_b => data_b_i,
q_a => data_a_o,
q_b => data_b_o
);
clksel <= "CLOCK1" when g_dual_clock = true else "CLOCK0";
end generate genram1;
genbwsel1: if(g_use_bwsel = true) generate
bwsel_int_a <= bwsel_a_i;
bwsel_int_b <= bwsel_b_i;
end generate genbwsel1;
genbwsel2: if(g_use_bwsel = false) generate
bwsel_int_a <= (others => '1');
bwsel_int_b <= (others => '1');
end generate genbwsel2;
genram2: if(g_dual_clock = false) generate
altsyncram_component : altsyncram
altsyncram_component : altsyncram
generic map (
address_reg_b => clksel,
byteena_reg_b => clksel,
address_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => clksel,
indata_reg_b => "CLOCK0",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => g_size,
......@@ -148,12 +179,12 @@ begin -- syn
width_b => g_data_width,
width_byteena_a => (g_data_width+7)/8,
width_byteena_b => (g_data_width+7)/8,
wrcontrol_wraddress_reg_b => clksel
wrcontrol_wraddress_reg_b => "CLOCK0"
)
port map (
wren_a => wr_a_i,
clock0 => clk_a_i,
wren_b => wr_b_i,
clock0 => clk_a_i,
clock1 => clk_b_i,
byteena_a => bwsel_int_a,
byteena_b => bwsel_int_b,
......@@ -167,6 +198,22 @@ begin -- syn
q_b => data_b_o
);
end generate genram2;
-- clksel <= ;
genbwsel1: if(g_use_bwsel = true) generate
bwsel_int_a <= bwsel_a_i;
bwsel_int_b <= bwsel_b_i;
end generate genbwsel1;
genbwsel2: if(g_use_bwsel = false) generate
bwsel_int_a <= (others => '1');
bwsel_int_b <= (others => '1');
end generate genbwsel2;
......
trunk/software/wbgen2/lib/wbgen2_pkg.vhd
View file @ ed76e70f
......@@ -22,12 +22,62 @@ package wbgen2_pkg is
data_b_i : in std_logic_vector(g_data_width-1 downto 0);
data_a_o : out std_logic_vector(g_data_width-1 downto 0);
data_b_o : out std_logic_vector(g_data_width-1 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
rd_a_i : in std_logic;
rd_b_i : in std_logic;
wr_a_i : in std_logic;
wr_b_i : in std_logic);
end component;
component wbgen2_eic
generic (
g_num_interrupts : natural;
g_irq00_mode : std_logic_vector(1 downto 0);
g_irq01_mode : std_logic_vector(1 downto 0);
g_irq02_mode : std_logic_vector(1 downto 0);
g_irq03_mode : std_logic_vector(1 downto 0);
g_irq04_mode : std_logic_vector(1 downto 0);
g_irq05_mode : std_logic_vector(1 downto 0);
g_irq06_mode : std_logic_vector(1 downto 0);
g_irq07_mode : std_logic_vector(1 downto 0);
g_irq08_mode : std_logic_vector(1 downto 0);
g_irq09_mode : std_logic_vector(1 downto 0);
g_irq0a_mode : std_logic_vector(1 downto 0);
g_irq0b_mode : std_logic_vector(1 downto 0);
g_irq0c_mode : std_logic_vector(1 downto 0);
g_irq0d_mode : std_logic_vector(1 downto 0);
g_irq0e_mode : std_logic_vector(1 downto 0);
g_irq0f_mode : std_logic_vector(1 downto 0);
g_irq10_mode : std_logic_vector(1 downto 0);
g_irq11_mode : std_logic_vector(1 downto 0);
g_irq12_mode : std_logic_vector(1 downto 0);
g_irq13_mode : std_logic_vector(1 downto 0);
g_irq14_mode : std_logic_vector(1 downto 0);
g_irq15_mode : std_logic_vector(1 downto 0);
g_irq16_mode : std_logic_vector(1 downto 0);
g_irq17_mode : std_logic_vector(1 downto 0);
g_irq18_mode : std_logic_vector(1 downto 0);
g_irq19_mode : std_logic_vector(1 downto 0);
g_irq1a_mode : std_logic_vector(1 downto 0);
g_irq1b_mode : std_logic_vector(1 downto 0);
g_irq1c_mode : std_logic_vector(1 downto 0);
g_irq1d_mode : std_logic_vector(1 downto 0);
g_irq1e_mode : std_logic_vector(1 downto 0);
g_irq1f_mode : std_logic_vector(1 downto 0));
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
reg_ier_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_ier_wr_stb_i : in std_logic;
reg_idr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_idr_wr_stb_i : in std_logic;
reg_isr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
reg_isr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_isr_wr_stb_i : in std_logic;
wb_irq_o : out std_logic);
end component;
end wbgen2_pkg;
trunk/software/wbgen2/target_wishbone.lua
View file @ ed76e70f
......@@ -152,6 +152,7 @@ function gen_bus_logic_wishbone()
}, {
va(vi("ack_sreg", acklen), 1);
});
va("ack_in_progress", 1);
} ); } );
end
end
......@@ -187,6 +188,7 @@ function gen_bus_logic_wishbone()
vsyncprocess("bus_clock_int", "rst_n_i", {
vreset(0, {
va("ack_sreg", 0);
va("ack_in_progress", 0);
va("rddata_reg", 0);
resetcode
});
......@@ -238,12 +240,12 @@ function gen_bus_logic_wishbone()
-- now generate an address decoder for the RAMs, driving rd_i and wr_i lines.
local sens_list = { "wb_addr_i", "wb_cyc_i", "wb_stb_i", "wb_we_i" };
local sens_list = { "wb_addr_i", "rd_int", "wr_int" };
local proc_body = { };
foreach_reg(function(reg)
if(reg.__type == TYPE_RAM) then
table.insert(sens_list, reg.full_prefix.."_rddata_int");
-- table.insert(sens_list, reg.full_prefix.."_rddata_int");
table_join(proc_body, {vif(vequal(vi("wb_addr_i", address_bus_width-1, address_bus_width - address_bus_select_bits), reg.select_bits), {
va(reg.full_prefix.."_rd_int", "rd_int");
va(reg.full_prefix.."_wr_int", "wr_int");
......
trunk/software/wbgen2/wbgen_common.lua
View file @ ed76e70f
......@@ -11,6 +11,7 @@ TYPE_FIELD = 3;
TYPE_FIFO = 4;
TYPE_ENUM = 5;
TYPE_RAM = 6;
TYPE_IRQ = 7;
-- FIFO register flags
FIFO_FULL = 0x1;
......@@ -39,9 +40,11 @@ PASS_THROUGH = 0x40;
INTEGER = 0x80;
EXPRESSION = 0x100;
-- reg LOAD types
LOAD_INT = 1;
LOAD_EXT = 2;
-- access shorcuts
ACC_RO_WO = 1;
ACC_WO_RO = 2;
ACC_RW_RW = 3;
......@@ -50,12 +53,19 @@ ACC_RW_RO = 4;
FROM_WB = 1;
TO_WB = 2;
-- IRQ triggers
EDGE_RISING = 0;
EDGE_FALLING = 1;
LEVEL_0 = 2;
LEVEL_1 = 3;
function peripheral(x) x['__type']=TYPE_PERIPH; periph = x; return x; end
function reg(x) x['__type']=TYPE_REG; return x; end
function field(x) x['__type']=TYPE_FIELD; return x; end
function fifo_reg(x) x['__type']=TYPE_FIFO; return x; end
function ram(x) x['__type']=TYPE_RAM; return x; end
function enum(x) x['__type']=TYPE_ENUM; return x; end
function irq(x) x['__type']=TYPE_IRQ; return x; end
function range2bits(range)
......@@ -138,7 +148,17 @@ end
function foreach_reg(func)
for i,v in pairs(periph) do
if(type(v) == 'table') then
if(v.__type ~= nil and (v.__type == TYPE_REG or v.__type == TYPE_FIFO or v.__type == TYPE_RAM)) then
if(v.__type ~= nil and (v.__type == TYPE_REG or v.__type == TYPE_FIFO or v.__type == TYPE_RAM or v.__type == TYPE_IRQ)) then
func(v);
end
end
end
end
function foreach_regx(accepted_types, func)
for i,v in pairs(periph) do
if(type(v) == 'table') then
if(v.__type ~= nil and (match(v.__type, accepted_types))) then
func(v);
end
end
......@@ -427,6 +447,7 @@ function wbgen_count_subblocks()
local ramcount = 0;
local fifocount = 0;
local regcount = 0;
local irqcount = 0;
-- count the RAMs & FIFOs in the design
foreach_reg(function(reg)
......@@ -439,11 +460,20 @@ function wbgen_count_subblocks()
if(reg.__type == TYPE_REG) then
regcount = regcount + 1;
end
end
if(reg.__type == TYPE_IRQ) then
irqcount = irqcount + 1;
end
end
);
periph.ramcount = ramcount;
periph.fifocount = fifocount;
periph.regcount = regcount;
periph.irqcount = irqcount;
if(ramcount + fifocount + regcount + irqcount == 0) then
die("Can't generate an empty peripheral. Define some regs, RAMs, FIFOs or IRQs, please...");
end
end
trunk/software/wbgen2/wbgen_eic.lua 0 → 100644
View file @ ed76e70f
-- -*- Mode: LUA; tab-width: 2 -*-
-- wbgen2 - a simple Wishbone slave generator
-- (c) 2010 Tomasz Wlostowski
-- CERN BE-Co-HT
-- LICENSED UNDER GPL v2
-- EIC (tm) = Embedded Interrupt Controller
-- regs:
--
-- EIC_IER = interrupt enable reg [passthru]
-- EIC_IDR = interrupt disable reg [passthru]
-- EIC_IMR = interrupt mask reg [rw, load-ext]
-- EIC_ISR = interrupt status reg [rw, reset on write 1]
--
function wbgen_gen_irq_controller()
-- trigger = IRQ_POSEDGE, NEGEDGE, HIGH, LOW
-- name, desc
-- c/hdl_prefix
local irq_list = {};
foreach_reg(function(irq) if(irq.__type == TYPE_IRQ) then
print("IRQ: "..irq.name);
end
end);
end
trunk/software/wbgen2/wbgen2.lua → trunk/software/wbgen2/wbgen_main.lua
View file @ ed76e70f
#!/usr/bin/lua
wbgen2_version="0.3"
wbgen2_libdir="/home/slayer/wbgen2_svn/wbgen2"
wbgen2_version="0.5"
device_family="altera_cyclone3";
......@@ -10,15 +8,21 @@ options = {};
options.reset_type = "asynchronous";
options.target_interconnect = "wb-classic";
options.register_data_output = false;
options.lang = "vhdl";
function my_dofile(name)
dofile("/home/slayer/wbgen2_svn/wbgen2/"..name);
end
dofile(wbgen2_libdir.."/wbgen_common.lua");
dofile(wbgen2_libdir.."/cgen_common.lua");
dofile(wbgen2_libdir.."/cgen_vhdl.lua");
dofile(wbgen2_libdir.."/cgen_verilog.lua");
dofile(wbgen2_libdir.."/cgen_c_headers.lua");
dofile(wbgen2_libdir.."/wbgen_regbank.lua");
dofile(wbgen2_libdir.."/wbgen_rams.lua");
dofile(wbgen2_libdir.."/target_wishbone.lua");
my_dofile("wbgen_common.lua");
my_dofile("cgen_common.lua");
my_dofile("cgen_vhdl.lua");
my_dofile("cgen_verilog.lua");
my_dofile("cgen_c_headers.lua");
my_dofile("wbgen_regbank.lua");
my_dofile("wbgen_rams.lua");
my_dofile("wbgen_eic.lua");
my_dofile("target_wishbone.lua");
function chk_nil(p,s)
if(p == nil) then
......@@ -56,15 +60,21 @@ function parse_args(arg)
while(arg[n] ~= nil) do
local sw = arg[n];
if(sw == "-vo") then
if (sw == "-vo") then
options.output_hdl_file = chk_nil(arg[n+1], "HDL output filename expected");
n=n+2;
elseif(sw == "-co") then
elseif (sw == "-co") then
options.output_c_header_file = chk_nil(arg[n+1], "C header output filename expected");
n=n+2;
elseif(sw == "-consto") then
elseif (sw == "-consto") then
options.output_vlog_constants_file = chk_nil(arg[n+1],"Verilog constants filename expected");
n=n+2;
elseif (sw == "-lang") then
options.lang = chk_nil(arg[n+1],"Target HDL language name expected");
if (options.lang ~= "vhdl" and options.lang ~= "verilog") then
die("Unknown HDL: "..options.lang);
end
n=n+2;
else
n=n+1;
end
......@@ -109,7 +119,12 @@ cgen_build_signals_ports();
if(options.output_hdl_file ~= nil) then
cgen_generate_init(options.output_hdl_file)
cgen_generate_vhdl_code(tree);
if (options.lang == "vhdl") then
cgen_generate_vhdl_code(tree);
elseif (options.lang == "verilog") then
cgen_generate_verilog_code(tree);
end
cgen_generate_done();
end
......
trunk/software/wbgen2/wbgen_rams.lua
View file @ ed76e70f
......@@ -15,7 +15,7 @@ function ram_wire_core_ports(ram)
vpm ("rd_b_i", prefix.."_rd_i"); } );
else -- ram is not readable - the read strobe low and leave the data output open
table_join(ram.maps, { vpm ("data_b_o", vopenpin());
vpm ("rd_b_i", vi(allzeros, 0)) });
vpm ("rd_b_i", vi("allzeros", 0)) });
end
if(match(ram.access_dev, {WRITE_ONLY, READ_WRITE})) then
......
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