Project description
Project to share generic HDL cores.
General project information
To make cores more easy to share, they should be coded has described in the VHDL coding guidelines .
Wishbone slave core generator
Wishbone slave core generator (wbgen2) is a Lua script for generating VHDL Wishbone slave cores from a register set description provided by the user. By the ”slave core” we mean a HDL entity which is connected to Wishbone bus on one side, and on the other side it provides ports for accessing memory mapped registers, FIFOs and RAMs.
Sources and documentation are in SVN repository : wbgen2_sources
Requires LUA 5.1.4+.