includeModuleSV.sv 431 Bytes
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//                              -*- Mode: Verilog -*-
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// Filename        : includeModuleSV.sv
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// Description     : Included submodule
// Author          : Adrian Fiergolski
// Created On      : Thu Sep 18 10:51:41 2014
// Last Modified By: Adrian Fiergolski
// Last Modified On: Thu Sep 18 10:51:41 2014
// Update Count    : 0
// Status          : Unknown, Use with caution!

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module includeModuleSV;
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endmodule // includeModuleSV