Commit 0c0be836 authored by Tristan Gingold's avatar Tristan Gingold

Add a test for vlg macro not found.

parent e07d8a68
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PWD := $(shell pwd)
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := vlog.v \
VERILOG_OBJ := work/vlog/.vlog_v \
VHDL_SRC :=
VHDL_OBJ :=
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/.work
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/.work:
(vlib work && vmap $(VMAP_FLAGS) work && touch work/.work )|| rm -rf work
work/vlog/.vlog_v: vlog.v
vlog -work work $(VLOG_FLAGS) ${INCLUDE_DIRS} $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "vlog.v" ]
module gate;
wire `name(w3);
endmodule
......@@ -375,6 +375,9 @@ def test_err_vlog_define():
with pytest.raises(SystemExit) as _:
run([], path="078err_vlg_define")
def test_err_vlog_no_macro():
run_compare(path="079err_vlg_macro")
def test_dep_level():
run(['list-files'], path="053vlog_dep_level")
run(['list-files', '--delimiter', ','], path="053vlog_dep_level")
......
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