Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Commits
2431e387
Commit
2431e387
authored
Mar 30, 2019
by
Javier D. Garcia-Lasheras
1
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Fix Active-HDL support in Windows Cmd and PowerShell
parent
13f5d20e
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
10 additions
and
10 deletions
+10
-10
active_hdl.py
hdlmake/tools/active_hdl.py
+10
-10
No files found.
hdlmake/tools/active_hdl.py
View file @
2431e387
...
...
@@ -56,31 +56,31 @@ class ToolActiveHDL(ToolSim):
"""Print Makefile compilation target for Aldec Active-HDL simulator"""
fileset
=
self
.
fileset
self
.
writeln
(
"simulation:"
)
self
.
writeln
(
"
\t\t
echo
\"
# Active-HDL command file,"
" generated by HDLMake
\"
> run.command"
)
self
.
writeln
(
"
\t\t
echo # Active-HDL command file,"
" generated by HDLMake > run.command"
)
self
.
writeln
()
self
.
writeln
(
"
\t\t
echo
\"
# Create library and set as"
" default target
\"
>> run.command"
)
self
.
writeln
(
"
\t\t
echo
\"
alib work
\"
>> run.command"
)
self
.
writeln
(
"
\t\t
echo
\"
set worklib work
\"
>> run.command"
)
self
.
writeln
(
"
\t\t
echo # Create library and set as"
" default target >> run.command"
)
self
.
writeln
(
"
\t\t
echo
alib work
>> run.command"
)
self
.
writeln
(
"
\t\t
echo
set worklib work
>> run.command"
)
self
.
writeln
()
self
.
writeln
(
"
\t\t
echo
\"
# Compiling HDL source files
\"
>> run.command"
)
"
\t\t
echo
# Compiling HDL source files
>> run.command"
)
for
vl_file
in
fileset
.
filter
(
VerilogFile
):
self
.
writeln
(
"
\t\t
echo
\"
alog
"
+
"
\t\t
echo
alog
\"
"
+
vl_file
.
rel_path
(
)
+
"
\"
>> run.command"
)
for
sv_file
in
fileset
.
filter
(
SVFile
):
self
.
writeln
(
"
\t\t
echo
\"
alog
"
+
"
\t\t
echo
alog
\"
"
+
sv_file
.
rel_path
(
)
+
"
\"
>> run.command"
)
for
vhdl_file
in
fileset
.
filter
(
VHDLFile
):
self
.
writeln
(
"
\t\t
echo
\"
acom
"
+
"
\t\t
echo
acom
\"
"
+
vhdl_file
.
rel_path
(
)
+
"
\"
>> run.command"
)
...
...
Javier D. Garcia-Lasheras
@garcialasheras
mentioned in issue
#7 (closed)
·
Mar 30, 2019
mentioned in issue
#7 (closed)
mentioned in issue #7
Toggle commit list
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment