Move shell stuff to the root folder

parent 71431bfc
......@@ -28,7 +28,7 @@ import os
import logging
import sys
from hdlmake.util import shell
from hdlmake import shell
from hdlmake.util.termcolor import colored
from hdlmake import new_dep_solver as dep_solver
from hdlmake import fetch as fetch_mod
......
......@@ -23,7 +23,7 @@
from __future__ import absolute_import
import os
from hdlmake.util import shell
from hdlmake import shell
class Fetcher(object):
......
......@@ -24,7 +24,7 @@
from __future__ import absolute_import
import os
from hdlmake.util import path as path_utils
from hdlmake.util import shell
from hdlmake import shell
import logging
from .constants import GIT
from .fetcher import Fetcher
......
......@@ -33,7 +33,7 @@ import os
import logging
from hdlmake.util import path as path_mod
from hdlmake.util import shell
from hdlmake import shell
from hdlmake.manifest_parser import ManifestParser
from .content import ModuleContent
import six
......
......@@ -29,7 +29,7 @@ import logging
from .make_syn import ToolSyn
from hdlmake.util import shell
from hdlmake import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
UCFFile, CDCFile, NGCFile)
......
......@@ -31,7 +31,7 @@ import os.path
import logging
from .make_sim import ToolSim
from hdlmake.util import shell
from hdlmake import shell
from hdlmake.srcfile import VerilogFile, VHDLFile
......
......@@ -7,7 +7,7 @@ import string
import logging
from .makefile import ToolMakefile
from hdlmake.util import shell
from hdlmake import shell
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
from hdlmake.dep_file import DepFile
......
......@@ -6,7 +6,7 @@ import logging
import string
from .makefile import ToolMakefile
from hdlmake.util import shell
from hdlmake import shell
def _check_synthesis_manifest(manifest_dict):
......
......@@ -28,7 +28,7 @@ import os
import logging
import six
from hdlmake.util import shell
from hdlmake import shell
class ToolMakefile(object):
......
......@@ -30,7 +30,7 @@ import logging
from .make_syn import ToolSyn
from hdlmake.util import path as path_mod
from hdlmake.util import shell
from hdlmake import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
SignalTapFile, SDCFile, QIPFile, QSYSFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
......
......@@ -28,7 +28,7 @@ import os
import string
from .make_sim import ToolSim
from hdlmake.util import shell
from hdlmake import shell
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
import six
......
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