Skip to content

H
Hdlmake
Commit 30e76327 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
Browse files
Options

Start moving the module stuff to a dedicated folder

parent 8b810c56
Hide whitespace changes
Inline Side-by-side
Showing with 19 additions and 18 deletions
hdlmake/module_altera.py → hdlmake/mod/altera.py
View file @ 30e76327
import os
from .module_plugin import ModulePlugin
from .util import path as path_mod
from .plugin import ModulePlugin
from hdlmake.util import path as path_mod
class ModuleAltera(ModulePlugin):
def __init__(self):
......@@ -16,7 +16,7 @@ class ModuleAltera(ModulePlugin):
super(ModuleAltera, self).process_manifest()
def _process_manifest_altera(self):
from .srcfile import TCLFile
from hdlmake.srcfile import TCLFile
if self.manifest_dict["quartus_preflow"] != None:
path = path_mod.rel2abs(self.manifest_dict["quartus_preflow"], self.path);
if not os.path.exists(path):
......
hdlmake/module_content.py → hdlmake/mod/content.py
View file @ 30e76327
import logging
from . import fetch
from .module_plugin import ModulePlugin
from .util import path as path_mod
from hdlmake import fetch
from .plugin import ModulePlugin
from hdlmake.util import path as path_mod
class ModuleContent(ModulePlugin):
def __init__(self):
......@@ -20,7 +20,7 @@ class ModuleContent(ModulePlugin):
super(ModuleContent, self).process_manifest()
def _process_manifest_files(self):
from .srcfile import TCLFile, VerilogFile, VHDLFile, SourceFileSet
from hdlmake.srcfile import TCLFile, VerilogFile, VHDLFile, SourceFileSet
# HDL files provided by the module
if self.manifest_dict["files"] == []:
self.files = SourceFileSet()
......
hdlmake/module_core.py → hdlmake/mod/core.py
View file @ 30e76327
from .module_plugin import ModulePlugin
from .plugin import ModulePlugin
class ModuleCore(ModulePlugin):
def __init__(self):
......
hdlmake/module_simulation.py → hdlmake/mod/simulation.py
View file @ 30e76327
from .module_plugin import ModulePlugin
from .plugin import ModulePlugin
class ModuleSimulation(object):
class ModuleSimulation(ModulePlugin):
def __init__(self):
# Manifest Simulation Properties
......@@ -24,7 +24,7 @@ class ModuleSimulation(object):
super(ModuleSimulation, self).process_manifest()
def _process_manifest_simulation(self):
from .srcfile import SourceFileSet
from hdlmake.srcfile import SourceFileSet
# Simulation properties
self.sim_tool = self.manifest_dict["sim_tool"]
self.sim_top = self.manifest_dict["sim_top"]
......
hdlmake/module_synthesis.py → hdlmake/mod/synthesis.py
View file @ 30e76327
from .module_plugin import ModulePlugin
from .plugin import ModulePlugin
class ModuleSynthesis(ModulePlugin):
def __init__(self):
......
hdlmake/module.py
View file @ 30e76327
......@@ -28,11 +28,11 @@ import logging
from .manifest_parser import Manifest, ManifestParser
from .util import path as path_mod
from . import fetch
from .module_core import ModuleCore
from .module_synthesis import ModuleSynthesis
from .module_simulation import ModuleSimulation
from .module_content import ModuleContent
from .module_altera import ModuleAltera
from .mod.core import ModuleCore
from .mod.synthesis import ModuleSynthesis
from .mod.simulation import ModuleSimulation
from .mod.content import ModuleContent
from .mod.altera import ModuleAltera
class Module(ModuleCore, ModuleSynthesis, ModuleSimulation, ModuleContent, ModuleAltera):
......@@ -155,8 +155,9 @@ class Module(ModuleCore, ModuleSynthesis, ModuleSimulation, ModuleContent, Modul
break
def process_manifest(self):
super(Module, self).process_manifest()
logging.debug("Process manifest at: " + os.path.dirname(self.path))
super(Module, self).process_manifest()
def parse_manifest(self):
"""
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment