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Commit 35cb5526 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Improve coding style for all the tools

parent 2aee04b8
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Showing with 494 additions and 353 deletions
hdlmake/tools/active_hdl.py
View file @ 35cb5526
......@@ -21,13 +21,14 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
import string
"""Module providing support for Aldec Active-HDL simulator"""
from hdlmake.action import ActionMakefile
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile
class ToolActiveHDL(ActionMakefile):
"""Class providing the interface to control an Active-HDL simulation"""
TOOL_INFO = {
'name': 'Aldec Active-HDL',
......@@ -40,11 +41,14 @@ class ToolActiveHDL(ActionMakefile):
def __init__(self):
super(ToolActiveHDL, self).__init__()
def detect_version(self, path):
"""Get the version from the Aldec-HDL binary program"""
pass
def _print_clean(self, top_module):
"""Print the Makefile clean target for Aldec Active-HDL simulator"""
self.writeln("""\
#target for cleaning all intermediate stuff
clean:
......@@ -57,41 +61,36 @@ mrproper: clean
def _print_sim_compilation(self, fileset, top_module):
# TODO: ??
"""Print Makefile compilation target for Aldec Active-HDL simulator"""
self.writeln("simulation:")
self.writeln(
"\t\techo \"# Active-HDL command file, generated by HDLMake\" > run.command")
self.writeln("\t\techo \"# Active-HDL command file,"
" generated by HDLMake\" > run.command")
self.writeln()
self.writeln(
"\t\techo \"# Create library and set as default target\" >> run.command")
self.writeln("\t\techo \"# Create library and set as"
" default target\" >> run.command")
self.writeln("\t\techo \"alib work\" >> run.command")
self.writeln("\t\techo \"set worklib work\" >> run.command")
self.writeln()
self.writeln(
"\t\techo \"# Compiling HDL source files\" >> run.command")
for vl in fileset.filter(VerilogFile):
for vl_file in fileset.filter(VerilogFile):
self.writeln(
"\t\techo \"alog " +
vl.rel_path(
vl_file.rel_path(
) +
"\" >> run.command")
for sv in fileset.filter(SVFile):
for sv_file in fileset.filter(SVFile):
self.writeln(
"\t\techo \"alog " +
sv.rel_path(
sv_file.rel_path(
) +
"\" >> run.command")
for vhdl in fileset.filter(VHDLFile):
for vhdl_file in fileset.filter(VHDLFile):
self.writeln(
"\t\techo \"acom " +
vhdl.rel_path(
vhdl_file.rel_path(
) +
"\" >> run.command")
self.writeln()
self.writeln("\t\tvsimsa -do run.command")
hdlmake/tools/diamond.py
View file @ 35cb5526
......@@ -21,10 +21,11 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for Lattice Diamond IDE"""
import subprocess
import sys
import os
import logging
import string
from hdlmake.action import ActionMakefile
......@@ -34,6 +35,7 @@ DIAMOND_STANDARD_LIBS = ['ieee', 'std']
class ToolDiamond(ActionMakefile):
"""Class providing the interface for Lattice Diamond synthesis"""
TOOL_INFO = {
'name': 'Diamond',
......@@ -46,11 +48,17 @@ class ToolDiamond(ActionMakefile):
def __init__(self):
super(ToolDiamond, self).__init__()
self.files = []
self.filename = None
self.header = None
self.tclname = 'temporal.tcl'
def detect_version(self, path):
"""Get version from the Lattice Diamond program"""
return 'unknown'
def generate_synthesis_makefile(self, top_mod, tool_path):
"""Generate a synthesis Makefile for a Lattice Diamond project"""
makefile_tmplt = string.Template("""PROJECT := ${project_name}
DIAMOND_CRAP := \
$$(PROJECT)1.sty \
......@@ -108,17 +116,15 @@ mrproper:
syn_post_cmd=syn_post_cmd,
diamondc_path=os.path.join(tool_path, bin_name))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
for file_aux in top_mod.incl_makefiles:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.files = []
def generate_synthesis_project(self, update=False, tool_version='',
top_mod=None, fileset=None):
"""Create project for Lattice Diamond synthesis"""
self.filename = top_mod.manifest_dict["syn_project"]
self.header = None
self.tclname = 'temporal.tcl'
if update is True:
self.update_project()
else:
......@@ -131,26 +137,28 @@ mrproper:
self.execute()
def emit(self, update=False):
f = open(self.tclname, "w")
f.write(self.header + '\n')
f.write(self.__emit_files(update=update))
f.write('prj_project save\n')
f.write('prj_project close\n')
f.close()
"""Create a TCL file to feed Lattice Diamond command interpreter"""
file_aux = open(self.tclname, "w")
file_aux.write(self.header + '\n')
file_aux.write(self.__emit_files(update=update))
file_aux.write('prj_project save\n')
file_aux.write('prj_project close\n')
file_aux.close()
def execute(self):
"""Feed the TCL file to the Lattice Diamond command interpreter"""
# The binary name for Diamond is different in Linux and Windows
if sys.platform == 'cygwin':
tmp = 'pnmainc {0}'
else:
tmp = 'diamondc {0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
process_aux = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
# But do not wait till diamond finish, start displaying output
# immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() is not None:
out = process_aux.stderr.read(1)
if out == '' and process_aux.poll() is not None:
break
if out != '':
sys.stdout.write(out)
......@@ -158,39 +166,53 @@ mrproper:
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
"""Add files to the inner fileset"""
for file_aux in fileset:
self.files.append(file_aux)
def create_project(self,
syn_device,
syn_grade,
syn_package,
syn_top):
tmp = 'prj_project new -name {0} -impl {0} -dev {1} -synthesis \"synplify\"'
"""Create an empty Lattice Diamond project"""
tmp = ('prj_project new -name {0} -impl {0}'
' -dev {1} -synthesis \"synplify\"')
target = syn_device + syn_grade + syn_package
self.header = tmp.format(self.filename, target.upper())
def update_project(self):
"""Create an empty Lattice Diamond project"""
tmp = 'prj_project open \"{0}\"'
self.header = tmp.format(self.filename + '.ldf')
def __emit_files(self, update=False):
"""Emit files required for building the Lattice Diamond project"""
tmp = 'prj_src {0} \"{1}\"'
ret = []
for f in self.files:
for file_aux in self.files:
line = ''
if isinstance(f, VHDLFile) or isinstance(f, VerilogFile) or isinstance(f, SVFile) or isinstance(f, EDFFile):
if (isinstance(file_aux, VHDLFile) or
isinstance(file_aux, VerilogFile) or
isinstance(file_aux, SVFile) or
isinstance(file_aux, EDFFile)):
if update:
line = line + '\n' + tmp.format('remove', f.rel_path())
line = line + '\n' + tmp.format('add', f.rel_path())
elif isinstance(f, LPFFile):
line = line + '\n' + tmp.format('remove',
file_aux.rel_path())
line = line + '\n' + tmp.format('add',
file_aux.rel_path())
elif isinstance(file_aux, LPFFile):
if update:
line = line + '\n' + \
tmp.format('enable', self.filename + '.lpf')
line = line + '\n' + tmp.format('remove', f.rel_path())
line = line + '\n' + tmp.format('add -exclude', f.rel_path())
line = line + '\n' + tmp.format('enable', f.rel_path())
line = line + '\n' + tmp.format('remove',
file_aux.rel_path())
line = line + '\n' + tmp.format('add -exclude',
file_aux.rel_path())
line = line + '\n' + tmp.format('enable',
file_aux.rel_path())
else:
continue
ret.append(line)
return ('\n'.join(ret)) + '\n'
hdlmake/tools/ghdl.py
View file @ 35cb5526
......@@ -21,6 +21,8 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for GHDL simulator"""
import string
from hdlmake.action import ActionMakefile
from hdlmake.srcfile import VHDLFile
......@@ -28,6 +30,7 @@ from hdlmake.srcfile import VHDLFile
GHDL_STANDARD_LIBS = ['ieee', 'std']
class ToolGHDL(ActionMakefile):
"""Class providing the interface for Lattice Diamond synthesis"""
TOOL_INFO = {
'name': 'GHDL',
......@@ -41,10 +44,12 @@ class ToolGHDL(ActionMakefile):
super(ToolGHDL, self).__init__()
def detect_version(self, path):
"""Get tool version for GHDL"""
pass
def _print_sim_options(self, top_module):
"""Print the GHDL options to the Makefile"""
if top_module.manifest_dict["ghdl_opt"]:
ghdl_opt = top_module.manifest_dict["ghdl_opt"]
else:
......@@ -56,6 +61,7 @@ class ToolGHDL(ActionMakefile):
def _print_clean(self, top_module):
"""Print the Makefile clean target for GHDL"""
self.writeln("""\
#target for cleaning all intermediate stuff
clean:
......@@ -68,7 +74,7 @@ mrproper: clean
def _print_sim_compilation(self, fileset, top_module):
# TODO: vhdl87 vs vhdl97 options
"""Print the GDHL simulation compilation target"""
self.writeln("simulation:")
self.writeln("\t\t# Analyze sources")
for vhdl in fileset.filter(VHDLFile):
......
hdlmake/tools/isim.py
View file @ 35cb5526
This diff is collapsed.
hdlmake/tools/iverilog.py
View file @ 35cb5526
......@@ -21,11 +21,10 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for IVerilog (Icarus Verilog) simulator"""
from subprocess import Popen, PIPE
import string
import os
import platform
import logging
from hdlmake.util import path as path_mod
from hdlmake.action import ActionMakefile
......@@ -40,6 +39,7 @@ IVERILOG_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
class ToolIVerilog(ActionMakefile):
"""Class providing the interface for Icarus Verilog simulator"""
TOOL_INFO = {
'name': 'Icarus Verilog',
......@@ -53,6 +53,7 @@ class ToolIVerilog(ActionMakefile):
super(ToolIVerilog, self).__init__()
def detect_version(self, path):
"""Get version from Icarus Verilog program"""
is_windows = path_mod.check_windows()
iverilog = Popen("iverilog -v 2>/dev/null| awk '{if(NR==1) print $4}'",
shell=True,
......@@ -63,30 +64,30 @@ class ToolIVerilog(ActionMakefile):
return version
def _print_sim_compilation(self, fileset, top_module):
"""Generate compile simulation Makefile target for IVerilog"""
self.writeln("simulation:")
self.writeln(
"\t\techo \"# IVerilog command file, generated by HDLMake\" > run.command")
self.writeln("\t\techo \"# IVerilog command file,"
" generated by HDLMake\" > run.command")
for inc in top_module.get_include_dirs_list():
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
for vl in fileset.filter(VerilogFile):
self.writeln("\t\techo \"" + vl.rel_path() + "\" >> run.command")
for vlog in fileset.filter(VerilogFile):
self.writeln("\t\techo \"" + vlog.rel_path() + "\" >> run.command")
for vhdl in fileset.filter(VHDLFile):
self.writeln("\t\techo \"" + vhdl.rel_path() + "\" >> run.command")
for sv in fileset.filter(SVFile):
self.writeln("\t\techo \"" + sv.rel_path() + "\" >> run.command")
self.writeln("""
\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE) -o $(TOP_MODULE).vvp -c run.command
for svlog in fileset.filter(SVFile):
self.writeln("\t\techo \"" + svlog.rel_path() + "\" >> run.command")
""")
self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command")
def _print_sim_options(self, top_module):
"""Print the IVerilog options to the Makefile"""
if top_module.manifest_dict["iverilog_opt"]:
iverilog_opt = top_module.manifest_dict["iverilog_opt"]
else:
......@@ -98,6 +99,7 @@ class ToolIVerilog(ActionMakefile):
def _print_clean(self, top_module):
"""Print the Makefile clean target for Icarus Verilog"""
self.writeln("""\
#target for cleaning all intermediate stuff
clean:
......
hdlmake/tools/libero.py
View file @ 35cb5526
......@@ -21,11 +21,12 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for Microsemi Libero IDE synthesis"""
import subprocess
import sys
import os
import string
import logging
from hdlmake.action import ActionMakefile
from hdlmake.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
......@@ -35,6 +36,7 @@ LIBERO_STANDARD_LIBS = ['ieee', 'std']
class ToolLibero(ActionMakefile):
"""Class providing the interface for Microsemi Libero IDE synthesis"""
TOOL_INFO = {
'name': 'Libero',
......@@ -47,11 +49,21 @@ class ToolLibero(ActionMakefile):
def __init__(self):
super(ToolLibero, self).__init__()
self.files = []
self.filename = None
self.syn_device = None
self.syn_grade = None
self.syn_package = None
self.syn_top = None
self.header = None
self.tclname = 'temporal.tcl'
def detect_version(self, path):
"""Get version for Microsemi Libero IDE synthesis"""
return 'unknown'
def generate_synthesis_makefile(self, top_mod, tool_path):
"""Generate the synthesis Makefile for Microsemi Libero IDE"""
makefile_tmplt = string.Template("""PROJECT := ${project_name}
LIBERO_CRAP := \
run.tcl
......@@ -105,21 +117,19 @@ mrproper:
syn_post_cmd=syn_post_cmd,
libero_sh_path=os.path.join(tool_path, "libero"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
for file_aux in top_mod.incl_makefiles:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.files = []
"""Create a Microsemi Libero IDE synthesis project"""
self.filename = top_mod.manifest_dict["syn_project"]
self.syn_device = top_mod.manifest_dict["syn_device"]
self.syn_grade = top_mod.manifest_dict["syn_grade"]
self.syn_package = top_mod.manifest_dict["syn_package"]
self.syn_top = top_mod.manifest_dict["syn_top"]
self.header = None
self.tclname = 'temporal.tcl'
if update is True:
self.update_project()
......@@ -130,22 +140,24 @@ mrproper:
self.execute()
def emit(self, update=False):
f = open(self.tclname, "w")
f.write(self.header + '\n')
f.write(self.__emit_files(update=update))
f.write('save_project\n')
f.write('close_project\n')
f.close()
"""Emit the TCL file that is required to generate the project"""
file_aux = open(self.tclname, "w")
file_aux.write(self.header + '\n')
file_aux.write(self.__emit_files(update=update))
file_aux.write('save_project\n')
file_aux.write('close_project\n')
file_aux.close()
def execute(self):
"""Feed the TCL script to Microsemi Libero IDE command interpreter"""
tmp = 'libero SCRIPT:{0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
process_aux = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
# But do not wait till Libero finish, start displaying output
# immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() is not None:
out = process_aux.stderr.read(1)
if out == '' and process_aux.poll() is not None:
break
if out != '':
sys.stdout.write(out)
......@@ -153,11 +165,15 @@ mrproper:
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
"""Add files to the inner fileset"""
for file_aux in fileset:
self.files.append(file_aux)
def create_project(self):
tmp = 'new_project -location {{./{0}}} -name {{{0}}} -hdl {{VHDL}} -family {{ProASIC3}} -die {{{1}}} -package {{{2}}} -speed {{{3}}} -die_voltage {{1.5}}'
"""Create a new Microsemi Libero IDE project"""
tmp = ('new_project -location {{./{0}}} -name {{{0}}} -hdl'
' {{VHDL}} -family {{ProASIC3}} -die {{{1}}} -package'
' {{{2}}} -speed {{{3}}} -die_voltage {{1.5}}')
self.header = tmp.format(
self.filename,
self.syn_device.upper(),
......@@ -165,26 +181,30 @@ mrproper:
self.syn_grade)
def update_project(self):
"""Update an existing Microsemi Libero IDE project"""
tmp = 'open_project -file {{{0}/{0}.prjx}}'
self.header = tmp.format(self.filename)
def __emit_files(self, update=False):
"""Emit the supported HDL files that need to be added to the project"""
link_string = 'create_links {0} {{{1}}}'
enable_string = 'organize_tool_files -tool {{{0}}} -file {{{1}}} -module {{{2}::work}} -input_type {{constraint}}'
enable_string = ('organize_tool_files -tool {{{0}}} -file {{{1}}}'
' -module {{{2}::work}} -input_type {{constraint}}')
synthesis_constraints = []
compilation_constraints = []
ret = []
# First stage: linking files
for f in self.files:
if isinstance(f, VHDLFile) or isinstance(f, VerilogFile):
line = link_string.format('-hdl_source', f.rel_path())
elif isinstance(f, SDCFile):
line = link_string.format('-sdc', f.rel_path())
synthesis_constraints.append(f)
compilation_constraints.append(f)
elif isinstance(f, PDCFile):
line = link_string.format('-pdc', f.rel_path())
compilation_constraints.append(f)
for file_aux in self.files:
if (isinstance(file_aux, VHDLFile) or
isinstance(file_aux, VerilogFile)):
line = link_string.format('-hdl_source', file_aux.rel_path())
elif isinstance(file_aux, SDCFile):
line = link_string.format('-sdc', file_aux.rel_path())
synthesis_constraints.append(file_aux)
compilation_constraints.append(file_aux)
elif isinstance(file_aux, PDCFile):
line = link_string.format('-pdc', file_aux.rel_path())
compilation_constraints.append(file_aux)
else:
continue
ret.append(line)
......@@ -192,8 +212,8 @@ mrproper:
# module needs to be present!)
if synthesis_constraints:
line = 'organize_tool_files -tool {SYNTHESIZE} '
for f in synthesis_constraints:
line = line + '-file {' + f.rel_path() + '} '
for file_aux in synthesis_constraints:
line = line + '-file {' + file_aux.rel_path() + '} '
line = line + \
'-module {' + self.syn_top + '::work} -input_type {constraint}'
ret.append(line)
......@@ -201,8 +221,8 @@ mrproper:
# module needs to be present!)
if compilation_constraints:
line = 'organize_tool_files -tool {COMPILE} '
for f in compilation_constraints:
line = line + '-file {' + f.rel_path() + '} '
for file_aux in compilation_constraints:
line = line + '-file {' + file_aux.rel_path() + '} '
line = line + \
'-module {' + self.syn_top + '::work} -input_type {constraint}'
ret.append(line)
......
hdlmake/tools/modelsim.py
View file @ 35cb5526
......@@ -21,18 +21,19 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for Mentor Modelsim simulation"""
from __future__ import print_function
import xml.dom.minidom
import os
from .sim_makefile_support import VsimMakefileWriter
XmlImpl = xml.dom.minidom.getDOMImplementation()
MODELSIM_STANDARD_LIBS = ['ieee', 'std', 'altera_mf']
class ToolModelsim(VsimMakefileWriter):
"""Class providing the interface for Mentor Modelsim simulator"""
TOOL_INFO = {
'name': 'Modelsim',
......@@ -55,10 +56,12 @@ class ToolModelsim(VsimMakefileWriter):
["./modelsim.ini", "transcript", "*.vcd", "*.wlf"])
def detect_version(self, path):
"""Get version from the Mentor Modelsim program"""
pass
def _print_sim_options(self, top_module):
"""Print the Modelsim options to the Makefile"""
if top_module.pool.env["modelsim_path"]:
modelsim_ini_path = os.path.join(
top_module.pool.env["modelsim_path"],
......
hdlmake/tools/planahead.py
View file @ 35cb5526
......@@ -21,11 +21,12 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for Xilinx PlanAhead synthesis"""
import subprocess
import sys
import os
import string
from string import Template
import logging
from hdlmake.action import ActionMakefile
......@@ -37,6 +38,8 @@ PLANAHEAD_STANDARD_LIBS = ['ieee', 'std']
class ToolPlanAhead(ActionMakefile):
"""Class providing the interface for Xilinx PlanAhead synthesis"""
TOOL_INFO = {
'name': 'PlanAhead',
......@@ -49,11 +52,18 @@ class ToolPlanAhead(ActionMakefile):
def __init__(self):
super(ToolPlanAhead, self).__init__()
self.properties = []
self.files = []
self.filename = None
self.header = None
self.tclname = 'temporal.tcl'
def detect_version(self, path):
"""Get the Xilinx PlanAhead program version"""
return 'unknown'
def generate_synthesis_makefile(self, top_mod, tool_path):
"""Generate a synthesis Makefile for Xilinx PlanAhead"""
makefile_tmplt = string.Template("""PROJECT := ${project_name}
PLANAHEAD_CRAP := \
planAhead_* \
......@@ -115,18 +125,15 @@ mrproper:
syn_post_cmd=syn_post_cmd,
planahead_sh_path=os.path.join(tool_path, "planAhead"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
for file_aux in top_mod.incl_makefiles:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.properties = []
self.files = []
"""Create a Xilinx PlanAhead project"""
self.filename = top_mod.manifest_dict["syn_project"]
self.header = None
self.tclname = 'temporal.tcl'
if update is True:
logging.info("Existing project detected: updating...")
self.update_project()
......@@ -144,25 +151,27 @@ mrproper:
logging.info("PlanAhead project file generated.")
def emit(self):
f = open(self.tclname, "w")
f.write(self.header + '\n')
for p in self.properties:
f.write(p.emit() + '\n')
f.write(self.__emit_files())
f.write('update_compile_order -fileset sources_1\n')
f.write('update_compile_order -fileset sim_1\n')
f.write('exit\n')
f.close()
"""Emit the TCL file that will be used to generate the project"""
file_aux = open(self.tclname, "w")
file_aux.write(self.header + '\n')
for prop in self.properties:
file_aux.write(prop.emit() + '\n')
file_aux.write(self.__emit_files())
file_aux.write('update_compile_order -fileset sources_1\n')
file_aux.write('update_compile_order -fileset sim_1\n')
file_aux.write('exit\n')
file_aux.close()
def execute(self):
"""Source the TCL file to the Xilinx PlanAhead interpreter"""
tmp = 'planAhead -mode tcl -source {0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
process_aux = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
# But do not wait till planahead finish, start displaying output
# immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() is not None:
out = process_aux.stderr.read(1)
if out == '' and process_aux.poll() is not None:
break
if out != '':
sys.stdout.write(out)
......@@ -170,10 +179,12 @@ mrproper:
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
"""Add files to the inner fileset"""
for file_aux in fileset:
self.files.append(file_aux)
def add_property(self, new_property):
"""Add a new Xilinx PlanAhead property to the defined set"""
self.properties.append(new_property)
def add_initial_properties(self,
......@@ -181,20 +192,21 @@ mrproper:
syn_grade,
syn_package,
syn_top):
PAPP = _PlanAheadProjectProperty
"""Add the initial properties to the Xilinx PlanAhead project"""
prop = _PlanAheadProjectProperty
self.add_property(
PAPP(
prop(
name='part',
value=syn_device +
syn_package +
syn_grade,
objects='current_project'))
self.add_property(
PAPP(name='target_language',
prop(name='target_language',
value='VHDL',
objects='current_project'))
self.add_property(
PAPP(
prop(
name='ng.output_hdl_format',
value='VHDL',
objects='get_filesets sim_1'))
......@@ -202,39 +214,50 @@ mrproper:
# self.add_property(PAPP(name='steps.bitgen.args.b', value='true',
# objects='get_runs impl_1'))
self.add_property(
PAPP(name='top',
prop(name='top',
value=syn_top,
objects='get_property srcset [current_run]'))
def create_project(self):
"""Create an empty Xilinx PlanAhead project"""
tmp = 'create_project {0} ./'
self.header = tmp.format(self.filename)
def update_project(self):
"""Update an existing Xilinx PlanAhead project"""
tmp = 'open_project ./{0}'
self.header = tmp.format(self.filename + '.ppr')
def __emit_properties(self):
"""Add to the project the different properties that have been defined"""
tmp = "set_property {0} {1} [{2}]"
ret = []
for p in self.properties:
line = tmp.format(p.name, p.value, p.objects)
for prop in self.properties:
line = tmp.format(prop.name, prop.value, prop.objects)
ret.append(line)
return ('\n'.join(ret)) + '\n'
def __emit_files(self):
"""Add to the project the different files defined in the design"""
tmp = "add_files -norecurse {0}"
ret = []
for f in self.files:
if isinstance(f, VHDLFile) or isinstance(f, VerilogFile) or isinstance(f, SVFile) or isinstance(f, UCFFile) or isinstance(f, NGCFile) or isinstance(f, XMPFile) or isinstance(f, XCOFile):
line = tmp.format(f.rel_path())
for file_aux in self.files:
if (isinstance(file_aux, VHDLFile) or
isinstance(file_aux, VerilogFile) or
isinstance(file_aux, SVFile) or
isinstance(file_aux, UCFFile) or
isinstance(file_aux, NGCFile) or
isinstance(file_aux, XMPFile) or
isinstance(file_aux, XCOFile)):
line = tmp.format(file_aux.rel_path())
else:
continue
ret.append(line)
return ('\n'.join(ret)) + '\n'
class _PlanAheadProjectProperty:
class _PlanAheadProjectProperty(object):
"""Class that serves as a convenient storage for PlanAhead properties"""
def __init__(self, name=None, value=None, objects=None):
self.name = name
......@@ -242,6 +265,7 @@ class _PlanAheadProjectProperty:
self.objects = objects
def emit(self):
"""Emit the property defined by the class inner parameters"""
tmp = "set_property {0} {1} [{2}]"
line = tmp.format(self.name, self.value, self.objects)
return(line)
return line
hdlmake/tools/quartus.py
View file @ 35cb5526
This diff is collapsed.
hdlmake/tools/riviera.py
View file @ 35cb5526
......@@ -22,6 +22,8 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for Aldec Riviera-PRO simulation"""
from __future__ import print_function
from .sim_makefile_support import VsimMakefileWriter
......@@ -61,6 +63,7 @@ RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES)
class ToolRiviera(VsimMakefileWriter):
"""Class providing the interface for Aldec Riviera-PRO simulator"""
TOOL_INFO = {
'name': 'Riviera',
......@@ -76,5 +79,6 @@ class ToolRiviera(VsimMakefileWriter):
self.additional_clean.extend(["*.asdb", "*.vcd", ])
def detect_version(self, path):
"""Get version from Aldec Riviera-PRO binary program"""
pass
hdlmake/tools/sim_makefile_support.py
View file @ 35cb5526
......@@ -21,11 +21,14 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing common stuff for Modelsim, Vsim... like simulators"""
import os
import platform
import string
from hdlmake.action import ActionMakefile
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
class VsimMakefileWriter(ActionMakefile):
......@@ -62,8 +65,10 @@ class VsimMakefileWriter(ActionMakefile):
def _print_sim_options(self, top_module):
"""Print the vsim options to the Makefile"""
self.vlog_flags.append(
self.__get_rid_of_vsim_incdirs(top_module.manifest_dict["vlog_opt"]))
self.__get_rid_of_vsim_incdirs(
top_module.manifest_dict["vlog_opt"]))
self.vcom_flags.append(top_module.manifest_dict["vcom_opt"])
self.vmap_flags.append(top_module.manifest_dict["vmap_opt"])
self.vsim_flags.append(top_module.manifest_dict["vsim_opt"])
......@@ -78,6 +83,7 @@ class VsimMakefileWriter(ActionMakefile):
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
def _print_clean(self, top_module):
"""Print the Makefile clean target"""
if platform.system() == 'Windows':
del_command = "rm -rf"
else:
......@@ -91,11 +97,9 @@ class VsimMakefileWriter(ActionMakefile):
def _print_sim_compilation(self, fileset, top_module):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
"""
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
if platform.system() == 'Windows':
del_command = "rm -rf"
......@@ -137,74 +141,68 @@ class VsimMakefileWriter(ActionMakefile):
self.write(lib + slash_char + "." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)"
self.write(' '.join(["\t(vlib", lib, "&&", vmap_command,
lib, "&&", "touch", lib + slash_char + "." + lib, ")"]))
lib, "&&", "touch", lib + slash_char + "." + lib, ")"]))
self.write(' '.join(["||", del_command, lib, "\n"]))
self.write('\n\n')
# rules for all _primary.dat files for sv
for vl in fileset.filter(VerilogFile):
self.write(
"%s: %s" % (os.path.join(vl.library, vl.purename, ".%s_%s" % (vl.purename, vl.extension())),
vl.rel_path())
)
for vlog in fileset.filter(VerilogFile):
self.write("%s: %s" % (os.path.join(vlog.library, vlog.purename,
".%s_%s" % (vlog.purename, vlog.extension())), vlog.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile in vl.depends_on if dfile is not vl]:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
for dep_file in [dfile for dfile
in vlog.depends_on if dfile is not vlog]:
if dep_file in fileset:
name = dep_file.purename
extension = dep_file.extension()
self.write(
" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" %
(name, extension)))
self.write(" \\\n" + os.path.join(dep_file.library,
name, ".%s_%s" % (name, extension)))
else: # the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
#
# self.write("\t\tvlog -work "+vl.library)
# self.write("\t\tvlog -work "+vlog.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
# self.write(" -sv ")
# incdir = "+incdir+"
# incdir += '+'.join(vl.include_dirs)
# incdir += '+'.join(vlog.include_dirs)
# incdir += " "
# self.write(incdir)
# self.writeln(vl.vlog_opt+" $<")
#
compile_template = string.Template(
"\t\tvlog -work ${library} $$(VLOG_FLAGS) ${sv_option} $${INCLUDE_DIRS} $$<")
compile_line = compile_template.substitute(library=vl.library,
sv_option="-sv" if isinstance(vl, SVFile) else "")
# self.writeln(vlog.vlog_opt+" $<")
compile_template = string.Template("\t\tvlog -work ${library}"
" $$(VLOG_FLAGS) ${sv_option} $${INCLUDE_DIRS} $$<")
compile_line = compile_template.substitute(
library=vlog.library, sv_option="-sv"
if isinstance(vlog, SVFile) else "")
self.writeln(compile_line)
self.write("\t\t@" + mkdir_command + " $(dir $@)")
self.writeln(" && touch $@ \n\n")
self.write("\n")
self.writeln()
# list rules for all _primary.dat files for vhdl
for vhdl in fileset.filter(VHDLFile):
lib = vhdl.library
purename = vhdl.purename
# each .dat depends on corresponding .vhd file
self.write(
"%s: %s" % (os.path.join(lib, purename, "." + purename + "_" + vhdl.extension()),
vhdl.rel_path())
)
self.write("%s: %s" % (os.path.join(lib, purename, "." +
purename + "_" + vhdl.extension()), vhdl.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile in vhdl.depends_on if dfile is not vhdl]:
if dep_file in fileset: # the dep_file is compiled -> we depend on marker file
for dep_file in [dfile for dfile in vhdl.depends_on
if dfile is not vhdl]:
if dep_file in fileset:
name = dep_file.purename
extension = dep_file.extension()
self.write(
" \\\n" + os.path.join(dep_file.library, name, ".%s_%s" %
(name, extension)))
else: # the file is included -> we depend directly on the file
self.write(" \\\n" + os.path.join(dep_file.library,
name, ".%s_%s" % (name, extension)))
else:
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln(
' '.join(["\t\tvcom $(VCOM_FLAGS)", vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@" + mkdir_command + " $(dir $@) && touch $@ \n")
self.writeln()
self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)",
vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@" + mkdir_command +
" $(dir $@) && touch $@ \n\n")
def __create_copy_rule(self, name, src):
"""Get a Makefile rule named name, which depends on src, copying it to
......@@ -219,11 +217,13 @@ class VsimMakefileWriter(ActionMakefile):
return rule
def __get_rid_of_vsim_incdirs(self, vlog_opt=""):
"""Parse the VLOG options and purge the included dirs"""
if not vlog_opt:
vlog_opt = ""
vlogs = vlog_opt.split(' ')
ret = []
for v in vlogs:
if not v.startswith("+incdir+"):
ret.append(v)
for vlog_aux in vlogs:
if not vlog_aux.startswith("+incdir+"):
ret.append(vlog_aux)
return ' '.join(ret)
hdlmake/tools/vivado.py
View file @ 35cb5526
......@@ -21,6 +21,8 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing support for Xilinx Vivado synthesis"""
import subprocess
import sys
import os
......@@ -36,6 +38,7 @@ VIVADO_STANDARD_LIBS = ['ieee', 'std']
class ToolVivado(ActionMakefile):
"""Class providing the interface for Xilinx Vivado synthesis"""
TOOL_INFO = {
'name': 'vivado',
......@@ -50,11 +53,18 @@ class ToolVivado(ActionMakefile):
def __init__(self):
super(ToolVivado, self).__init__()
self.properties = []
self.files = []
self.filename = None
self.header = None
self.tclname = 'temporal.tcl'
def detect_version(self, path):
"""Get version from Xilinx Vivado binary program"""
return 'unknown'
def generate_synthesis_makefile(self, top_mod, tool_path):
"""Generate a synthesis Makefile for Xilinx Vivado"""
makefile_tmplt = string.Template("""PROJECT := ${project_name}
VIVADO_CRAP := \
run.tcl
......@@ -114,17 +124,14 @@ mrproper:
syn_post_cmd=syn_post_cmd,
vivado_sh_path=os.path.join(tool_path, "vivado"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
for file_aux in top_mod.incl_makefiles:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.properties = []
self.files = []
"""Generate a Xilinx Vivado synthesis project"""
self.filename = top_mod.manifest_dict["syn_project"]
self.header = None
self.tclname = 'temporal.tcl'
if update is True:
logging.info("Existing project detected: updating...")
self.update_project()
......@@ -138,29 +145,30 @@ mrproper:
self.add_files(fileset)
self.emit()
self.execute()
logging.info("Vivado project file generated.")
def emit(self):
f = open(self.tclname, "w")
f.write(self.header + '\n')
for p in self.properties:
f.write(p.emit() + '\n')
f.write(self.__emit_files())
f.write('update_compile_order -fileset sources_1\n')
f.write('update_compile_order -fileset sim_1\n')
f.write('exit\n')
f.close()
"""Emit the TCL file that will be feeded to the Vivado interpreter"""
file_aux = open(self.tclname, "w")
file_aux.write(self.header + '\n')
for prop in self.properties:
file_aux.write(prop.emit() + '\n')
file_aux.write(self.__emit_files())
file_aux.write('update_compile_order -fileset sources_1\n')
file_aux.write('update_compile_order -fileset sim_1\n')
file_aux.write('exit\n')
file_aux.close()
def execute(self):
"""Feed the TCL file to the Xilinx Vivado command line interpreter"""
tmp = 'vivado -mode tcl -source {0}'
cmd = tmp.format(self.tclname)
p = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
process_aux = subprocess.Popen(cmd, shell=True, stderr=subprocess.PIPE)
# But do not wait till Vivado finish, start displaying output
# immediately ##
while True:
out = p.stderr.read(1)
if out == '' and p.poll() is not None:
out = process_aux.stderr.read(1)
if out == '' and process_aux.poll() is not None:
break
if out != '':
sys.stdout.write(out)
......@@ -168,20 +176,20 @@ mrproper:
os.remove(self.tclname)
def add_files(self, fileset):
for f in fileset:
self.files.append(f)
"""Add files to the inner fileset"""
for file_aux in fileset:
self.files.append(file_aux)
def add_property(self, new_property):
"""Add a new propertiy to the Xilinx Vivado project"""
self.properties.append(new_property)
def add_initial_properties(self,
syn_device,
syn_grade,
syn_package,
syn_top):
PAPP = _VivadoProjectProperty
def add_initial_properties(self, syn_device, syn_grade,
syn_package, syn_top):
"""Add initial properties to the Xilinx Vivado project"""
vivado_prop = _VivadoProjectProperty
self.add_property(
PAPP(
vivado_prop(
name='part',
value=syn_device +
syn_package +
......@@ -191,51 +199,64 @@ mrproper:
# value='em.avnet.com:microzed_7010:part0:1.0',
# objects='current_project'))
self.add_property(
PAPP(name='target_language',
value='VHDL',
objects='current_project'))
vivado_prop(name='target_language',
value='VHDL',
objects='current_project'))
# self.add_property(PAPP(name='ng.output_hdl_format', value='VHDL', objects='get_filesets sim_1'))
# self.add_property(PAPP(name='ng.output_hdl_format',
# value='VHDL', objects='get_filesets sim_1'))
# the bitgen b arg generates a raw configuration bitstream
# self.add_property(PAPP(name='steps.bitgen.args.b', value='true',
# objects='get_runs impl_1'))
self.add_property(
PAPP(name='top',
value=syn_top,
objects='get_property srcset [current_run]'))
vivado_prop(name='top',
value=syn_top,
objects='get_property srcset [current_run]'))
def create_project(self):
"""Create an empty Xilinx Vivado project"""
tmp = 'create_project {0} ./'
self.header = tmp.format(self.filename)
def update_project(self):
"""Update an existing Xilinx Vivado project"""
tmp = 'open_project ./{0}'
self.header = tmp.format(self.filename + '.xpr')
def __emit_properties(self):
"""Emit the properties to be added to the project"""
tmp = "set_property {0} {1} [{2}]"
ret = []
for p in self.properties:
line = tmp.format(p.name, p.value, p.objects)
for prop in self.properties:
line = tmp.format(prop.name, prop.value, prop.objects)
ret.append(line)
return ('\n'.join(ret)) + '\n'
def __emit_files(self):
"""Emit the design HDL files that must be added to the project"""
tmp = "add_files -norecurse {0}"
tcl = "source {0}"
ret = []
for f in self.files:
if isinstance(f, VHDLFile) or isinstance(f, VerilogFile) or isinstance(f, SVFile) or isinstance(f, UCFFile) or isinstance(f, NGCFile) or isinstance(f, XMPFile) or isinstance(f, XCOFile) or isinstance(f, BDFile):
line = tmp.format(f.rel_path())
elif isinstance(f, TCLFile):
line = tcl.format(f.rel_path())
for file_aux in self.files:
if (isinstance(file_aux, VHDLFile) or
isinstance(file_aux, VerilogFile) or
isinstance(file_aux, SVFile) or
isinstance(file_aux, UCFFile) or
isinstance(file_aux, NGCFile) or
isinstance(file_aux, XMPFile) or
isinstance(file_aux, XCOFile) or
isinstance(file_aux, BDFile)):
line = tmp.format(file_aux.rel_path())
elif isinstance(file_aux, TCLFile):
line = tcl.format(file_aux.rel_path())
else:
continue
ret.append(line)
return ('\n'.join(ret)) + '\n'
class _VivadoProjectProperty:
class _VivadoProjectProperty(object):
"""Class providing an storage for Xilinx Vivado properties"""
def __init__(self, name=None, value=None, objects=None):
self.name = name
......@@ -243,6 +264,8 @@ class _VivadoProjectProperty:
self.objects = objects
def emit(self):
"""Emit the Xilinx Vivado property the class instance contains"""
tmp = "set_property {0} {1} [{2}]"
line = tmp.format(self.name, self.value, self.objects)
return(line)
return line
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