As an advanced example for Xilinx Vivado, we have chosen the Beam Position Monitor (BPM) design from the Beam Diagnostics group of the Brazilian Synchrotron Light Laboratory (LNLS) for the **AMC FMC Carrier (AFC)**. Equiped in **Xilinx Artix-7** FPGA, it allows to connect clock source to any clock input.
In the following instructions, we will see how easy is to build the bitstream from the command line (**tested on both Windows and Linux hosts**).
We start by cloning the repository and getting into the AFC reference design:
.. code-block:: bash
git clone https://github.com/lnls-dig/bpm-gw.git
cd bpm-gw/hdl/syn/afc_v3/vivado/dbe_bpm2/
Now, the Beam Position Monitor requires a series of HDL libraries that are provided under ``hdlmake`` format in both the CERN Open Hardware repository and GitHub. In this example, you have the option of fetching all of the dependencies for all of the reference designs provided in the downloaded source code by using the ``git submodule`` mechanism, this is:
.. code-block:: bash
git submodule init
git submodule update
Alternatively, if you only want to download the design submodule dependencies the design needs, we can use the ``hdlmake fetch``, but we will need to modify the ``bpm-gw/hdl/Manifest.py`` so that its new content is:
.. note:: In order to allow the use of IP-XACT IP Core libraries for Vivado, the ``fetcho`` variable in the ``Manifest.py`` hierarchy is not only used as the folder to store remote ``hdlmake`` modules, but it's automatically assigned as the value for the ``ip_repo_paths`` Vivado project property.
Once this is done, ``hdlmake`` will only clone the listed repositories in the ``fetchto`` folder and then will checkout the appropriated commits by previously interrogating the ``git submodule`` mechanism. In this example, doing
.. code-block:: bash
hdlmake fetch
Once we have all the dependencies, we can run ``hdlmake`` to automatically generate a synthesis ``Makefile``. Once we have done this, we can just run Make to automatically generate the bitstream:
.. code-block:: bash
hdlmake
make
This project makes use of **custom Xilinx Vivado properties** and **custom Python code**, so it is a very valuable example as a template for custom setups. Here, you can see a copy of the top ``Manifest.py`` contents for the BPM design:
@@ -1036,11 +1140,14 @@ Once we have all the dependencies, we can run ``hdlmake`` to automatically gener
.. code-block:: bash
hdlmake
make
It's important to know that this design relies on versioned Intel IP-Cores, so it will only work just out of the box with the appropriated Intel Quartus version (**WR PTP Core v4.0 requires Intel Quartus 16.0**).
If you want to use a different Intel Quartus version, you will need to fix the IP-Core versions. This is an example patch for **upgrading WR PTP Core v4.0 from Intel Quartus 16.0 to Intel Quartus 16.1**:
