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3eaa0599
Commit
3eaa0599
authored
Dec 05, 2019
by
Severin Haas
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Added test/example stuff for synthesis of IGLOO2 devices
parent
b2df73e8
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Manifest.py
tests/counter/syn/igloo2_libero/vhdl/Manifest.py
+15
-0
igloo2_top.pdc
tests/counter/top/igloo2/igloo2_top.pdc
+30
-0
igloo2_top.sdc
tests/counter/top/igloo2/igloo2_top.sdc
+24
-0
Manifest.py
tests/counter/top/igloo2/vhdl/Manifest.py
+9
-0
igloo2_top.vhd
tests/counter/top/igloo2/vhdl/igloo2_top.vhd
+55
-0
No files found.
tests/counter/syn/igloo2_libero/vhdl/Manifest.py
0 → 100644
View file @
3eaa0599
target
=
"microsemi"
syn_tool
=
"liberosoc"
action
=
"synthesis"
language
=
"vhdl"
syn_family
=
"IGLOO2"
syn_device
=
"M2GL060"
syn_grade
=
"-1"
syn_package
=
"484 FBGA"
syn_top
=
"igloo2_top"
syn_project
=
"demo"
modules
=
{
"local"
:
[
"../../../top/igloo2/vhdl"
],
}
tests/counter/top/igloo2/igloo2_top.pdc
0 → 100644
View file @
3eaa0599
# Microsemi Physical design constraints file
# Family: IGLOO2, Die: M2GL060, Package: 484 FBGA, Speed grade: -1
#
# IO banks setting
#
set_iobank Bank2 -vcci 3.3 -fixed yes
set_iobank Bank4 -vcci 3.3 -fixed no
set_iobank Bank5 -vcci 3.3 -fixed yes
set_iobank Bank6 -vcci 3.3 -fixed yes
set_iobank Bank9 -vcci 3.3 -fixed yes
#
# I/O constraints
#
set_io led_o\[0\] -iostd LVTTL -pinname G3 -fixed yes -direction OUTPUT
set_io led_o\[1\] -iostd LVTTL -pinname H3 -fixed yes -direction OUTPUT
set_io led_o\[2\] -iostd LVTTL -pinname H1 -fixed yes -direction OUTPUT
set_io led_o\[3\] -iostd LVTTL -pinname G1 -fixed yes -direction OUTPUT
set_io led_o\[4\] -iostd LVTTL -pinname H4 -fixed yes -direction OUTPUT
set_io led_o\[5\] -iostd LVTTL -pinname H5 -fixed yes -direction OUTPUT
set_io led_o\[6\] -iostd LVTTL -pinname H6 -fixed yes -direction OUTPUT
set_io led_o\[7\] -iostd LVTTL -pinname J1 -fixed yes -direction OUTPUT
set_io clear_i -iostd LVTTL -pinname B1 -fixed yes
set_io count_i -iostd LVTTL -pinname C1 -fixed yes
# 40MHz clock
set_io clock_i -iostd LVTTL -pinname J20 -fixed yes
tests/counter/top/igloo2/igloo2_top.sdc
0 → 100644
View file @
3eaa0599
# Top Level Design Parameters
# Clocks
create_clock -name {clock_i} -period 25 -waveform {0 12.5 } [ get_ports { clock_i } ]
# False Paths Between Clocks
# False Path Constraints
# Maximum Delay Constraints
# Multicycle Constraints
# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top
# Other Constraints
tests/counter/top/igloo2/vhdl/Manifest.py
0 → 100644
View file @
3eaa0599
files
=
[
"igloo2_top.vhd"
,
"../igloo2_top.pdc"
,
"../igloo2_top.sdc"
,
]
modules
=
{
"local"
:
[
"../../../modules/counter/vhdl"
],
}
tests/counter/top/igloo2/vhdl/igloo2_top.vhd
0 → 100644
View file @
3eaa0599
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, adopted for IGLOO2 M2GL060
-- Author : Javier D. Garcia-Lasheras, small changes by Severin Haas
-----------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
std_logic_unsigned
.
all
;
use
ieee
.
std_logic_arith
.
all
;
entity
igloo2_top
is
port
(
clear_i
:
in
std_logic
;
count_i
:
in
std_logic
;
clock_i
:
in
std_logic
;
led_o
:
out
std_logic_vector
(
7
downto
0
)
);
end
igloo2_top
;
-----------------------------------------------------------------------
architecture
structure
of
igloo2_top
is
component
counter
port
(
clock
:
in
std_logic
;
clear
:
in
std_logic
;
count
:
in
std_logic
;
Q
:
out
std_logic_vector
(
7
downto
0
)
);
end
component
;
signal
s_clock
:
std_logic
;
signal
s_clear
:
std_logic
;
signal
s_count
:
std_logic
;
signal
s_Q
:
std_logic_vector
(
7
downto
0
);
begin
U_counter
:
counter
port
map
(
clock
=>
s_clock
,
clear
=>
s_clear
,
count
=>
s_count
,
Q
=>
s_Q
);
s_clock
<=
clock_i
;
s_clear
<=
clear_i
;
s_count
<=
count_i
;
led_o
<=
s_Q
;
end
architecture
structure
;
----------------------------------------------------------------
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