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Hdlmake
Commit 47b3bddc authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Refactor how the tool_info is stored in their Classes

parent ef068159
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Showing with 187 additions and 207 deletions
hdlmake/action/simulation.py
View file @ 47b3bddc
......@@ -71,7 +71,7 @@ class ActionSimulation(
elif tool_name is "ghdl":
tool_object = ToolGHDL()
tool_info = tool_object.get_keys()
tool_info = tool_object.TOOL_INFO
if sys.platform == 'cygwin':
bin_name = tool_info['windows_bin']
else:
......
hdlmake/action/synthesis.py
View file @ 47b3bddc
......@@ -79,7 +79,7 @@ class ActionSynthesis(
self._check_synthesis_makefile()
tool_object = self._load_synthesis_tool()
tool_info = tool_object.get_keys()
tool_info = tool_object.TOOL_INFO
path_key = tool_info['id'] + '_path'
name = tool_info['name']
......@@ -202,7 +202,7 @@ end sdb_meta_pkg;""")
self._check_synthesis_project()
tool_object = self._load_synthesis_tool()
tool_info = tool_object.get_keys()
tool_info = tool_object.TOOL_INFO
path_key = tool_info['id'] + '_path'
version_key = tool_info['id'] + '_version'
name = tool_info['name']
......
hdlmake/env.py
View file @ 47b3bddc
......@@ -123,7 +123,7 @@ class Env(dict):
def check_tool(self, info_class):
tool_info = info_class.get_keys()
tool_info = info_class.TOOL_INFO
if sys.platform == 'cygwin':
bin_name = tool_info['windows_bin']
else:
......
hdlmake/tools/active_hdl.py
View file @ 47b3bddc
......@@ -28,21 +28,19 @@ from hdlmake.action import ActionMakefile
class ToolActiveHDL(ActionMakefile):
TOOL_INFO = {
'name': 'Aldec Active-HDL',
'id': 'aldec',
'windows_bin': 'vsimsa',
'linux_bin': None}
def __init__(self):
super(ToolActiveHDL, self).__init__()
def detect_version(self, path):
pass
def get_keys(self):
tool_info = {
'name': 'Aldec Active-HDL',
'id': 'aldec',
'windows_bin': 'vsimsa',
'linux_bin': None
}
return tool_info
def get_standard_libraries(self):
ALDEC_STANDARD_LIBS = ['ieee', 'std']
return ALDEC_STANDARD_LIBS
......
hdlmake/tools/diamond.py
View file @ 47b3bddc
......@@ -34,22 +34,19 @@ DIAMOND_STANDARD_LIBS = ['ieee', 'std']
class ToolDiamond(ActionMakefile):
TOOL_INFO = {
'name': 'Diamond',
'id': 'diamond',
'windows_bin': 'pnmainc',
'linux_bin': 'diamondc',
'project_ext': 'ldf'}
def __init__(self):
super(ToolDiamond, self).__init__()
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'Diamond',
'id': 'diamond',
'windows_bin': 'pnmainc',
'linux_bin': 'diamondc',
'project_ext': 'ldf'
}
return tool_info
def get_standard_libraries(self):
return DIAMOND_STANDARD_LIBS
......
hdlmake/tools/ghdl.py
View file @ 47b3bddc
......@@ -27,21 +27,18 @@ from hdlmake.action import ActionMakefile
class ToolGHDL(ActionMakefile):
TOOL_INFO = {
'name': 'GHDL',
'id': 'ghdl',
'windows_bin': 'ghdl',
'linux_bin': 'ghdl'}
def __init__(self):
super(ToolGHDL, self).__init__()
def detect_version(self, path):
pass
def get_keys(self):
tool_info = {
'name': 'GHDL',
'id': 'ghdl',
'windows_bin': 'ghdl',
'linux_bin': 'ghdl'
}
return tool_info
def get_standard_libraries(self):
GHDL_STANDARD_LIBS = ['ieee', 'std']
return GHDL_STANDARD_LIBS
......@@ -66,10 +63,11 @@ class ToolGHDL(ActionMakefile):
self.writeln("""\
#target for cleaning all intermediate stuff
clean:
\t\trm -rf *.cf
\t\trm -rf *.cf *.o $(TOP_MODULE)
#target for cleaning final files
mrproper: clean
\t\trm -r *.vcd
""")
......
hdlmake/tools/ise.py
View file @ 47b3bddc
......@@ -21,13 +21,14 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing the classes that are used to handle Xilinx ISE"""
from __future__ import print_function
import xml.dom.minidom
import xml.parsers.expat
import logging
import re
import os
import platform
import string
from subprocess import Popen, PIPE
......@@ -35,8 +36,8 @@ import hdlmake.new_dep_solver as dep_solver
from hdlmake.action import ActionMakefile
from hdlmake.util import path as path_mod
XmlImpl = xml.dom.minidom.getDOMImplementation()
XML_IMPL = xml.dom.minidom.getDOMImplementation()
FAMILY_NAMES = {
"XC6S": "Spartan6",
......@@ -49,32 +50,45 @@ FAMILY_NAMES = {
"XC7K": "Kintex7",
"XC7A": "Artix7"}
ISE_STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std',
'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib']
class ToolISE(ActionMakefile):
"""Class providing the methods to create and build a Xilinx ISE project"""
TOOL_INFO = {
'name': 'ISE',
'id': 'ise',
'windows_bin': 'ise',
'linux_bin': 'ise',
'project_ext': 'xise'}
def __init__(self):
super(ToolISE, self).__init__()
def get_keys(self):
tool_info = {
'name': 'ISE',
'id': 'ise',
'windows_bin': 'ise',
'linux_bin': 'ise',
'project_ext': 'xise'
}
return tool_info
self.props = {}
self.files = []
self.libs = []
self.xml_doc = None
self.xml_files = []
self.xml_props = []
self.xml_libs = []
self.xml_ise = None
self.xml_project = None
self.xml_bindings = None
self.top_mod = None
self.ise = None
self.fileset = []
self.flist = []
def get_standard_libraries(self):
ISE_STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std',
'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib']
return ISE_STANDARD_LIBS
def detect_version(self, path):
is_windows = path_mod.check_windows()
version_pattern = re.compile(
'.*?(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d).*')
r'.*?(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d).*')
# First check if we have version in path
match = re.match(version_pattern, path)
......@@ -88,15 +102,15 @@ class ToolISE(ActionMakefile):
xst_output = xst_output.stdout.readlines()[0]
xst_output = xst_output.strip()
version_pattern = re.compile(
'Release\s(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d)\s.*')
r'Release\s(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d)\s.*')
match = re.match(version_pattern, xst_output)
if match:
ise_version = "%s.%s" % (
match.group('major'),
match.group('minor'))
else:
logging.error("xst output is not in expected format: %s\n" % xst_output +
"Can't determine ISE version")
logging.error("xst output is not in expected format: %s\n",
xst_output + "Can't determine ISE version")
return None
return ise_version
......@@ -283,9 +297,9 @@ mrproper:
"syn_post_bitstream_cmd"],
xtclsh_path=os.path.join(tool_path, "xtclsh"))
self.write(makefile_text)
for f in top_mod.incl_makefiles:
if os.path.exists(f):
self.write("include %s\n" % f)
for file_aux in top_mod.incl_makefiles:
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
class StringBuffer(list):
......@@ -309,16 +323,6 @@ mrproper:
def generate_synthesis_project(
self, update=False, tool_version='', top_mod=None, fileset=None):
self.props = {}
self.files = []
self.libs = []
self.xml_doc = None
self.xml_files = []
self.xml_props = []
self.xml_libs = []
self.xml_ise = None
self.xml_project = None
self.xml_bindings = None
self.top_mod = top_mod
self.ise = tool_version
......@@ -335,7 +339,8 @@ mrproper:
self.load_xml(top_mod.manifest_dict["syn_project"])
except:
logging.error("Error while reading the project file.\n"
"Are you sure that syn_project indicates a correct ISE project file?")
"Are you sure that syn_project indicates "
"a correct ISE project file?")
raise
else:
self.add_initial_properties()
......@@ -351,8 +356,8 @@ mrproper:
self.libs.append(lib)
def add_libs(self, libs):
for l in libs:
self._add_lib(l)
for lib_aux in libs:
self._add_lib(lib_aux)
self.libs.remove('work')
def add_property(self, name, value, is_default=False):
......@@ -369,29 +374,32 @@ mrproper:
self.add_property("Create Binary Configuration File", "true")
def _set_values_from_manifest(self):
tm = self.top_mod
if tm.manifest_dict["syn_family"] is None:
tm.manifest_dict["syn_family"] = FAMILY_NAMES.get(
tm.manifest_dict["syn_device"][0:4].upper())
if tm.manifest_dict["syn_family"] is None:
top_module = self.top_mod
if top_module.manifest_dict["syn_family"] is None:
top_module.manifest_dict["syn_family"] = FAMILY_NAMES.get(
top_module.manifest_dict["syn_device"][0:4].upper())
if top_module.manifest_dict["syn_family"] is None:
logging.error(
"syn_family is not definied in Manifest.py and can not be guessed!")
"syn_family is not definied in Manifest.py"
" and can not be guessed!")
quit(-1)
self.add_property("Device", tm.manifest_dict["syn_device"])
self.add_property("Device Family", tm.manifest_dict["syn_family"])
self.add_property("Speed Grade", tm.manifest_dict["syn_grade"])
self.add_property("Package", tm.manifest_dict["syn_package"])
self.add_property("Device", top_module.manifest_dict["syn_device"])
self.add_property("Device Family",
top_module.manifest_dict["syn_family"])
self.add_property("Speed Grade", top_module.manifest_dict["syn_grade"])
self.add_property("Package", top_module.manifest_dict["syn_package"])
self.add_property(
"Implementation Top",
"Architecture|" +
tm.manifest_dict[
top_module.manifest_dict[
"syn_top"])
self.add_property(
"Implementation Top Instance Path",
"/" + tm.manifest_dict["syn_top"])
"/" + top_module.manifest_dict["syn_top"])
def _parse_props(self):
for xmlp in self.xml_project.getElementsByTagName("properties")[0].getElementsByTagName("property"):
properties_temp = self.xml_project.getElementsByTagName("properties")
for xmlp in properties_temp[0].getElementsByTagName("property"):
self.add_property(
name=xmlp.getAttribute("xil_pn:name"),
value=xmlp.getAttribute("xil_pn:value"),
......@@ -404,15 +412,16 @@ mrproper:
where=self.xml_doc.documentElement)
def _parse_libs(self):
for l in self.xml_project.getElementsByTagName("libraries")[0].getElementsByTagName("library"):
self._add_lib(l.getAttribute("xil_pn:name"))
libraries_temp = self.xml_project.getElementsByTagName("libraries")
for lib_aux in libraries_temp[0].getElementsByTagName("library"):
self._add_lib(lib_aux.getAttribute("xil_pn:name"))
self.xml_libs = self._purge_dom_node(
name="libraries",
where=self.xml_doc.documentElement)
def load_xml(self, filename):
f = open(filename)
self.xml_doc = xml.dom.minidom.parse(f)
file_xml = open(filename)
self.xml_doc = xml.dom.minidom.parse(file_xml)
self.xml_project = self.xml_doc.getElementsByTagName("project")[0]
import sys
try:
......@@ -440,80 +449,84 @@ mrproper:
"xil_pn:ise_version").split(
'.'))
where.removeChild(node)
except:
except xml.parsers.expat.ExpatError:
pass
f.close()
file_xml.close()
self._set_values_from_manifest()
def _purge_dom_node(self, name, where):
try:
node = where.getElementsByTagName(name)[0]
where.removeChild(node)
except:
except xml.parsers.expat.ExpatError:
pass
new = self.xml_doc.createElement(name)
where.appendChild(new)
return new
def _output_files(self, node):
from hdlmake.srcfile import UCFFile, VHDLFile, VerilogFile, CDCFile, NGCFile
for f in self.files:
fp = self.xml_doc.createElement("file")
fp.setAttribute("xil_pn:name", os.path.relpath(f.path))
if isinstance(f, VHDLFile):
fp.setAttribute("xil_pn:type", "FILE_VHDL")
elif isinstance(f, VerilogFile):
fp.setAttribute("xil_pn:type", "FILE_VERILOG")
elif isinstance(f, UCFFile):
fp.setAttribute("xil_pn:type", "FILE_UCF")
elif isinstance(f, CDCFile):
fp.setAttribute("xil_pn:type", "FILE_CDC")
elif isinstance(f, NGCFile):
fp.setAttribute("xil_pn:type", "FILE_NGC")
from hdlmake.srcfile import (UCFFile, VHDLFile, VerilogFile,
CDCFile, NGCFile)
for file_aux in self.files:
file_project = self.xml_doc.createElement("file")
file_project.setAttribute("xil_pn:name",
os.path.relpath(file_aux.path))
if isinstance(file_aux, VHDLFile):
file_project.setAttribute("xil_pn:type", "FILE_VHDL")
elif isinstance(file_aux, VerilogFile):
file_project.setAttribute("xil_pn:type", "FILE_VERILOG")
elif isinstance(file_aux, UCFFile):
file_project.setAttribute("xil_pn:type", "FILE_UCF")
elif isinstance(file_aux, CDCFile):
file_project.setAttribute("xil_pn:type", "FILE_CDC")
elif isinstance(file_aux, NGCFile):
file_project.setAttribute("xil_pn:type", "FILE_NGC")
else:
continue
assoc = self.xml_doc.createElement("association")
assoc.setAttribute("xil_pn:name", "Implementation")
assoc.setAttribute("xil_pn:seqID", str(self.files.index(f) + 1))
assoc.setAttribute("xil_pn:seqID",
str(self.files.index(file_aux) + 1))
try:
if(f.library != "work"):
if file_aux.library != "work":
lib = self.xml_doc.createElement("library")
lib.setAttribute("xil_pn:name", f.library)
fp.appendChild(lib)
lib.setAttribute("xil_pn:name", file_aux.library)
file_project.appendChild(lib)
except:
pass
fp.appendChild(assoc)
node.appendChild(fp)
file_project.appendChild(assoc)
node.appendChild(file_project)
def _output_bindings(self, node):
from hdlmake.srcfile import CDCFile
for b in [f for f in self.files if isinstance(f, CDCFile)]:
bp = self.xml_doc.createElement("binding")
bp.setAttribute(
for binding in [file_aux for file_aux in self.files
if isinstance(file_aux, CDCFile)]:
binding_project = self.xml_doc.createElement("binding")
binding_project.setAttribute(
"xil_pn:location",
self.top_mod.manifest_dict["syn_top"])
bp.setAttribute("xil_pn:name", b.rel_path())
node.appendChild(bp)
binding_project.setAttribute("xil_pn:name", binding.rel_path())
node.appendChild(binding_project)
def _output_props(self, node):
for name, prop in self.props.iteritems():
node.appendChild(prop.emit_xml(self.xml_doc))
def _output_libs(self, node):
for l in self.libs:
ll = self.xml_doc.createElement("library")
ll.setAttribute("xil_pn:name", l)
node.appendChild(ll)
for lib_aux in self.libs:
lib_project = self.xml_doc.createElement("library")
lib_project.setAttribute("xil_pn:name", lib_aux)
node.appendChild(lib_project)
def _output_ise(self, node):
i = self.xml_doc.createElement("version")
i.setAttribute("xil_pn:ise_version", '%s' % (self.ise))
i.setAttribute("xil_pn:schema_version", "2")
node.appendChild(i)
ise_ver_project = self.xml_doc.createElement("version")
ise_ver_project.setAttribute("xil_pn:ise_version", '%s' % (self.ise))
ise_ver_project.setAttribute("xil_pn:schema_version", "2")
node.appendChild(ise_ver_project)
def emit_xml(self, filename=None):
if not self.xml_doc:
......@@ -532,7 +545,7 @@ mrproper:
output_file.close()
def create_empty_project(self):
self.xml_doc = XmlImpl.createDocument(
self.xml_doc = XML_IMPL.createDocument(
"http://www.xilinx.com/XMLSchema",
"project",
None)
......@@ -568,9 +581,11 @@ mrproper:
def supported_files(self, fileset):
from hdlmake.srcfile import UCFFile, CDCFile, NGCFile, SourceFileSet
sup_files = SourceFileSet()
for f in fileset:
if (isinstance(f, UCFFile)) or (isinstance(f, NGCFile)) or (isinstance(f, CDCFile)):
sup_files.add(f)
for file_aux in fileset:
if ((isinstance(file_aux, UCFFile)) or
(isinstance(file_aux, NGCFile)) or
(isinstance(file_aux, CDCFile))):
sup_files.add(file_aux)
else:
continue
return sup_files
......
hdlmake/tools/isim.py
View file @ 47b3bddc
......@@ -44,18 +44,15 @@ ISIM_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
class ToolISim(ActionMakefile):
TOOL_INFO = {
'name': 'ISim',
'id': 'isim',
'windows_bin': 'isimgui',
'linux_bin': 'isimgui'}
def __init__(self):
super(ToolISim, self).__init__()
def get_keys(self):
tool_info = {
'name': 'ISim',
'id': 'isim',
'windows_bin': 'isimgui',
'linux_bin': 'isimgui'
}
return tool_info
def get_standard_libraries(self):
return ISIM_STANDARD_LIBS
......
hdlmake/tools/iverilog.py
View file @ 47b3bddc
......@@ -40,18 +40,15 @@ IVERILOG_STANDARD_LIBS = ['std', 'ieee', 'ieee_proposed', 'vl', 'synopsys',
class ToolIVerilog(ActionMakefile):
TOOL_INFO = {
'name': 'Icarus Verilog',
'id': 'iverilog',
'windows_bin': 'iverilog',
'linux_bin': 'iverilog'}
def __init__(self):
super(ToolIVerilog, self).__init__()
def get_keys(self):
tool_info = {
'name': 'Icarus Verilog',
'id': 'iverilog',
'windows_bin': 'iverilog',
'linux_bin': 'iverilog'
}
return tool_info
def get_standard_libraries(self):
return IVERILOG_STANDARD_LIBS
......
hdlmake/tools/libero.py
View file @ 47b3bddc
......@@ -35,22 +35,19 @@ LIBERO_STANDARD_LIBS = ['ieee', 'std']
class ToolLibero(ActionMakefile):
TOOL_INFO = {
'name': 'Libero',
'id': 'libero',
'windows_bin': 'libero',
'linux_bin': 'libero',
'project_ext': 'prjx'}
def __init__(self):
super(ToolLibero, self).__init__()
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'Libero',
'id': 'libero',
'windows_bin': 'libero',
'linux_bin': 'libero',
'project_ext': 'prjx' # older projects are prj
}
return tool_info
def get_standard_libraries(self):
return LIBERO_STANDARD_LIBS
......
hdlmake/tools/modelsim.py
View file @ 47b3bddc
......@@ -34,6 +34,13 @@ MODELSIM_STANDARD_LIBS = ['ieee', 'std', 'altera_mf']
class ToolModelsim(VsimMakefileWriter):
TOOL_INFO = {
'name': 'Modelsim',
'id': 'modelsim',
'windows_bin': 'vsim',
'linux_bin': 'vsim'}
def __init__(self):
super(ToolModelsim, self).__init__()
self.vcom_flags.extend(["-modelsimini", "modelsim.ini"])
......@@ -49,14 +56,6 @@ class ToolModelsim(VsimMakefileWriter):
def detect_version(self, path):
pass
def get_keys(self):
tool_info = {
'name': 'Modelsim',
'id': 'modelsim',
}
tool_info.update(super(ToolModelsim, self).get_keys())
return tool_info
def get_standard_libraries(self):
return MODELSIM_STANDARD_LIBS
......
hdlmake/tools/planahead.py
View file @ 47b3bddc
......@@ -36,22 +36,19 @@ PLANAHEAD_STANDARD_LIBS = ['ieee', 'std']
class ToolPlanAhead(ActionMakefile):
TOOL_INFO = {
'name': 'PlanAhead',
'id': 'planahead',
'windows_bin': 'planAhead',
'linux_bin': 'planAhead',
'project_ext': 'ppr'}
def __init__(self):
super(ToolPlanAhead, self).__init__()
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'PlanAhead',
'id': 'planahead',
'windows_bin': 'planAhead',
'linux_bin': 'planAhead',
'project_ext': 'ppr'
}
return tool_info
def get_standard_libraries(self):
return PLANAHEAD_STANDARD_LIBS
......
hdlmake/tools/quartus.py
View file @ 47b3bddc
......@@ -37,6 +37,13 @@ QUARTUS_STANDARD_LIBS = ['altera', 'altera_mf', 'lpm', 'ieee', 'std']
class ToolQuartus(ActionMakefile):
TOOL_INFO = {
'name': 'Quartus',
'id': 'quartus',
'windows_bin': 'quartus',
'linux_bin': 'quartus',
'project_ext': 'qsf'}
def __init__(self):
self._preflow = None
self._postmodule = None
......@@ -46,16 +53,6 @@ class ToolQuartus(ActionMakefile):
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'Quartus',
'id': 'quartus',
'windows_bin': 'quartus',
'linux_bin': 'quartus',
'project_ext': 'qsf'
}
return tool_info
def get_standard_libraries(self):
return QUARTUS_STANDARD_LIBS
......
hdlmake/tools/riviera.py
View file @ 47b3bddc
......@@ -62,6 +62,12 @@ RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES)
class ToolRiviera(VsimMakefileWriter):
TOOL_INFO = {
'name': 'Riviera',
'id': 'riviera',
'windows_bin': 'vsim',
'linux_bin': 'vsim'}
def __init__(self):
super(ToolRiviera, self).__init__()
self.vcom_flags.append("-2008")
......@@ -70,14 +76,6 @@ class ToolRiviera(VsimMakefileWriter):
def detect_version(self, path):
pass
def get_keys(self):
tool_info = {
'name': 'Riviera',
'id': 'riviera',
}
tool_info.update(super(ToolRiviera, self).get_keys())
return tool_info
def get_standard_libraries(self):
return RIVIERA_STANDARD_LIBS
......
hdlmake/tools/sim_makefile_support.py
View file @ 47b3bddc
......@@ -61,14 +61,6 @@ class VsimMakefileWriter(ActionMakefile):
super(VsimMakefileWriter, self).__init__()
def get_keys(self):
tool_info = {
'windows_bin': 'vsim',
'linux_bin': 'vsim'
}
return tool_info
def _print_sim_options(self, top_module):
self.vlog_flags.append(
self.__get_rid_of_vsim_incdirs(top_module.manifest_dict["vlog_opt"]))
......
hdlmake/tools/vivado.py
View file @ 47b3bddc
......@@ -35,22 +35,20 @@ VIVADO_STANDARD_LIBS = ['ieee', 'std']
class ToolVivado(ActionMakefile):
TOOL_INFO = {
'name': 'vivado',
'id': 'vivado',
'windows_bin': 'vivado',
'linux_bin': 'vivado',
'project_ext': 'xpr'
}
def __init__(self):
super(ToolVivado, self).__init__()
def detect_version(self, path):
return 'unknown'
def get_keys(self):
tool_info = {
'name': 'vivado',
'id': 'vivado',
'windows_bin': 'vivado',
'linux_bin': 'vivado',
'project_ext': 'xpr'
}
return tool_info
def get_standard_libraries(self):
return VIVADO_STANDARD_LIBS
......
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