Improvements on how the .tcl files are cleaned in Makefile

parent f5fd4714
......@@ -53,7 +53,7 @@ class ToolDiamond(ToolSyn):
VHDLFile: _LATTICE_SOURCE.format('add'),
VerilogFile: _LATTICE_SOURCE.format('add')}
CLEAN_TARGETS = {'clean': ["*.sty", "$(PROJECT)", "run.tcl"],
CLEAN_TARGETS = {'clean': ["*.sty", "$(PROJECT)"],
'mrproper': ["*.jed"]}
TCL_CONTROLS = {'create': 'prj_project new -name $(PROJECT)'
......
......@@ -73,7 +73,7 @@ class ToolISE(ToolSyn):
SVFile: 'xfile add $(sourcefile)'}
CLEAN_TARGETS = {'clean': ["xst", "xlnx_auto_0_xdb", "iseconfig _xmsgs",
"_ngo", "*.b", "*_summary.html", "*.tcl",
"_ngo", "*.b", "*_summary.html",
"*.bld", "*.cmd_log", "*.drc", "*.lso", "*.ncd",
"*.ngc", "*.ngd", "*.ngr", "*.pad", "*.par",
"*.pcf", "*.prj", "*.ptwx", "*.stx", "*.syr",
......
......@@ -52,7 +52,7 @@ class ToolLibero(ToolSyn):
VHDLFile: _LIBERO_SOURCE.format('-hdl_source'),
VerilogFile: _LIBERO_SOURCE.format('-hdl_source')}
CLEAN_TARGETS = {'clean': ["$(PROJECT)", "run.tcl"],
CLEAN_TARGETS = {'clean': ["$(PROJECT)"],
'mrproper': ["*.pdb", "*.stp"]}
TCL_CONTROLS = {
......
......@@ -194,6 +194,9 @@ SYN_POST_{0}_CMD := {2}
self.makefile_clean()
self.writeln("\t\t" + shell.del_command() +
" project synthesize translate map par bitstream")
self.writeln("\t\t" + shell.del_command() +
" project.tcl synthesize.tcl translate.tcl" +
" map.tcl par.tcl bitstream.tcl files.tcl")
self.writeln()
self.makefile_mrproper()
......
......@@ -48,7 +48,7 @@ class ToolPlanAhead(ToolXilinx):
XMPFile: ToolXilinx._XILINX_SOURCE,
XCOFile: ToolXilinx._XILINX_SOURCE}
CLEAN_TARGETS = {'clean': ["planAhead_*", "planAhead.*", "run.tcl",
CLEAN_TARGETS = {'clean': ["planAhead_*", "planAhead.*",
".Xil", "$(PROJECT).cache", "$(PROJECT).data",
" $(PROJECT).runs", "$(PROJECT).ppr"]}
......
......@@ -73,7 +73,7 @@ class ToolQuartus(ToolSyn):
SVFile: _QUARTUS_SOURCE.format('VERILOG_FILE') +
_QUARTUS_LIBRARY}
CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "run.tcl", "*.summary",
CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "*.summary",
"*.done", "*.jdi", "*.pin", "*.qws",
"db", "incremental_db", "$(PROJECT).qsf",
"*.qpf"],
......
......@@ -59,7 +59,7 @@ class ToolVivado(ToolXilinx):
VHOFile: ToolXilinx._XILINX_SOURCE,
VEOFile: ToolXilinx._XILINX_SOURCE}
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb",
CLEAN_TARGETS = {'clean': [".Xil", "*.jou", "*.log", "*.pb",
"$(PROJECT).cache", "$(PROJECT).data", "work",
"$(PROJECT).runs", "$(PROJECT).hw",
"$(PROJECT).ip_user_files", "$(PROJECT_FILE)"]}
......
......@@ -43,7 +43,7 @@ class ToolVivadoSim(ToolSim):
HDL_FILES = {VerilogFile: '', VHDLFile: '', SVFile: ''}
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb",
CLEAN_TARGETS = {'clean': [".Xil", "*.jou", "*.log", "*.pb",
"work", "xsim.dir"],
'mrproper': ["*.wdb", "*.vcd"]}
......
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