Commit 4fc0214d authored by Tristan Gingold's avatar Tristan Gingold

Add a test for verilog recursion.

parent 0c0be836
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "vlog.v" ]
`define nest(x) `nest(x)
module gate;
wire `nest(w3);
endmodule
......@@ -378,6 +378,10 @@ def test_err_vlog_define():
def test_err_vlog_no_macro():
run_compare(path="079err_vlg_macro")
def test_err_vlog_recursion():
with pytest.raises(SystemExit) as _:
run([], path="080err_vlg_recursion")
def test_dep_level():
run(['list-files'], path="053vlog_dep_level")
run(['list-files', '--delimiter', ','], path="053vlog_dep_level")
......
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