Include the Xilinx BMM files in Vivado, ISE and PlanAhead

parent 968fa87d
......@@ -184,6 +184,11 @@ class VHOFile(File):
pass
class BMMFile(File):
"""Xilinx Block Memory Map File"""
pass
class VEOFile(File):
"""Xilinx Verilog Template File"""
pass
......@@ -212,6 +217,7 @@ XILINX_FILE_DICT = {
'ram': RAMFile,
'vho': VHOFile,
'veo': VEOFile,
'bmm': BMMFile,
'xci': XCIFile}
......
......@@ -31,7 +31,7 @@ from .make_syn import ToolSyn
from hdlmake.util import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
UCFFile, CDCFile, NGCFile)
UCFFile, CDCFile, NGCFile, BMMFile)
FAMILY_NAMES = {
"XC6S": "Spartan6",
......@@ -65,6 +65,7 @@ class ToolISE(ToolSyn):
SUPPORTED_FILES = {
UCFFile: 'xfile add $(sourcefile)',
CDCFile: 'xfile add $(sourcefile)',
BMMFile: 'xfile add $(sourcefile)',
NGCFile: 'xfile add $(sourcefile)'}
HDL_FILES = {
......
......@@ -25,7 +25,7 @@
from __future__ import absolute_import
from .xilinx import ToolXilinx
from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile, XCOFile)
from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile, XCOFile, BMMFile)
class ToolPlanAhead(ToolXilinx):
......@@ -46,6 +46,7 @@ class ToolPlanAhead(ToolXilinx):
UCFFile: ToolXilinx._XILINX_SOURCE,
NGCFile: ToolXilinx._XILINX_SOURCE,
XMPFile: ToolXilinx._XILINX_SOURCE,
BMMFile: ToolXilinx._XILINX_SOURCE,
XCOFile: ToolXilinx._XILINX_SOURCE}
CLEAN_TARGETS = {'clean': ["planAhead_*", "planAhead.*",
......
......@@ -27,7 +27,7 @@
from __future__ import absolute_import
from .xilinx import ToolXilinx
from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, COEFile, BDFile, TCLFile,
XCOFile, COEFile, BDFile, TCLFile, BMMFile,
MIFFile, RAMFile, VHOFile, VEOFile, XCFFile)
......@@ -54,6 +54,7 @@ class ToolVivado(ToolXilinx):
XCOFile: ToolXilinx._XILINX_SOURCE,
COEFile: ToolXilinx._XILINX_SOURCE,
BDFile: ToolXilinx._XILINX_SOURCE,
BMMFile: ToolXilinx._XILINX_SOURCE,
TCLFile: ToolXilinx._XILINX_SOURCE,
MIFFile: ToolXilinx._XILINX_SOURCE,
RAMFile: ToolXilinx._XILINX_SOURCE,
......
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