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Projects
Hdlmake
Commits
55709f50
Commit
55709f50
authored
Jul 23, 2016
by
Javier D. Garcia-Lasheras
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A more ordered way to process the Manifest dict using super
parent
2ba26cdf
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Showing
7 changed files
with
48 additions
and
18 deletions
+48
-18
module.py
hdlmake/module.py
+5
-9
module_altera.py
hdlmake/module_altera.py
+7
-2
module_content.py
hdlmake/module_content.py
+8
-2
module_core.py
hdlmake/module_core.py
+8
-2
module_plugin.py
hdlmake/module_plugin.py
+6
-0
module_simulation.py
hdlmake/module_simulation.py
+6
-1
module_synthesis.py
hdlmake/module_synthesis.py
+8
-2
No files found.
hdlmake/module.py
View file @
55709f50
...
...
@@ -154,6 +154,10 @@ class Module(ModuleCore, ModuleSynthesis, ModuleSimulation, ModuleContent, Modul
except
OSError
:
# a catologue is not empty - we are done
break
def
process_manifest
(
self
):
super
(
Module
,
self
)
.
process_manifest
()
logging
.
debug
(
"Process manifest at: "
+
os
.
path
.
dirname
(
self
.
path
))
def
parse_manifest
(
self
):
"""
Create a dictionary from the module Manifest.py and assign it to the manifest_dict property.
...
...
@@ -213,15 +217,7 @@ class Module(ModuleCore, ModuleSynthesis, ModuleSimulation, ModuleContent, Modul
self
.
manifest_dict
=
opt_map
# Process the parsed manifest_dict to assign the module properties
self
.
_process_manifest_universal
()
self
.
_process_manifest_synthesis
()
self
.
_process_manifest_simulation
()
self
.
_process_manifest_includes
()
self
.
_process_manifest_files
()
self
.
_process_manifest_modules
()
self
.
_process_manifest_altera
()
self
.
_process_manifest_force_tool
()
self
.
_process_manifest_included_makefiles
()
self
.
process_manifest
()
# Tag the module as parsed
self
.
isparsed
=
True
...
...
hdlmake/module_altera.py
View file @
55709f50
import
os
from
.module_plugin
import
ModulePlugin
from
.util
import
path
as
path_mod
class
ModuleAltera
(
object
):
class
ModuleAltera
(
ModulePlugin
):
def
__init__
(
self
):
super
(
ModuleAltera
,
self
)
.
__init__
()
# Manifest Altera Properties
self
.
quartus_preflow
=
None
self
.
quartus_postmodule
=
None
self
.
quartus_postflow
=
None
self
.
hw_tcl_filename
=
None
super
(
ModuleAltera
,
self
)
.
__init__
()
def
process_manifest
(
self
):
self
.
_process_manifest_altera
()
super
(
ModuleAltera
,
self
)
.
process_manifest
()
def
_process_manifest_altera
(
self
):
from
.srcfile
import
TCLFile
...
...
hdlmake/module_content.py
View file @
55709f50
import
logging
from
.
import
fetch
from
.module_plugin
import
ModulePlugin
from
.util
import
path
as
path_mod
class
ModuleContent
(
object
):
class
ModuleContent
(
ModulePlugin
):
def
__init__
(
self
):
super
(
ModuleContent
,
self
)
.
__init__
()
# Manifest Files Properties
self
.
files
=
None
# Manifest Modules Properties
...
...
@@ -12,6 +12,12 @@ class ModuleContent(object):
self
.
git
=
[]
self
.
svn
=
[]
self
.
git_submodules
=
[]
super
(
ModuleContent
,
self
)
.
__init__
()
def
process_manifest
(
self
):
self
.
_process_manifest_files
()
self
.
_process_manifest_modules
()
super
(
ModuleContent
,
self
)
.
process_manifest
()
def
_process_manifest_files
(
self
):
from
.srcfile
import
TCLFile
,
VerilogFile
,
VHDLFile
,
SourceFileSet
...
...
hdlmake/module_core.py
View file @
55709f50
from
.module_plugin
import
ModulePlugin
class
ModuleCore
(
object
):
class
ModuleCore
(
ModulePlugin
):
def
__init__
(
self
):
super
(
ModuleCore
,
self
)
.
__init__
()
# Universal Manifest Properties
self
.
library
=
"work"
self
.
target
=
None
self
.
action
=
None
super
(
ModuleCore
,
self
)
.
__init__
()
# Manifest Force tool Property
self
.
force_tool
=
None
def
process_manifest
(
self
):
self
.
_process_manifest_force_tool
()
self
.
_process_manifest_universal
()
super
(
ModuleCore
,
self
)
.
process_manifest
()
def
_process_manifest_force_tool
(
self
):
if
self
.
manifest_dict
[
"force_tool"
]:
ft
=
self
.
manifest_dict
[
"force_tool"
]
...
...
hdlmake/module_plugin.py
0 → 100644
View file @
55709f50
class
ModulePlugin
(
object
):
def
process_manifest
(
self
):
pass
hdlmake/module_simulation.py
View file @
55709f50
from
.module_plugin
import
ModulePlugin
class
ModuleSimulation
(
object
):
def
__init__
(
self
):
super
(
ModuleSimulation
,
self
)
.
__init__
()
# Manifest Simulation Properties
self
.
sim_top
=
None
self
.
sim_tool
=
None
...
...
@@ -16,7 +16,12 @@ class ModuleSimulation(object):
self
.
iverilog_opt
=
None
# Includes Manifest Properties
self
.
include_dirs
=
None
super
(
ModuleSimulation
,
self
)
.
__init__
()
def
process_manifest
(
self
):
self
.
_process_manifest_simulation
()
self
.
_process_manifest_includes
()
super
(
ModuleSimulation
,
self
)
.
process_manifest
()
def
_process_manifest_simulation
(
self
):
from
.srcfile
import
SourceFileSet
...
...
hdlmake/module_synthesis.py
View file @
55709f50
from
.module_plugin
import
ModulePlugin
class
ModuleSynthesis
(
object
):
class
ModuleSynthesis
(
ModulePlugin
):
def
__init__
(
self
):
super
(
ModuleSynthesis
,
self
)
.
__init__
()
# Manifest Synthesis Properties
self
.
syn_device
=
None
self
.
syn_family
=
None
...
...
@@ -15,6 +15,12 @@ class ModuleSynthesis(object):
self
.
syn_post_script
=
None
# Manifest Included Makefiles
self
.
incl_makefiles
=
[]
super
(
ModuleSynthesis
,
self
)
.
__init__
()
def
process_manifest
(
self
):
self
.
_process_manifest_synthesis
()
self
.
_process_manifest_included_makefiles
()
super
(
ModuleSynthesis
,
self
)
.
process_manifest
()
def
_process_manifest_synthesis
(
self
):
# Synthesis properties
...
...
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