Add sim_top variable to complement syn_top: top_module is redundant now

5aa91926 · Javier D. Garcia-Lasheras · cd77102d · 5aa91926 · 5aa91926 · 5aa91926
Commit 5aa91926 authored Jul 22, 2016 by Javier D. Garcia-Lasheras
21 changed files
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -392,7 +392,7 @@ In the VHDL case, the top Manifest.py for Modelsim simulation is:

   action = "simulation"
   sim_tool = "modelsim"
-   top_module = "counter_tb"
+   sim_top = "counter_tb"

   sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"

@@ -406,7 +406,7 @@ And in the Verilog case, the associated Manifest.py is:

   action = "simulation"
   sim_tool = "modelsim"
-   top_module = "counter_tb"
+   sim_top = "counter_tb"

   sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"

@@ -420,7 +420,7 @@ The following common top specific Manifest variables describes the simulation:

 - ``action``: indicates that we are going to perform a simulation.
 - ``sim_tool``: indicates that modelsim is going to be the simulation we are going to use.
- ``top_module``: indicates the name of the top HDL entity/instance that is going to be simulated.
+- ``sim_top``: indicates the name of the top HDL entity/instance that is going to be simulated.
 - ``sim_post_cmd``: indicates a command that must be issued after the simulation process has finnished.

 Now, if we want to launch the simulation, we must follow the next steps. First, get into the folder containing the top Manifest.py we want to execute and run ``hdlmake`` without arguments. e.g. for VHDL:
@@ -768,7 +768,7 @@ As a very simple example, we can introduce both extra commands in the top simula

   action = "simulation"
   sim_tool = "modelsim"
-   top_module = "counter_tb"
+   sim_top = "counter_tb"

   sim_pre_cmd = "echo This is executed just before the simulation"
   sim_post_cmd = "echo This is executed just after the simulation"
@@ -849,7 +849,7 @@ The first one is to include this as a new variable in the top Manifest.py, i.e.:

   action = "simulation"
   sim_tool = "modelsim"
-   top_module = "counter_tb"
+   sim_top = "counter_tb"

   simulate_vhdl = False

@@ -1122,8 +1122,6 @@ Top Manifest variables
 +================+==============+=================================================================+===========+ 
 | action         | str          | What is the action that should be taken (simulation/synthesis)  | ""        | 
 +----------------+--------------+-----------------------------------------------------------------+-----------+
-| top_module     | str          | Top level entity for synthesis and simulation                   | None      |
-+----------------+--------------+-----------------------------------------------------------------+-----------+
 | incl_makefiles | list, str    | List of .mk files appended to toplevel makefile                 | []        |
 +----------------+--------------+-----------------------------------------------------------------+-----------+
 
@@ -1155,6 +1153,8 @@ Basic simulation variables:
 +----------------+--------------+-----------------------------------------------------------------+-----------+
 | Name           | Type         | Description                                                     | Default   |
 +================+==============+=================================================================+===========+
+| sim_top        | str          | Top level module for simulation                                 | None      |
+----------------+--------------+-----------------------------------------------------------------+-----------+
 | sim_tool       | str          | Simulation tool to be used (e.g. isim, vsim, iverilog)          | None      |
 +----------------+--------------+-----------------------------------------------------------------+-----------+
 | sim_pre_cmd    | str          | Command to be executed before simulation                        | None      |
@@ -1209,6 +1209,8 @@ Basic synthesis variables:
 +=================+=============+=================================================================+===========+
 | target          | str         | What is the target architecture                                 | ""        |
 +-----------------+-------------+-----------------------------------------------------------------+-----------+
+| syn_top         | str         | Top level module for synthesis                                  | None      |
+-----------------+-------------+-----------------------------------------------------------------+-----------+
 | syn_tool        | str         | Tool to be used in the synthesis                                | None      |
 +-----------------+-------------+-----------------------------------------------------------------+-----------+
 | syn_device      | str         | Target FPGA device                                              | None      |
@@ -1219,8 +1221,6 @@ Basic synthesis variables:
 +-----------------+-------------+-----------------------------------------------------------------+-----------+
 | syn_package     | str         | Package variant of target FPGA                                  | None      |
 +-----------------+-------------+-----------------------------------------------------------------+-----------+
-| syn_top         | str         | Top level module for synthesis                                  | None      |
-+-----------------+-------------+-----------------------------------------------------------------+-----------+
 | syn_project     | str         | Project file name                                               | None      |
 +-----------------+-------------+-----------------------------------------------------------------+-----------+
 | syn_pre_cmd     | str         | Command to be executed before synthesis                         | None      |
@@ -1331,23 +1331,6 @@ This option is targeted to VHDL designs in which the SDB (Self Describing Bus) s
 http://www.ohwr.org/projects/fpga-config-space/wiki 


-``--no-parse``
--------------------------
-
-HDLMake includes both a VHDL and a Verilog parser, allowing for building optimal 
-dependency-driven filesets by performing a recursive relation search with the
-selected ``top_module`` as the root.
-
-By default, the parser is enabled and only the strictly neccessary files will
-be added to the file set, this is:
-
- All those files containing entities that our ``top_module`` requires.
- All those tool-specific files that cannot be parsed but are mandatory.
-
-When the ``--no-parse`` argument is provided, the parser is disabled and all the files included in the module
-hierarchy will be used when building a design file set.
-
-
 ``--force``
 -----------
 Force hdlmake to generate the makefile, even if the specified tool is missing.

--- a/hdlmake/__main__.py
+++ b/hdlmake/__main__.py
@@ -130,6 +130,7 @@ def _action_runner(modules_pool):
                logging.error("`sim_tool' manifest variable has to be specified. "
                              "Otherwise hdlmake doesn't know how to simulate the project.")
                quit()
+            top_mod.top_entity = top_mod.sim_top
            action = [ 
                GenerateSimulationMakefile, 
            ]
@@ -138,6 +139,7 @@ def _action_runner(modules_pool):
                logging.error("`syn_tool' manifest variable has to be specified. "
                              "Otherwise hdlmake doesn't know how to synthesize the project.")
                quit()
+            top_mod.top_entity = top_mod.syn_top
            action = [
                GenerateSynthesisProject,
                GenerateSynthesisMakefile,

--- a/hdlmake/action/simulation.py
+++ b/hdlmake/action/simulation.py
@@ -33,8 +33,8 @@ from .action import Action
 class GenerateSimulationMakefile(Action):

    def _check_manifest(self):
-        if not self.modules_pool.get_top_module().top_module:
-            logging.error("top_module variable must be set in the top manifest.")
+        if not self.modules_pool.get_top_module().sim_top:
+            logging.error("sim_top variable must be set in the top manifest.")
            sys.exit("Exiting")
        if not self.modules_pool.get_top_module().sim_tool:
            logging.error("sim_tool variable must be set in the top manifest.")

--- a/hdlmake/manifest_parser.py
+++ b/hdlmake/manifest_parser.py
@@ -95,6 +95,7 @@ class ManifestParser(ConfigParser):

        self.add_delimiter()

+        self.add_option('sim_top', default=None, help="Top level module for simulation", type='')
        self.add_option('sim_tool', default=None, help="Simulation tool to be used (e.g. isim, vsim, iverilog)", type='')
        self.add_option('sim_pre_cmd', default=None, help="Command to be executed before simulation", type='')
        self.add_option('sim_post_cmd', default=None, help="Command to be executed after simulation", type='')

--- a/hdlmake/module.py
+++ b/hdlmake/module.py
@@ -72,6 +72,7 @@ class Module(object):
        self.svn = []
        self.target = None
        self.action = None
+        self.top_entity = None
        self.vmap_opt = None
        self.vlog_opt = None
        self.vcom_opt = None
@@ -93,6 +94,7 @@ class Module(object):
        self.syn_ise_version = None
        self.syn_pre_script = None
        self.syn_post_script = None
+        self.sim_top = None
        self.sim_only_files = None
        self.sim_pre_script = None
        self.sim_post_script = None
@@ -282,6 +284,7 @@ class Module(object):
        self.vlog_opt = self.manifest_dict["vlog_opt"]
        self.iverilog_opt = self.manifest_dict["iverilog_opt"]
        self.sim_tool = self.manifest_dict["sim_tool"]
+        self.sim_top = self.manifest_dict["sim_top"]
        if self.manifest_dict["force_tool"]:
            ft = self.manifest_dict["force_tool"]
            self.force_tool = ft.split(' ')

--- a/hdlmake/module_pool.py
+++ b/hdlmake/module_pool.py
@@ -214,7 +214,7 @@ class ModulePool(list):
        return all_manifested_files

    def build_limited_file_set(self):
-        top_entity = self.top_module.top_module
+        top_entity = self.top_module.top_entity
        #self.solve_dependencies()
        all_files = self.build_complete_file_set()
        if not self._deps_solved:

--- a/hdlmake/tools/aldec/aldec.py
+++ b/hdlmake/tools/aldec/aldec.py
@@ -65,7 +65,7 @@ local: sim_pre_cmd simulation sim_post_cmd
 simulation:
 """)
        makefile_text_1 = makefile_tmplt_1.substitute(
-            top_module=top_module.top_module
+            top_module=top_module.top_entity
        )
        self.write(makefile_text_1)


--- a/hdlmake/tools/ghdl/ghdl.py
+++ b/hdlmake/tools/ghdl/ghdl.py
@@ -68,7 +68,7 @@ simulation:
 """)

        makefile_text_1 = makefile_tmplt_1.substitute(
-            top_module=top_module.top_module
+            top_module=top_module.top_entity
        )
        self.write(makefile_text_1)


--- a/hdlmake/tools/isim/isim.py
+++ b/hdlmake/tools/isim/isim.py
@@ -80,7 +80,7 @@ class ToolControls(MakefileWriter):
        from hdlmake.srcfile import VerilogFile, VHDLFile
        make_preambule_p1 = """## variables #############################
 PWD := $(shell pwd)
-TOP_MODULE := """ + top_module.top_module + """
+TOP_MODULE := """ + top_module.top_entity + """
 FUSE_OUTPUT ?= isim_proj

 XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) + """

--- a/hdlmake/tools/iverilog/iverilog.py
+++ b/hdlmake/tools/iverilog/iverilog.py
@@ -86,7 +86,7 @@ simulation:
 """)

        makefile_text_1 = makefile_tmplt_1.substitute(
-            top_module=top_module.top_module
+            top_module=top_module.top_entity
        )
        self.write(makefile_text_1)


--- a/tests/counter/sim/aldec/verilog/Manifest.py
+++ b/tests/counter/sim/aldec/verilog/Manifest.py
 action = "simulation"
 sim_tool = "aldec"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"


--- a/tests/counter/sim/aldec/vhdl/Manifest.py
+++ b/tests/counter/sim/aldec/vhdl/Manifest.py
 action = "simulation"
 sim_tool = "aldec"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"


--- a/tests/counter/sim/ghdl/vhdl/Manifest.py
+++ b/tests/counter/sim/ghdl/vhdl/Manifest.py
 action = "simulation"
 sim_tool = "ghdl"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "ghdl -r counter_tb --stop-time=6us --vcd=counter_tb.vcd; gtkwave counter_tb.vcd"


--- a/tests/counter/sim/isim/verilog/Manifest.py
+++ b/tests/counter/sim/isim/verilog/Manifest.py
 action = "simulation"
 target = "xilinx"
 sim_tool = "isim"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd"


--- a/tests/counter/sim/isim/vhdl/Manifest.py
+++ b/tests/counter/sim/isim/vhdl/Manifest.py
 action = "simulation"
 target = "xilinx"
 sim_tool = "isim"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd"


--- a/tests/counter/sim/iverilog/verilog/Manifest.py
+++ b/tests/counter/sim/iverilog/verilog/Manifest.py
 action = "simulation"
 sim_tool = "iverilog"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"


--- a/tests/counter/sim/iverilog/vhdl/Manifest.py
+++ b/tests/counter/sim/iverilog/vhdl/Manifest.py
 action = "simulation"
 sim_tool = "iverilog"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_pre_cmd ="echo IMPORTANT, IVerilog always needs a Verilog testbench, no matter if the DUT is written in VHDL!"
 sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"

--- a/tests/counter/sim/modelsim/verilog/Manifest.py
+++ b/tests/counter/sim/modelsim/verilog/Manifest.py
 action = "simulation"
 sim_tool = "modelsim"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "vsim -novopt -do ../vsim.do -i counter_tb"


--- a/tests/counter/sim/modelsim/vhdl/Manifest.py
+++ b/tests/counter/sim/modelsim/vhdl/Manifest.py
 action = "simulation"
 sim_tool = "modelsim"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"


--- a/tests/counter/sim/riviera/verilog/Manifest.py
+++ b/tests/counter/sim/riviera/verilog/Manifest.py
 action = "simulation"
 sim_tool = "riviera"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "vsim -do ../vsim.do"


--- a/tests/counter/sim/riviera/vhdl/Manifest.py
+++ b/tests/counter/sim/riviera/vhdl/Manifest.py
 action = "simulation"
 sim_tool = "riviera"
-top_module = "counter_tb"
+sim_top = "counter_tb"

 sim_post_cmd = "vsim -do ../vsim.do"