Handle hdl as a dictionay in Aldec Active-HDL

5c7c8e07 · Javier D. Garcia-Lasheras · b18e9fbc · 5c7c8e07 · 5c7c8e07 · 5c7c8e07
Commit 5c7c8e07 authored Mar 13, 2017 by Javier D. Garcia-Lasheras
4 changed files
--- a/hdlmake/tools/active_hdl.py
+++ b/hdlmake/tools/active_hdl.py
@@ -34,13 +34,13 @@ class ToolActiveHDL(ToolSim):

    TOOL_INFO = {
        'name': 'Aldec Active-HDL',
-        'id': 'aldec',
+        'id': 'active_hdl',
        'windows_bin': 'vsimsa',
        'linux_bin': None}

    STANDARD_LIBS = ['ieee', 'std']

-    HDL_FILES = [VHDLFile, VerilogFile, SVFile]
+    HDL_FILES = {VHDLFile: None, VerilogFile: None, SVFile: None}

    CLEAN_TARGETS = {'clean': ["run.command", "library.cfg", "work"],
                     'mrproper': ["*.vcd", "*.asdb"]}
@@ -48,7 +48,7 @@ class ToolActiveHDL(ToolSim):
    def __init__(self):
        super(ToolActiveHDL, self).__init__()
        self._tool_info.update(ToolActiveHDL.TOOL_INFO)
-        self._hdl_files.extend(ToolActiveHDL.HDL_FILES)
+        self._hdl_files.update(ToolActiveHDL.HDL_FILES)
        self._standard_libs.extend(ToolActiveHDL.STANDARD_LIBS)
        self._clean_targets.update(ToolActiveHDL.CLEAN_TARGETS)


--- a/tests/counter/sim/aldec/play_sim.do
+++ b/tests/counter/sim/aldec/play_sim.do
--- a/tests/counter/sim/aldec/verilog/Manifest.py
+++ b/tests/counter/sim/aldec/verilog/Manifest.py
 action = "simulation"
-sim_tool = "aldec"
+sim_tool = "active_hdl"
 sim_top = "counter_tb"

 sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"

--- a/tests/counter/sim/aldec/vhdl/Manifest.py
+++ b/tests/counter/sim/aldec/vhdl/Manifest.py
 action = "simulation"
-sim_tool = "aldec"
+sim_tool = "active_hdl"
 sim_top = "counter_tb"

 sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"