Rename the Makefile printing methods

parent 3b9d64d5
......@@ -55,7 +55,7 @@ class ActionMakefile(Action):
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def _print_sim_top(self, top_module):
def makefile_sim_top(self, top_module):
top_parameter = string.Template("""\
TOP_MODULE := ${top_module}
PWD := $$(shell pwd)
......@@ -63,7 +63,7 @@ PWD := $$(shell pwd)
self.writeln(top_parameter.substitute(
top_module=top_module.manifest_dict["sim_top"]))
def _print_syn_top(self, top_module, tool_path, tool_info):
def makefile_syn_top(self, top_module, tool_path, tool_info):
"""Create the top part of the synthesis Makefile"""
if path_mod.check_windows():
tcl_interpreter = tool_info["windows_bin"]
......@@ -85,7 +85,7 @@ TCL_INTERPRETER := $$(TOOL_PATH)/${tcl_interpreter}
tool_path=tool_path,
top_module=top_module.manifest_dict["syn_top"]))
def _print_syn_tcl(self, top_module, tcl_controls):
def makefile_syn_tcl(self, top_module, tcl_controls):
"""Create the Makefile TCL dictionary for the selected tool"""
tcl_string = string.Template("""\
......@@ -147,18 +147,18 @@ export TCL_BITSTREAM
tcl_bitstream=tcl_controls["bitstream"]))
def _print_sim_options(self, top_module):
def makefile_sim_options(self, top_module):
pass
def _print_sim_local(self, top_module):
def makefile_sim_local(self, top_module):
self.writeln("#target for performing local simulation\n"
"local: sim_pre_cmd simulation sim_post_cmd\n")
def _print_syn_local(self):
def makefile_syn_local(self):
self.writeln("#target for performing local synthesis\n"
"local: syn_pre_cmd synthesis syn_post_cmd\n")
def _print_syn_build(self):
def makefile_syn_build(self):
"""Generate a Makefile to handle a synthesis project"""
self.writeln("""\
#target for performing local synthesis
......@@ -208,7 +208,7 @@ bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd run_
""")
def _print_sim_sources(self, fileset):
def makefile_sim_sources(self, fileset):
from hdlmake.srcfile import VerilogFile, VHDLFile
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
......@@ -254,7 +254,7 @@ bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd run_
" \\\n")
self.write('\n')
def _print_syn_command(self, top_module):
def makefile_syn_command(self, top_module):
"""Create the Makefile targets for user defined commands"""
syn_command = string.Template("""\
# User defined commands
......@@ -315,7 +315,7 @@ syn_post_bitstream_cmd:
syn_post_bitstream_cmd=top_module.manifest_dict[
"syn_post_bitstream_cmd"]))
def _print_sim_command(self, top_module):
def makefile_sim_command(self, top_module):
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
......@@ -352,7 +352,7 @@ sim_post_cmd:
" " + ' '.join(clean_targets["mrproper"])
self.writeln(tmp)
def _print_syn_clean(self, clean_targets):
def makefile_syn_clean(self, clean_targets):
"""Print the Makefile clean target for synthesis"""
self._print_tool_clean(clean_targets)
self.writeln("\t\t" + path_mod.del_command() +
......@@ -361,17 +361,17 @@ sim_post_cmd:
" tcl_synthesize tcl_translate tcl_map tcl_par tcl_bitstream")
self._print_tool_mrproper(clean_targets)
def _print_sim_clean(self, clean_targets):
def makefile_sim_clean(self, clean_targets):
"""Print the Makefile clean target for synthesis"""
self._print_tool_clean(clean_targets)
self._print_tool_mrproper(clean_targets)
def _print_sim_phony(self, top_module):
def makefile_sim_phony(self, top_module):
"""Print simulation PHONY target list to the Makefile"""
self.writeln(
".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
def _print_syn_phony(self):
def makefile_syn_phony(self):
"""Print synthesis PHONY target list to the Makefile"""
self.writeln(
".PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis")
......
......@@ -97,11 +97,11 @@ class ActionSimulation(
# dep_solver.solve(dep_files)
# tool_object.generate_simulation_makefile(dep_files, top_module)
tool_object._print_sim_top(top_module)
tool_object._print_sim_options(top_module)
tool_object._print_sim_local(top_module)
tool_object._print_sim_sources(dep_files)
tool_object._print_sim_compilation(dep_files, top_module)
tool_object._print_sim_command(top_module)
tool_object._print_sim_clean(tool_object.CLEAN_TARGETS)
tool_object._print_sim_phony(top_module)
tool_object.makefile_sim_top(top_module)
tool_object.makefile_sim_options(top_module)
tool_object.makefile_sim_local(top_module)
tool_object.makefile_sim_sources(dep_files)
tool_object.makefile_sim_compilation(dep_files, top_module)
tool_object.makefile_sim_command(top_module)
tool_object.makefile_sim_clean(tool_object.CLEAN_TARGETS)
tool_object.makefile_sim_phony(top_module)
......@@ -226,12 +226,12 @@ end sdb_meta_pkg;""")
module=self.get_module_by_path("."))])
tool_object._print_incl_makefiles(top_module)
tool_object._print_syn_top(top_module, tool_path, tool_info)
tool_object._print_syn_tcl(top_module, tool_ctrl)
tool_object._print_syn_files(fileset)
tool_object._print_syn_local()
tool_object._print_syn_command(top_module)
tool_object._print_syn_build()
tool_object._print_syn_clean(tool_object.CLEAN_TARGETS)
tool_object._print_syn_phony()
tool_object.makefile_syn_top(top_module, tool_path, tool_info)
tool_object.makefile_syn_tcl(top_module, tool_ctrl)
tool_object.makefile_syn_files(fileset)
tool_object.makefile_syn_local()
tool_object.makefile_syn_command(top_module)
tool_object.makefile_syn_build()
tool_object.makefile_syn_clean(tool_object.CLEAN_TARGETS)
tool_object.makefile_syn_phony()
logging.info(name + " project file generated.")
......@@ -49,7 +49,7 @@ class ToolActiveHDL(ActionMakefile):
"""Get the version from the Aldec-HDL binary program"""
pass
def _print_sim_compilation(self, fileset, top_module):
def makefile_sim_compilation(self, fileset, top_module):
"""Print Makefile compilation target for Aldec Active-HDL simulator"""
self.writeln("simulation:")
self.writeln("\t\techo \"# Active-HDL command file,"
......
......@@ -52,7 +52,7 @@ class ToolGHDL(ActionMakefile):
"""Get tool version for GHDL"""
pass
def _print_sim_options(self, top_module):
def makefile_sim_options(self, top_module):
"""Print the GHDL options to the Makefile"""
if top_module.manifest_dict["ghdl_opt"]:
ghdl_opt = top_module.manifest_dict["ghdl_opt"]
......@@ -63,7 +63,7 @@ class ToolGHDL(ActionMakefile):
self.writeln(ghdl_string.substitute(
ghdl_opt=ghdl_opt))
def _print_sim_compilation(self, fileset, top_module):
def makefile_sim_compilation(self, fileset, top_module):
"""Print the GDHL simulation compilation target"""
self.writeln("simulation:")
self.writeln("\t\t# Analyze sources")
......
......@@ -80,7 +80,7 @@ class ToolISim(ActionMakefile):
return None
return isim_version
def _print_sim_top(self, top_module):
def makefile_sim_top(self, top_module):
"""Print the top section of the Makefile for Xilinx ISim"""
self.writeln("""## variables #############################
PWD := $(shell pwd)
......@@ -91,7 +91,7 @@ XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) +
"""
""")
def _print_sim_options(self, top_module):
def makefile_sim_options(self, top_module):
"""Print the Xilinx ISim simulation options in the Makefile"""
self.writeln("""VHPCOMP_FLAGS := -intstyle default \
-incremental -initfile xilinxsim.ini
......@@ -101,7 +101,7 @@ VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ +
top_module.manifest_dict["vlog_opt"]) + """
""")
def _print_sim_compilation(self, fileset, top_module):
def makefile_sim_compilation(self, fileset, top_module):
"""Print the compile simulation target for Xilinx ISim"""
make_preambule_p2 = """## rules #################################
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
......
......@@ -67,7 +67,7 @@ class ToolIVerilog(ActionMakefile):
version = iverilog.stdout.readlines()[0].strip()
return version
def _print_sim_compilation(self, fileset, top_module):
def makefile_sim_compilation(self, fileset, top_module):
"""Generate compile simulation Makefile target for IVerilog"""
self.writeln("simulation:")
......@@ -94,7 +94,7 @@ class ToolIVerilog(ActionMakefile):
self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command")
def _print_sim_options(self, top_module):
def makefile_sim_options(self, top_module):
"""Print the IVerilog options to the Makefile"""
if top_module.manifest_dict["iverilog_opt"]:
iverilog_opt = top_module.manifest_dict["iverilog_opt"]
......
......@@ -59,7 +59,7 @@ class ToolModelsim(VsimMakefileWriter):
"""Get version from the Mentor Modelsim program"""
pass
def _print_sim_options(self, top_module):
def makefile_sim_options(self, top_module):
"""Print the Modelsim options to the Makefile"""
if top_module.pool.env["modelsim_path"]:
modelsim_ini_path = os.path.join(
......@@ -68,4 +68,4 @@ class ToolModelsim(VsimMakefileWriter):
else:
modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
super(ToolModelsim, self)._print_sim_options(top_module)
super(ToolModelsim, self).makefile_sim_options(top_module)
......@@ -72,7 +72,7 @@ class ToolPlanAhead(ActionMakefile):
"""Get the Xilinx PlanAhead program version"""
return 'unknown'
def _print_syn_tcl(self, top_module, tcl_controls):
def makefile_syn_tcl(self, top_module, tcl_controls):
"""Create a Xilinx PlanAhead project"""
tmp = "set_property {0} {1} [{2}]"
syn_device = top_module.manifest_dict["syn_device"]
......@@ -88,9 +88,9 @@ class ToolPlanAhead(ActionMakefile):
for prop in properties:
create_new.append(tmp.format(prop[0], prop[1], prop[2]))
tcl_controls["create"] = "\n".join(create_new)
super(ToolPlanAhead, self)._print_syn_tcl(top_module, tcl_controls)
super(ToolPlanAhead, self).makefile_syn_tcl(top_module, tcl_controls)
def _print_syn_files(self, fileset):
def makefile_syn_files(self, fileset):
"""Create a Xilinx PlanAhead project"""
self.writeln("define TCL_FILES")
tmp = "add_files -norecurse {0}"
......
......@@ -60,7 +60,7 @@ class VsimMakefileWriter(ActionMakefile):
self.copy_rules = {}
super(VsimMakefileWriter, self).__init__()
def _print_sim_options(self, top_module):
def makefile_sim_options(self, top_module):
"""Print the vsim options to the Makefile"""
self.vlog_flags.append(
self.__get_rid_of_vsim_incdirs(
......@@ -78,7 +78,7 @@ class VsimMakefileWriter(ActionMakefile):
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
def _print_sim_compilation(self, fileset, top_module):
def makefile_sim_compilation(self, fileset, top_module):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
......
......@@ -81,7 +81,7 @@ class ToolVivado(ActionMakefile):
"""Get version from Xilinx Vivado binary program"""
return 'unknown'
def _print_syn_tcl(self, top_module, tcl_controls):
def makefile_syn_tcl(self, top_module, tcl_controls):
"""Create a Xilinx Vivado project"""
tmp = "set_property {0} {1} [{2}]"
syn_device = top_module.manifest_dict["syn_device"]
......@@ -97,9 +97,9 @@ class ToolVivado(ActionMakefile):
for prop in properties:
create_new.append(tmp.format(prop[0], prop[1], prop[2]))
tcl_controls["create"] = "\n".join(create_new)
super(ToolVivado, self)._print_syn_tcl(top_module, tcl_controls)
super(ToolVivado, self).makefile_syn_tcl(top_module, tcl_controls)
def _print_syn_files(self, fileset):
def makefile_syn_files(self, fileset):
"""Create a Xilinx Vivado project"""
self.writeln("define TCL_FILES")
tmp = "add_files -norecurse {0}"
......
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