Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Commits
6bda472d
Commit
6bda472d
authored
Apr 02, 2019
by
Javier D. Garcia-Lasheras
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Fix System Verilog files included on Verilog synthesis list
parent
ba831ab5
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
4 additions
and
1 deletion
+4
-1
make_syn.py
hdlmake/tools/make_syn.py
+4
-1
No files found.
hdlmake/tools/make_syn.py
View file @
6bda472d
...
...
@@ -8,6 +8,8 @@ import string
from
.makefile
import
ToolMakefile
from
hdlmake.util
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
SVFile
def
_check_synthesis_manifest
(
manifest_dict
):
"""Check the manifest contains all the keys for a synthesis project"""
...
...
@@ -114,7 +116,8 @@ endif""")
file_list
=
[]
for
file_aux
in
self
.
fileset
:
if
isinstance
(
file_aux
,
filetype
):
file_list
.
append
(
shell
.
tclpath
(
file_aux
.
rel_path
()))
if
not
(
filetype
==
VerilogFile
and
isinstance
(
file_aux
,
SVFile
)):
file_list
.
append
(
shell
.
tclpath
(
file_aux
.
rel_path
()))
if
not
file_list
==
[]:
ret
.
append
(
'SOURCES_{0} :=
\\\n
'
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment