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Hdlmake
Commit 6bda472d authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Fix System Verilog files included on Verilog synthesis list

parent ba831ab5
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Showing with 4 additions and 1 deletion
hdlmake/tools/make_syn.py
View file @ 6bda472d
...@@ -8,6 +8,8 @@ import string ...@@ -8,6 +8,8 @@ import string
from .makefile import ToolMakefile from .makefile import ToolMakefile
from hdlmake.util import shell from hdlmake.util import shell
from hdlmake.srcfile import VerilogFile, SVFile
def _check_synthesis_manifest(manifest_dict): def _check_synthesis_manifest(manifest_dict):
"""Check the manifest contains all the keys for a synthesis project""" """Check the manifest contains all the keys for a synthesis project"""
...@@ -114,7 +116,8 @@ endif""") ...@@ -114,7 +116,8 @@ endif""")
file_list = [] file_list = []
for file_aux in self.fileset: for file_aux in self.fileset:
if isinstance(file_aux, filetype): if isinstance(file_aux, filetype):
file_list.append(shell.tclpath(file_aux.rel_path())) if not (filetype == VerilogFile and isinstance(file_aux, SVFile)):
file_list.append(shell.tclpath(file_aux.rel_path()))
if not file_list == []: if not file_list == []:
ret.append( ret.append(
'SOURCES_{0} := \\\n' 'SOURCES_{0} := \\\n'
......
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